Pipelined RISC-V Processor

Implementation of the orginal pipelined version of a RISC-V processor

The pipeline implementation of a RISC-V processor with data forwarding techniques to overcome data hazards.

Name		Name	Last commit message	Last commit date
Latest commit History 5 Commits
ALU_64_bit.v		ALU_64_bit.v
ALU_Control.v		ALU_Control.v
Control_Unit.v		Control_Unit.v
Data_memory.v		Data_memory.v
EX_MEM.v		EX_MEM.v
Figure1.jpg		Figure1.jpg
Forwarding_Unit.v		Forwarding_Unit.v
ID_EX.v		ID_EX.v
ID_EX.v.bak		ID_EX.v.bak
IF_ID.v		IF_ID.v
Instruction_Memory.v		Instruction_Memory.v
MEM_WB.v		MEM_WB.v
Program_Counter.v		Program_Counter.v
README.md		README.md
RISC_V_Pipelined.v		RISC_V_Pipelined.v
RISC_V_Processor.v		RISC_V_Processor.v
adder.v		adder.v
immediate_data.v		immediate_data.v
instruction_parser.v		instruction_parser.v
multiplexer.v		multiplexer.v
mux_4_in.v		mux_4_in.v
registerFile.v		registerFile.v
run.do		run.do
tb.v		tb.v
vsim.wlf		vsim.wlf
wave.do		wave.do

mazy1998/RISC-V-Processor