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RPMPv3.qsf
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RPMPv3.qsf
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# -------------------------------------------------------------------------- #
#
# Copyright (C) 2017 Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Intel Program License
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel FPGA IP License Agreement, or other applicable license
# agreement, including, without limitation, that your use is for
# the sole purpose of programming logic devices manufactured by
# Intel and sold by Intel or its authorized distributors. Please
# refer to the applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 17.1.0 Build 590 10/25/2017 SJ Lite Edition
# Date created = 19:09:52 April 21, 2018
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# RPMPv3_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus Prime software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
set_global_assignment -name FAMILY "MAX II"
set_global_assignment -name DEVICE EPM240T100C5
set_global_assignment -name TOP_LEVEL_ENTITY RPMPv3
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 17.1.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "19:09:52 APRIL 21, 2018"
set_global_assignment -name LAST_QUARTUS_VERSION "17.1.0 Lite Edition"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 100
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR "-1"
set_global_assignment -name POWER_EXT_SUPPLY_VOLTAGE_TO_REGULATOR 3.3V
set_global_assignment -name EDA_SIMULATION_TOOL "<None>"
set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
set_global_assignment -name EDA_RUN_TOOL_AUTOMATICALLY OFF -section_id eda_simulation
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT NONE -section_id eda_simulation
set_global_assignment -name QIP_FILE osc.qip
set_global_assignment -name VERILOG_FILE RPMPv3.v
set_global_assignment -name NUM_PARALLEL_PROCESSORS 4
set_location_assignment PIN_17 -to clk
set_location_assignment PIN_77 -to r[0]
set_location_assignment PIN_78 -to r[1]
set_location_assignment PIN_99 -to r[2]
set_location_assignment PIN_98 -to r[3]
set_location_assignment PIN_96 -to r[4]
set_location_assignment PIN_76 -to r[5]
set_location_assignment PIN_74 -to r[6]
set_location_assignment PIN_81 -to r[7]
set_location_assignment PIN_83 -to r[8]
set_location_assignment PIN_84 -to r[9]
set_location_assignment PIN_86 -to r[10]
set_location_assignment PIN_82 -to r[11]
set_location_assignment PIN_75 -to r[12]
set_location_assignment PIN_73 -to r[13]
set_location_assignment PIN_97 -to r[14]
set_location_assignment PIN_95 -to r[15]
set_instance_assignment -name AUTO_CLOCK_ENABLE_RECOGNITION ON -to clk
set_location_assignment PIN_4 -to led[0]
set_location_assignment PIN_5 -to led[1]
set_location_assignment PIN_6 -to led[2]
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "NO HEAT SINK WITH STILL AIR"
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS OFF
set_instance_assignment -name VIRTUAL_PIN ON -to osc_sig
set_location_assignment PIN_70 -to RATN
set_location_assignment PIN_90 -to ATN
set_location_assignment PIN_85 -to ACK
set_location_assignment PIN_72 -to rs[0]
set_location_assignment PIN_91 -to rs[1]
set_location_assignment PIN_92 -to rs[2]
set_location_assignment PIN_71 -to rs[3]
set_location_assignment PIN_14 -to zclk
set_location_assignment PIN_62 -to zmreq
set_location_assignment PIN_64 -to ziorq
set_location_assignment PIN_67 -to msltsl
set_location_assignment PIN_57 -to zrst
set_location_assignment PIN_58 -to zrd
set_location_assignment PIN_61 -to zwr
set_location_assignment PIN_20 -to cd
set_location_assignment PIN_21 -to ad
set_location_assignment PIN_36 -to a[0]
set_location_assignment PIN_38 -to a[1]
set_location_assignment PIN_34 -to a[2]
set_location_assignment PIN_30 -to a[3]
set_location_assignment PIN_26 -to a[4]
set_location_assignment PIN_28 -to a[5]
set_location_assignment PIN_40 -to a[6]
set_location_assignment PIN_42 -to a[7]
set_location_assignment PIN_52 -to a[8]
set_location_assignment PIN_53 -to a[9]
set_location_assignment PIN_50 -to a[10]
set_location_assignment PIN_51 -to a[11]
set_location_assignment PIN_48 -to a[12]
set_location_assignment PIN_49 -to a[13]
set_location_assignment PIN_54 -to a[14]
set_location_assignment PIN_55 -to a[15]
set_location_assignment PIN_41 -to d[0]
set_location_assignment PIN_43 -to d[1]
set_location_assignment PIN_37 -to d[2]
set_location_assignment PIN_39 -to d[3]
set_location_assignment PIN_33 -to d[4]
set_location_assignment PIN_35 -to d[5]
set_location_assignment PIN_27 -to d[6]
set_location_assignment PIN_29 -to d[7]
set_location_assignment PIN_44 -to dd
set_location_assignment PIN_1 -to zwait
set_location_assignment PIN_2 -to zint
set_location_assignment PIN_3 -to mbd
set_location_assignment PIN_68 -to cmd[0]
set_location_assignment PIN_88 -to cmd[1]
set_instance_assignment -name D1_FINE_DELAY ON -to a[*]
set_instance_assignment -name SYNCHRONIZER_TOGGLE_RATE 0 -to r[*]
set_instance_assignment -name SAFE_STATE_MACHINE ON -to msltsl