Merge pull request #9 from srivatsan-ramesh/dev

partial verilator_top module
meetps · Aug 17, 2016 · 8a2c342 · 8a2c342
2 parents a9ba0f4 + 1ecb17c
commit 8a2c342
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diff --git a/riscv/core.py b/riscv/core.py
@@ -1,52 +1,52 @@
-from myhdl import block, intbv, instances
+from myhdl import instance, delay
 
 from riscv.csr_file import *
 from riscv.hasti_bridge import *
 from riscv.pipeline import pipeline
 
 
 @block
-def vscale_core(clock,
-                ext_interrupts,
-                imem_haddr,
-                imem_hwrite,
-                imem_hsize,
-                imem_hburst,
-                imem_hmastlock,
-                imem_hprot,
-                imem_htrans,
-                imem_hwdata,
-                imem_hrdata,
-                imem_hready,
-                imem_hresp,
-                dmem_haddr,
-                dmem_hwrite,
-                dmem_hsize,
-                dmem_hburst,
-                dmem_hmastlock,
-                dmem_hprot,
-                dmem_htrans,
-                dmem_hwdata,
-                dmem_hrdata,
-                dmem_hready,
-                dmem_hresp,
-                htif_reset,
-                htif_id,
-                htif_pcr_req_valid,
-                htif_pcr_req_ready,
-                htif_pcr_req_rw,
-                htif_pcr_req_addr,
-                htif_pcr_req_data,
-                htif_pcr_resp_valid,
-                htif_pcr_resp_ready,
-                htif_pcr_resp_data,
-                htif_ipi_req_ready,
-                htif_ipi_req_valid,
-                htif_ipi_req_data,
-                htif_ipi_resp_ready,
-                htif_ipi_resp_data,
-                htif_ipi_resp_valid,
-                htif_debug_stats_pcr):
+def core(clock,
+         ext_interrupts,
+         imem_haddr,
+         imem_hwrite,
+         imem_hsize,
+         imem_hburst,
+         imem_hmastlock,
+         imem_hprot,
+         imem_htrans,
+         imem_hwdata,
+         imem_hrdata,
+         imem_hready,
+         imem_hresp,
+         dmem_haddr,
+         dmem_hwrite,
+         dmem_hsize,
+         dmem_hburst,
+         dmem_hmastlock,
+         dmem_hprot,
+         dmem_htrans,
+         dmem_hwdata,
+         dmem_hrdata,
+         dmem_hready,
+         dmem_hresp,
+         htif_reset,
+         htif_id,
+         htif_pcr_req_valid,
+         htif_pcr_req_ready,
+         htif_pcr_req_rw,
+         htif_pcr_req_addr,
+         htif_pcr_req_data,
+         htif_pcr_resp_valid,
+         htif_pcr_resp_ready,
+         htif_pcr_resp_data,
+         htif_ipi_req_ready,
+         htif_ipi_req_valid,
+         htif_ipi_req_data,
+         htif_ipi_resp_ready,
+         htif_ipi_resp_data,
+         htif_ipi_resp_valid,
+         htif_debug_stats_pcr):
     """
     Vscale : Core module assembly
     """
@@ -64,12 +64,13 @@ def vscale_core(clock,
     dmem_rdata = Signal(intbv(0)[HASTI_BUS_WIDTH:0])
     dmem_badmem_e = Signal(intbv(0)[1:])
 
-    @always_comb
+    @instance
     def assign():
         htif_ipi_req_valid.next = intbv(0)[1:]
         htif_ipi_req_data.next = intbv(0)[1:]
         htif_ipi_resp_ready.next = intbv(1)[1:]
         htif_debug_stats_pcr.next = intbv(0)[1:]
+        yield delay(1)
 
     imem_bridge = hasti_bridge(haddr=imem_haddr,
                                hwrite=imem_hwrite,

diff --git a/riscv/csr_file.py b/riscv/csr_file.py
@@ -115,14 +115,21 @@ def csr_setup():
         ie.next = priv_stack[0]
 
         host_wen.next = (htif_state == HTIF_STATE_IDLE) & htif_pcr_req_valid & htif_pcr_req_rw
-        system_en.next = cmd[2]
         system_wen.next = cmd[1] | cmd[0]
-        wen_internal.next = host_wen | system_wen
 
-        illegal_region.next = (system_wen & (addr[12:10] == 3)) | (system_en & addr[10:8] > prv)
         illegal_access.next = illegal_region | (system_en & ~defined)
 
         wdata_internal.next = wdata
+
+    @always_comb
+    def assign_1():
+        system_en.next = cmd[2]
+
+    @always_comb
+    def assign_2():
+
+        illegal_region.next = (system_wen & (addr[12:10] == 3)) | (system_en & addr[10:8] > prv)
+        wen_internal.next = host_wen | system_wen
         if host_wen:
             wdata_internal.next = htif_pcr_req_data
         elif system_wen:
@@ -418,4 +425,4 @@ def csr_seq_logic():
             if htif_fire & htif_pcr_req_addr == CSR_ADDR_TO_HOST & ~system_wen:
                 to_host.next = 0
 
-    return instances
+    return instances()
diff --git a/riscv/dp_hasti_sram.py b/riscv/dp_hasti_sram.py
@@ -1,4 +1,4 @@
-from myhdl import block, intbv, instances, concat
+from myhdl import block, intbv, instances, concat, Signal, always, always_comb
 from riscv.hasti_constants import *
 
 
@@ -23,7 +23,7 @@ def dp_hasti_sram(hclk,
                   p1_hmastlock,
                   p1_hprot,
                   p1_htrans,
-                  p1_hwdata,
+                  p1_hrdata,
                   p1_hready,
                   p1_hresp):
     """
@@ -34,32 +34,43 @@ def dp_hasti_sram(hclk,
     s_w1 = 0
     s_w2 = 1
 
-    mem = [intbv(0)[HASTI_BUS_WIDTH:] for i in range(nwords - 1)]
+    mem = [intbv(0)[HASTI_BUS_WIDTH:] for _ in range(nwords - 1)]
 
     p0_waddr = Signal(intbv(0)[HASTI_ADDR_WIDTH:])
     p0_wdata = Signal(intbv(0)[HASTI_BUS_WIDTH:])
     p0_wvalid = Signal(intbv(0)[1:])
     p0_wsize = Signal(intbv(0)[HASTI_SIZE_WIDTH:])
     p0_state = Signal(intbv(0)[1:])
+    p0_wmask_lut = Signal(intbv(0)[HASTI_BUS_NBYTES:])
+    p0_wmask_shift = Signal(intbv(0)[HASTI_BUS_NBYTES:])
+    p0_word_waddr = Signal(intbv(0)[HASTI_BUS_NBYTES:])
+    p0_wmask = Signal(intbv(0)[HASTI_BUS_WIDTH:])
+    p0_raddr = Signal(intbv(0)[HASTI_ADDR_WIDTH:])
+    p0_ren = Signal(intbv(0)[1:])
 
-    if p0_wsize == 0:
-        p0_wmask_lut.next = intbv(0x1)[HASTI_BUS_NBYTES:]
-    elif p0_wsize == 1:
-        p0_wmask_lut.next = intbv(0x3)[HASTI_BUS_NBYTES:]
-    else:
-        p0_wmask_lut.next = intbv(0xf)[HASTI_BUS_NBYTES:]
+    @always_comb
+    def assign_1():
+        if p0_wsize == 0:
+            p0_wmask_lut.next = intbv(0x1)[HASTI_BUS_NBYTES:]
+        elif p0_wsize == 1:
+            p0_wmask_lut.next = intbv(0x3)[HASTI_BUS_NBYTES:]
+        else:
+            p0_wmask_lut.next = intbv(0xf)[HASTI_BUS_NBYTES:]
 
-    wmask_concat = concat(intbv(p0_wmask_shift[3])[8:],
-                          intbv(p0_wmask_shift[2])[8:],
-                          intbv(p0_wmask_shift[1])[8:],
-                          intbv(p0_wmask_shift[0])[8:])
-    p0_wmask = Signal(intbv(wmask_concat)[HASTI_BUS_WIDTH:])
 
-    p0_wmask_shift = Signal(intbv(p0_wmask_lut << p0_waddr[1:0])[HASTI_BUS_NBYTES:])
-    p0_word_waddr = Signal(intbv(p0_waddr >> 2)[HASTI_ADDR_WIDTH:])
+    @always_comb
+    def assign_2():
+        p0_wmask.next = concat(*[p0_wmask_shift[3] for _ in range(8)],
+                               *[p0_wmask_shift[2] for _ in range(8)],
+                               *[p0_wmask_shift[1] for _ in range(8)],
+                               *[p0_wmask_shift[0] for _ in range(8)])
+    @always_comb
+    def assign_3():
+        p0_wmask_shift.next = p0_wmask_lut << p0_waddr[2:0]
+        p0_word_waddr.next = p0_waddr >> 2
+        p0_raddr.next = p0_haddr >> 2
+        p0_ren.next = p0_htrans == HASTI_TRANS_NONSEQ and not p0_hwrite
 
-    p0_raddr = Signal(intbv(p0_haddr >> 2)[HASTI_ADDR_WIDTH:])
-    p0_ren = Signal(intbv(p0_htrans == HASTI_TRANS_NONSEQ and not p0_hwrite)[1:])
     p0_bypass = Signal(intbv(0)[1:])
     p0_reg_raddr = Signal(intbv(0)[HASTI_ADDR_WIDTH:])
 
@@ -74,28 +85,39 @@ def p0():
             p0_wdata.next = intbv(0)[1:]
             p0_reg_raddr.next = intbv(0)[1:]
         else:
-            if (p0_state == s_w2):
+            if p0_state == s_w2:
                 p0_wdata.next = p0_hwdata
                 p0_state.next = s_w1
-            if (p0_htrans == HASTI_TRANS_NONSEQ):
+            if p0_htrans == HASTI_TRANS_NONSEQ:
                 if p0_hwrite:
                     p0_waddr.next = p0_haddr
                     p0_wsize.next = p0_hsize
                     p0_wvalid.next = intbv(1)[1:]
-                    if (p0_wvalid):
+                    if p0_wvalid:
                         mem[p0_word_waddr] = (mem[p0_word_waddr] & (not p0_wmask)) | (p0_wdata & p0_wmask)
                     p0_state.next = s_w2
                 else:
-                    p0_bypass.next = p0_wvalid & p0_word_waddr == p0_raddr
+                    p0_bypass.next = p0_wvalid and p0_word_waddr == p0_raddr
+
+    p0_rdata = Signal(intbv(0)[HASTI_BUS_WIDTH:])
+    p0_rmask = Signal(intbv(0)[HASTI_BUS_WIDTH:])
+
+    @always_comb
+    def assign_3():
+        p0_hrdata.next = (p0_wdata & p0_rmask) | (p0_rdata & (not p0_rmask))
+        p0_hready.next = 1
+        p0_hresp.next = HASTI_RESP_OKAY
 
-    p0_rdata = Signal(intbv(mem[p0_reg_raddr])[HASTI_BUS_WIDTH:])
-    p0_hrdata = (p0_wdata & p0_rmask) | (p0_rdata & (not p0_rmask))
-    p0_hready = Signal(intbv(1)[1:])
-    p0_rmask = Signal(intbv(intbv(p0_bypass)[32:] & p0_wmask)[HASTI_BUS_WIDTH:])
-    p0_hresp = HASTI_RESP_OKAY
+    p1_raddr = Signal(intbv(0)[HASTI_ADDR_WIDTH:])
+    p1_ren = Signal(intbv(0)[1:])
+
+    @always_comb
+    def assign_4():
+        p0_rmask.next = concat(*[p0_bypass for _ in range(32)]) & p0_wmask
+        p0_rdata.next = mem[p0_reg_raddr]
+        p1_raddr.next = p1_haddr >> 2
+        p1_ren.next = p1_htrans == HASTI_TRANS_NONSEQ and not p1_hwrite
 
-    p1_raddr = Signal(intbv(p1_haddr >> 2)[HASTI_ADDR_WIDTH:])
-    p1_ren = Signal(intbv((p1_htrans == HASTI_TRANS_NONSEQ & (not p1_hwrite)))[1:])
     p1_bypass = Signal(intbv(0)[1:])
     p1_reg_raddr = Signal(intbv(0)[HASTI_ADDR_WIDTH:])
 
@@ -111,10 +133,18 @@ def p1():
                 else:
                     p1_bypass.next = p0_wvalid & p0_word_waddr == p1_raddr
 
-    p1_rdata = Signal(intbv(mem[p1_reg_raddr])[HASTI_BUS_WIDTH:])
-    p1_rmask = Signal(intbv(intbv(p1_bypass)[32:] and p0_wmask)[HASTI_BUS_WIDTH:])
-    p1_hrdata = (p0_wdata & p1_rmask) | (p1_rdata & (not p1_rmask))
-    p1_hready = Signal(intbv(1)[1:])
-    p1_hresp = Signal(intbv(HASTI_RESP_OKAY)[1:])
+    p1_rdata = Signal(intbv(0)[HASTI_BUS_WIDTH:])
+    p1_rmask = Signal(intbv(0)[HASTI_BUS_WIDTH:])
+
+    @always_comb
+    def assign_5():
+        p1_rdata.next = mem[p1_reg_raddr]
+        p1_rmask.next = concat(*[p1_bypass for _ in range(32)]) and p0_wmask
+        p1_hready.next = Signal(intbv(1)[1:])
+        p1_hresp.next = Signal(intbv(HASTI_RESP_OKAY)[1:])
+
+    @always_comb
+    def assign_6():
+        p1_hrdata.next = (p0_wdata & p1_rmask) | (p1_rdata & (not p1_rmask))
 
     return instances()
diff --git a/riscv/pipeline.py b/riscv/pipeline.py
@@ -21,7 +21,6 @@ def pipeline(clock, ext_interrupts, reset, imem_wait, imem_addr, imem_rdata, ime
              dmem_wen, dmem_size, dmem_addr, dmem_wdata_delayed, dmem_rdata, dmem_badmem_e, htif_reset,
              htif_pcr_req_valid, htif_pcr_req_ready, htif_pcr_req_rw, htif_pcr_req_addr, htif_pcr_req_data,
              htif_pcr_resp_valid, htif_pcr_resp_ready, htif_pcr_resp_data):
-
     """
     The Pipeline Module
 
@@ -155,13 +154,13 @@ def load_data(address, data, mem_type):
     eret = Signal(False)
     epc = Signal(intbv(0)[XPR_LEN:])
 
-    controller_inst = controller(clock, reset, inst_DX, imem_wait, imem_badmem_e, dmem_wait, dmem_badmem_e,
-                                 cmp_true, PC_src_sel, imm_type, src_a_sel, src_b_sel, bypass_rs1, bypass_rs2,
-                                 alu_op, dmem_en, dmem_wen, dmem_size, dmem_type,md_req_valid, md_req_ready,
-                                 md_req_op, md_req_in_1_signed, md_req_in_2_signed, md_req_out_sel, md_resp_valid,
-                                 wr_reg_WB, reg_to_wr_WB, wb_src_sel_WB, stall_IF, kill_IF, stall_DX, kill_DX,
-                                 stall_WB, kill_WB, exception_WB, exception_code_WB, retire_WB, csr_cmd,
-                                 csr_imm_sel, illegal_csr_access, interrupt_pending, interrupt_taken, prv, eret)
+    controller_inst = controller(clock, reset, inst_DX, imem_wait, imem_badmem_e, dmem_wait, dmem_badmem_e, cmp_true,
+                                 prv, PC_src_sel, imm_type, bypass_rs1, bypass_rs2, src_a_sel, src_b_sel, alu_op,
+                                 dmem_en, dmem_wen, dmem_size, dmem_type, md_req_valid, md_req_ready,
+                                 md_req_in_1_signed, md_req_in_2_signed, md_req_op, md_req_out_sel, md_resp_valid,
+                                 eret, csr_cmd, csr_imm_sel, illegal_csr_access, interrupt_pending, interrupt_taken,
+                                 wr_reg_WB, reg_to_wr_WB, wb_src_sel_WB, stall_IF, kill_IF, stall_DX, kill_DX, stall_WB,
+                                 kill_WB, exception_WB, exception_code_WB, retire_WB)
 
     pc_mux_inst = PC_mux(PC_src_sel, inst_DX, rs1_data_bypassed, PC_IF, PC_DX, handler_PC, epc, PC_PIF)
 
@@ -215,7 +214,7 @@ def assign_3():
     alu_inst = alu(alu_op, alu_src_a, alu_src_b, alu_out)
 
     md_inst = mult_div(clock, reset, md_req_valid, md_req_ready, md_req_in_1_signed, md_req_in_2_signed, md_req_out_sel,
-                      md_req_op, rs1_data_bypassed, rs2_data_bypassed, md_resp_valid, md_resp_result)
+                       md_req_op, rs1_data_bypassed, rs2_data_bypassed, md_resp_valid, md_resp_result)
 
     @always_comb
     def assign_4():
@@ -265,7 +264,7 @@ def assign_6():
     csr_file_inst = csr_file(clock, ext_interrupts, reset, csr_addr, csr_cmd, csr_wdata, prv, illegal_csr_access,
                              csr_rdata, retire_WB, exception_WB, exception_code_WB, alu_out_WB, PC_WB, epc, eret,
                              handler_PC, interrupt_pending, interrupt_taken, htif_reset, htif_pcr_req_valid,
-                             htif_pcr_req_ready, htif_pcr_req_rw, htif_pcr_req_rw, htif_pcr_req_addr, htif_pcr_req_data,
+                             htif_pcr_req_ready, htif_pcr_req_rw, htif_pcr_req_addr, htif_pcr_req_data,
                              htif_pcr_resp_valid, htif_pcr_resp_ready, htif_pcr_resp_data)
 
     return instances()