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Makefile
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Makefile
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# List of variables
SHELL = /bin/bash
CC = gcc
CFLAGS = -Wall -Werror -Wextra -pedantic -std=gnu89 -g
# name of the executable
NAME = hsh
# Find all c files in current directory and substitute
# extension with object files (.o)
OBJ = $(patsubst %.c,%.o, $(wildcard *.c))
HEADERS = $(wildcard *.h)
LINTER = betty
# Main directive
all: $(NAME)
# Compile executable from object files
$(NAME): $(OBJ) $(HEADERS)
$(CC) -o $@ $^ $(CFLAGS)
.PHONY: clean, run, check, memcheck, memfull, test
clean:
rm -f *.o $(NAME)
# Compile and run command, @ means do not print info
run: all
@./$(NAME)
check:
@$(LINTER) *.[ch]
memcheck: all
@valgrind ./$(NAME)
memfull: all
@valgrind --leak-check=full --track-origins=yes ./$(NAME)
test: all
cp $(NAME) shell_v2_checker/ && cd shell_v2_checker && ./start.bash
crun: clean, all
@./$(NAME)