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X86MachineInstructionRaiser.cpp
3562 lines (3271 loc) · 141 KB
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X86MachineInstructionRaiser.cpp
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//===-- X86MachineInstructionRaiser.cpp -------------------------*- C++ -*-===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
// This file contains the implementation of X86MachineInstructionRaiser class
// for use by llvm-mctoll.
//
//===----------------------------------------------------------------------===//
#include "X86MachineInstructionRaiser.h"
#include "ExternalFunctions.h"
#include "MachineFunctionRaiser.h"
#include "X86InstrBuilder.h"
#include "X86ModuleRaiser.h"
#include "X86RaisedValueTracker.h"
#include "X86RegisterUtils.h"
#include "llvm-mctoll.h"
#include "llvm/ADT/DepthFirstIterator.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/CodeGen/LivePhysRegs.h"
#include "llvm/CodeGen/LoopTraversal.h"
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineJumpTableInfo.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/CodeGen/TargetRegisterInfo.h"
#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/IR/Instructions.h"
#include "llvm/Support/raw_ostream.h"
#include "llvm/Target/TargetMachine.h"
#include <set>
#include <vector>
using namespace llvm;
using namespace mctoll;
using namespace X86RegisterUtils;
// Constructor
X86MachineInstructionRaiser::X86MachineInstructionRaiser(MachineFunction &MF,
const ModuleRaiser *MR,
MCInstRaiser *MIR)
: MachineInstructionRaiser(MF, MR, MIR), machineRegInfo(MF.getRegInfo()),
x86TargetInfo(MF.getSubtarget<X86Subtarget>()) {
x86InstrInfo = x86TargetInfo.getInstrInfo();
x86RegisterInfo = x86TargetInfo.getRegisterInfo();
PrintPass =
(cl::getRegisteredOptions()["print-after-all"]->getNumOccurrences() > 0);
FPUStack.TOP = 0;
for (int i = 0; i < FPUSTACK_SZ; i++)
FPUStack.Regs[i] = nullptr;
raisedValues = nullptr;
}
bool X86MachineInstructionRaiser::raisePushInstruction(const MachineInstr &mi) {
const MCInstrDesc &MCIDesc = mi.getDesc();
uint64_t MCIDTSFlags = MCIDesc.TSFlags;
if ((MCIDTSFlags & X86II::FormMask) == X86II::AddRegFrm) {
// This is a register PUSH. If the source is register, create a slot on
// the stack.
if (mi.getOperand(0).isReg()) {
const DataLayout &DL = MR->getModule()->getDataLayout();
unsigned AllocaAddrSpace = DL.getAllocaAddrSpace();
// Create alloca instruction to allocate stack slot
Type *Ty = getPhysRegOperandType(mi, 0);
AllocaInst *Alloca =
new AllocaInst(Ty, AllocaAddrSpace, 0, DL.getPrefTypeAlignment(Ty));
// Create a stack slot associated with the alloca instruction
unsigned int StackFrameIndex = MF.getFrameInfo().CreateStackObject(
(Ty->getPrimitiveSizeInBits() / 8), DL.getPrefTypeAlignment(Ty),
false /* isSpillSlot */, Alloca);
// Compute size of new stack object.
const MachineFrameInfo &MFI = MF.getFrameInfo();
// Size of currently allocated object size
int64_t ObjectSize = MFI.getObjectSize(StackFrameIndex);
// Get the offset of the top of stack. Note that stack objects in MFI are
// not sorted by offset. So we need to walk the stack objects to find the
// offset of the top stack object.
int64_t StackTopOffset = 0;
for (int StackIndex = MFI.getObjectIndexBegin();
StackIndex < MFI.getObjectIndexEnd(); StackIndex++) {
int64_t ObjOffset = MFI.getObjectOffset(StackIndex);
if (ObjOffset < StackTopOffset)
StackTopOffset = ObjOffset;
}
int64_t Offset = StackTopOffset - ObjectSize;
// Set object size.
MF.getFrameInfo().setObjectOffset(StackFrameIndex, Offset);
// Add the alloca instruction to entry block
insertAllocaInEntryBlock(Alloca);
// The alloca corresponds to the current location of stack pointer
raisedValues->setPhysRegSSAValue(X86::RSP, mi.getParent()->getNumber(),
Alloca);
return true;
} else {
assert(false && "Unhandled PUSH instruction with a non-register operand");
}
} else {
assert(false && "Unhandled PUSH instruction with source operand other "
"than AddrRegFrm");
}
return false;
}
bool X86MachineInstructionRaiser::raisePopInstruction(const MachineInstr &mi) {
// TODO : Need to handle pop instructions other than those that restore bp
// from stack.
const MCInstrDesc &MCIDesc = mi.getDesc();
uint64_t MCIDTSFlags = MCIDesc.TSFlags;
if ((MCIDTSFlags & X86II::FormMask) == X86II::AddRegFrm) {
// This is a register POP. If the source is base pointer,
// not need to raise the instruction.
if (mi.definesRegister(X86::RBP) || mi.definesRegister(X86::EBP)) {
return true;
} else {
// assert(false && "Unhandled POP instruction that restores a register
// "
// "other than frame pointer");
return true;
}
} else {
if (getInstructionKind(mi.getOpcode()) == InstructionKind::LEAVE_OP) {
return true;
}
assert(false && "Unhandled POP instruction with source operand other "
"than AddrRegFrm");
}
return false;
}
bool X86MachineInstructionRaiser::raiseConvertBWWDDQMachineInstr(
const MachineInstr &MI) {
const MCInstrDesc &MIDesc = MI.getDesc();
unsigned int Opcode = MI.getOpcode();
LLVMContext &llvmContext(MF.getFunction().getContext());
assert(MIDesc.getNumImplicitUses() == 1 && MIDesc.getNumImplicitDefs() == 1 &&
"Unexpected number of implicit uses and defs in cbw/cwde/cdqe "
"instruction");
// Get the BasicBlock corresponding to MachineBasicBlock of MI.
// Raised instruction is added to this BasicBlock.
BasicBlock *RaisedBB = getRaisedBasicBlock(MI.getParent());
MCPhysReg UseReg = MIDesc.ImplicitUses[0];
MCPhysReg DefReg = MIDesc.ImplicitDefs[0];
Type *TargetTy = nullptr;
if (Opcode == X86::CDQE) {
assert(is32BitPhysReg(UseReg) &&
"Unexpected non-32-bit register in cdqe instruction");
assert(is64BitPhysReg(DefReg) &&
"Unexpected non-64-bit register in cdqe instruction");
TargetTy = Type::getInt64Ty(llvmContext);
} else if (Opcode == X86::CBW) {
assert(is8BitPhysReg(UseReg) &&
"Unexpected non-32-bit register in cbw instruction");
assert(is16BitPhysReg(DefReg) &&
"Unexpected non-64-bit register in cbw instruction");
TargetTy = Type::getInt16Ty(llvmContext);
} else if (Opcode == X86::CWDE) {
assert(is16BitPhysReg(UseReg) &&
"Unexpected non-32-bit register in cwde instruction");
assert(is32BitPhysReg(DefReg) &&
"Unexpected non-64-bit register in cwde instruction");
TargetTy = Type::getInt32Ty(llvmContext);
}
assert(TargetTy != nullptr &&
"Target type not set for cbw/cwde/cdqe instruction");
Value *UseValue = getRegOperandValue(
MI, MI.findRegisterUseOperandIdx(UseReg, false, nullptr));
// Generate sign-extend instruction
SExtInst *SextInst = new SExtInst(UseValue, TargetTy);
RaisedBB->getInstList().push_back(SextInst);
// Update the value mapping of DefReg
raisedValues->setPhysRegSSAValue(DefReg, MI.getParent()->getNumber(),
SextInst);
return true;
}
bool X86MachineInstructionRaiser::raiseConvertWDDQQOMachineInstr(
const MachineInstr &MI) {
const MCInstrDesc &MIDesc = MI.getDesc();
unsigned int Opcode = MI.getOpcode();
LLVMContext &Ctx(MF.getFunction().getContext());
assert(MIDesc.getNumImplicitUses() == 1 && MIDesc.getNumImplicitDefs() == 2 &&
"Unexpected number of implicit uses and defs in cwd/cdq/cqo "
"instruction");
// Get the BasicBlock corresponding to MachineBasicBlock of MI.
// Raised instruction is added to this BasicBlock.
BasicBlock *RaisedBB = getRaisedBasicBlock(MI.getParent());
MCPhysReg UseReg = MIDesc.ImplicitUses[0];
MCPhysReg DefReg_0 = MIDesc.ImplicitDefs[0];
MCPhysReg DefReg_1 = MIDesc.ImplicitDefs[1];
Type *TargetTy = nullptr;
Type *UseRegTy = nullptr;
if (Opcode == X86::CWD) {
assert(is16BitPhysReg(UseReg) && is16BitPhysReg(DefReg_0) &&
is16BitPhysReg(DefReg_1) && (UseReg == DefReg_0) &&
"Unexpected characteristics of use/def registers in cwd "
"instruction");
TargetTy = Type::getInt32Ty(Ctx);
UseRegTy = Type::getInt16Ty(Ctx);
} else if (Opcode == X86::CDQ) {
assert(is32BitPhysReg(UseReg) && is32BitPhysReg(DefReg_0) &&
is32BitPhysReg(DefReg_1) && (UseReg == DefReg_0) &&
"Unexpected characteristics of use/def registers in cdq "
"instruction");
TargetTy = Type::getInt64Ty(Ctx);
UseRegTy = Type::getInt32Ty(Ctx);
} else if (Opcode == X86::CQO) {
assert(is64BitPhysReg(UseReg) && is16BitPhysReg(DefReg_0) &&
is64BitPhysReg(DefReg_1) && (UseReg == DefReg_0) &&
"Unexpected characteristics of use/def registers in cdo "
"instruction");
TargetTy = Type::getInt128Ty(Ctx);
UseRegTy = Type::getInt64Ty(Ctx);
}
assert((TargetTy != nullptr) && (UseRegTy != nullptr) &&
"Target type not set for cwd/cdq/cqo instruction");
Value *UseValue = getRegOrArgValue(UseReg, MI.getParent()->getNumber());
// Generate sign-extend instruction
SExtInst *TargetSextInst = new SExtInst(UseValue, TargetTy);
assert(UseValue->getType()->getScalarSizeInBits() ==
UseRegTy->getScalarSizeInBits() &&
"Mismatched types in cwd/cdq/cqo instruction");
RaisedBB->getInstList().push_back(TargetSextInst);
// Logical Shift TargetSextInst by n-bits (where n is the size of
// UserRegTy) to get the high bytes and set DefReg_1 to the resulting
// value.
Value *ShiftAmount = ConstantInt::get(
TargetTy, UseRegTy->getScalarSizeInBits(), false /* isSigned */);
Instruction *LShrInst =
BinaryOperator::CreateLShr(TargetSextInst, ShiftAmount);
RaisedBB->getInstList().push_back(LShrInst);
// Truncate LShrInst to get the high bytes
Instruction *HighBytesInst =
CastInst::Create(Instruction::Trunc, LShrInst, UseRegTy);
RaisedBB->getInstList().push_back(HighBytesInst);
// Update the value mapping of DefReg_1
raisedValues->setPhysRegSSAValue(DefReg_1, MI.getParent()->getNumber(),
HighBytesInst);
return true;
}
bool X86MachineInstructionRaiser::raiseMoveImmToRegMachineInstr(
const MachineInstr &MI) {
unsigned int Opcode = MI.getOpcode();
bool success = false;
switch (Opcode) {
case X86::MOV8ri:
case X86::MOV16ri:
case X86::MOV32ri:
case X86::MOV64ri:
case X86::MOV64ri32: {
unsigned DestOpIndex = 0, SrcOpIndex = 1;
const MachineOperand &DestOp = MI.getOperand(DestOpIndex);
const MachineOperand &SrcOp = MI.getOperand(SrcOpIndex);
assert(MI.getNumExplicitOperands() == 2 && DestOp.isReg() &&
SrcOp.isImm() &&
"Expecting exactly two operands for move imm-to-reg instructions");
unsigned int DstPReg = DestOp.getReg();
int64_t SrcImm = SrcOp.getImm();
Type *ImmTy = getImmOperandType(MI, 1);
Value *SrcValue = ConstantInt::get(ImmTy, SrcImm);
SrcValue = castValue(SrcValue, getPhysRegType(DstPReg),
getRaisedBasicBlock(MI.getParent()));
// Check if the immediate value corresponds to a global variable.
if (SrcImm > 0) {
Value *GV = getGlobalVariableValueAt(MI, SrcImm);
if (GV != nullptr) {
SrcValue = GV;
}
}
// Update the value mapping of dstReg
raisedValues->setPhysRegSSAValue(DstPReg, MI.getParent()->getNumber(),
SrcValue);
success = true;
} break;
default:
assert(false && "Unhandled move imm-to-reg instruction");
break;
}
return success;
}
bool X86MachineInstructionRaiser::raiseMoveRegToRegMachineInstr(
const MachineInstr &MI) {
unsigned int Opcode = MI.getOpcode();
int MBBNo = MI.getParent()->getNumber();
LLVMContext &Ctx(MF.getFunction().getContext());
// Get the BasicBlock corresponding to MachineBasicBlock of MI.
// Raised instruction is added to this BasicBlock.
BasicBlock *RaisedBB = getRaisedBasicBlock(MI.getParent());
bool Success = false;
unsigned DstIndex = 0, Src1Index = 1, Src2Index = 2;
assert(
(MI.getNumExplicitOperands() == 2 || MI.getNumExplicitOperands() == 4) &&
MI.getOperand(DstIndex).isReg() &&
(MI.getOperand(Src1Index).isReg() || MI.getOperand(Src2Index).isReg()) &&
"Expecting exactly two or four operands for move reg-to-reg "
"instructions");
unsigned int DstPReg = MI.getOperand(DstIndex).getReg();
// Get source operand value
Value *SrcValue = nullptr;
if (MI.getNumExplicitOperands() == 2)
SrcValue = getRegOperandValue(MI, Src1Index);
else if (MI.getNumExplicitOperands() == 4)
SrcValue = getRegOperandValue(MI, Src2Index);
else
assert(false &&
"Unexpected operand numbers for move reg-to-reg instruction");
switch (Opcode) {
case X86::MOVSX16rr8:
case X86::MOVSX32rr8:
case X86::MOVSX32rr16:
case X86::MOVSX64rr8:
case X86::MOVSX64rr16:
case X86::MOVSX64rr32:
case X86::MOVZX16rr8:
case X86::MOVZX32rr8:
case X86::MOVZX32rr16:
case X86::MOVZX64rr8:
case X86::MOVZX64rr16: {
Type *Ty = nullptr;
Instruction::CastOps Cast;
// Check for sanity of source value
assert(SrcValue &&
"Encountered instruction with undefined source register");
switch (Opcode) {
case X86::MOVSX16rr8: {
assert(is16BitPhysReg(DstPReg) &&
"Not found expected 16-bit destination register - movsx "
"instruction");
Ty = Type::getInt16Ty(Ctx);
Cast = Instruction::SExt;
} break;
case X86::MOVSX32rr8:
case X86::MOVSX32rr16: {
assert(is32BitPhysReg(DstPReg) &&
"Not found expected 32-bit destination register - movsx "
"instruction");
Ty = Type::getInt32Ty(Ctx);
Cast = Instruction::SExt;
} break;
case X86::MOVSX64rr8:
case X86::MOVSX64rr16:
case X86::MOVSX64rr32: {
assert(is64BitPhysReg(DstPReg) &&
"Not found expected 64-bit destination register - movsx "
"instruction");
Ty = Type::getInt64Ty(Ctx);
Cast = Instruction::SExt;
} break;
case X86::MOVZX16rr8: {
assert(is16BitPhysReg(DstPReg) &&
"Not found expected 16-bit destination register - movsx "
"instruction");
Ty = Type::getInt16Ty(Ctx);
Cast = Instruction::ZExt;
} break;
case X86::MOVZX32rr8:
case X86::MOVZX32rr16: {
assert(is32BitPhysReg(DstPReg) &&
"Not found expected 32-bit destination register - movzx "
"instruction");
Ty = Type::getInt32Ty(Ctx);
Cast = Instruction::ZExt;
} break;
case X86::MOVZX64rr8:
case X86::MOVZX64rr16: {
assert(is64BitPhysReg(DstPReg) &&
"Not found expected 64-bit destination register - movzx "
"instruction");
Ty = Type::getInt64Ty(Ctx);
Cast = Instruction::ZExt;
} break;
default:
assert(false &&
"Should not reach here! - mov with extension instruction");
}
assert(Ty != nullptr &&
"Failed to set type - mov with extension instruction");
// Now create the cast instruction corresponding to the instruction.
CastInst *CInst = CastInst::Create(Cast, SrcValue, Ty);
RaisedBB->getInstList().push_back(CInst);
// Update the value mapping of DstPReg
raisedValues->setPhysRegSSAValue(DstPReg, MBBNo, CInst);
Success = true;
} break;
case X86::MOV64rr:
case X86::MOV32rr:
case X86::MOV16rr:
case X86::MOV8rr: {
unsigned int DstPRegSize = getPhysRegOperandSize(MI, DstIndex);
unsigned int SrcPRegSize = getPhysRegOperandSize(MI, Src1Index);
// Verify sanity of the instruction.
assert(DstPRegSize != 0 && DstPRegSize == SrcPRegSize &&
"Unexpected sizes of source and destination registers size differ "
"in mov instruction");
assert(SrcValue &&
"Encountered mov instruction with undefined source register");
assert(SrcValue->getType()->isSized() &&
"Unsized source value in move instruction");
MachineOperand MO = MI.getOperand(Src1Index);
assert(MO.isReg() && "Unexpected non-register operand");
SrcValue = matchSSAValueToSrcRegSize(MI, MO.getReg());
// Update the value mapping of DstPReg
raisedValues->setPhysRegSSAValue(DstPReg, MBBNo, SrcValue);
Success = true;
} break;
case X86::CMOV16rr:
case X86::CMOV32rr:
case X86::CMOV64rr: {
unsigned int DstPRegSize = getPhysRegOperandSize(MI, DstIndex);
unsigned int SrcPRegSize = getPhysRegOperandSize(MI, Src2Index);
// Verify sanity of the instruction.
assert(DstPRegSize != 0 && DstPRegSize == SrcPRegSize &&
"Unexpected sizes of source and destination registers size differ "
"in cmovcc instruction");
assert(SrcValue &&
"Encountered cmovcc instruction with undefined source register");
assert(SrcValue->getType()->isSized() &&
"Unsized source value in cmovcc instruction");
MachineOperand MO = MI.getOperand(Src2Index);
assert(MO.isReg() && "Unexpected non-register operand");
SrcValue = matchSSAValueToSrcRegSize(MI, MO.getReg());
// Get destination operand value
Value *DstValue = getRegOrArgValue(DstPReg, MBBNo);
Value *TrueValue = ConstantInt::getTrue(Ctx);
Value *FalseValue = ConstantInt::getFalse(Ctx);
CmpInst::Predicate Pred = CmpInst::Predicate::BAD_ICMP_PREDICATE;
Value *CMOVCond = nullptr;
switch (X86::getCondFromCMov(MI)) {
case X86::COND_NE: {
// Check if ZF == 0
Value *ZFValue = getRegOrArgValue(EFLAGS::ZF, MBBNo);
assert(ZFValue != nullptr &&
"Failed to get EFLAGS value while raising CMOVNE!");
Pred = CmpInst::Predicate::ICMP_EQ;
// Construct a compare instruction
CMOVCond = new ICmpInst(Pred, ZFValue, FalseValue, "Cond_CMOVNE");
} break;
case X86::COND_E: {
// Check if ZF == 1
Value *ZFValue = getRegOrArgValue(EFLAGS::ZF, MBBNo);
assert(ZFValue != nullptr &&
"Failed to get EFLAGS value while raising CMOVE!");
Pred = CmpInst::Predicate::ICMP_EQ;
// Construct a compare instruction
CMOVCond = new ICmpInst(Pred, ZFValue, TrueValue, "Cond_CMOVE");
} break;
case X86::COND_A: {
// Check CF == 0 and ZF == 0
Value *CFValue = getRegOrArgValue(EFLAGS::CF, MBBNo);
Value *ZFValue = getRegOrArgValue(EFLAGS::ZF, MBBNo);
assert((CFValue != nullptr) && (ZFValue != nullptr) &&
"Failed to get EFLAGS value while raising CMOVA!");
Pred = CmpInst::Predicate::ICMP_EQ;
// CF or ZF
BinaryOperator *CFZFOrCond =
BinaryOperator::CreateOr(CFValue, ZFValue, "CFZFOR_CMOVA");
RaisedBB->getInstList().push_back(CFZFOrCond);
// Test CF == 0 and ZF == 0
CMOVCond = new ICmpInst(Pred, CFZFOrCond, FalseValue, "Cond_CMOVA");
} break;
case X86::COND_L: {
// Check SF != OF
Value *SFValue = getRegOrArgValue(EFLAGS::SF, MBBNo);
Value *OFValue = getRegOrArgValue(EFLAGS::OF, MBBNo);
assert((SFValue != nullptr) && (OFValue != nullptr) &&
"Failed to get EFLAGS value while raising CMOVL!");
Pred = CmpInst::Predicate::ICMP_NE;
// Test SF != OF
CMOVCond = new ICmpInst(Pred, SFValue, OFValue, "Cond_CMOVL");
} break;
case X86::COND_G: {
// Check ZF == 0 and SF == OF
Value *ZFValue = getRegOrArgValue(EFLAGS::ZF, MBBNo);
Value *SFValue = getRegOrArgValue(EFLAGS::SF, MBBNo);
Value *OFValue = getRegOrArgValue(EFLAGS::OF, MBBNo);
assert((ZFValue != nullptr) && (SFValue != nullptr) &&
(OFValue != nullptr) &&
"Failed to get EFLAGS value while raising CMOVG!");
Pred = CmpInst::Predicate::ICMP_EQ;
// Compare ZF and 0
CmpInst *ZFCond = new ICmpInst(Pred, ZFValue, FalseValue, "ZFCmp_CMOVG");
RaisedBB->getInstList().push_back(ZFCond);
// Test SF == OF
CmpInst *SFOFCond = new ICmpInst(Pred, SFValue, OFValue, "SFOFCmp_CMOVG");
RaisedBB->getInstList().push_back(SFOFCond);
CMOVCond = BinaryOperator::CreateAnd(ZFCond, SFOFCond, "Cond_CMOVG");
} break;
case X86::COND_LE: {
// Check ZF == 1 or SF != OF
Value *ZFValue = getRegOrArgValue(EFLAGS::ZF, MBBNo);
Value *SFValue = getRegOrArgValue(EFLAGS::SF, MBBNo);
Value *OFValue = getRegOrArgValue(EFLAGS::OF, MBBNo);
assert((ZFValue != nullptr) && (SFValue != nullptr) &&
(OFValue != nullptr) &&
"Failed to get EFLAGS value while raising CMOVLE!");
// Check ZF == 1
CmpInst *ZFCond = new ICmpInst(CmpInst::Predicate::ICMP_EQ, ZFValue,
TrueValue, "ZFCmp_CMOVLE");
RaisedBB->getInstList().push_back(ZFCond);
// Test SF != OF
CmpInst *SFOFCond = new ICmpInst(CmpInst::Predicate::ICMP_NE, SFValue,
OFValue, "SFOFCmp_CMOVLE");
RaisedBB->getInstList().push_back(SFOFCond);
CMOVCond = BinaryOperator::CreateOr(ZFCond, SFOFCond, "Cond_CMOVLE");
} break;
case X86::COND_INVALID:
assert(false && "CMOV instruction with invalid condition found");
break;
default:
assert(false && "CMOV instruction with unhandled condition found");
break;
}
RaisedBB->getInstList().push_back(dyn_cast<Instruction>(CMOVCond));
// Ensure that the types of SrcValue and DstValue match.
DstValue = castValue(DstValue, SrcValue->getType(), RaisedBB);
// Generate SelectInst for CMOV instruction
SelectInst *SI = SelectInst::Create(CMOVCond, SrcValue, DstValue, "CMOV");
RaisedBB->getInstList().push_back(SI);
// Update the value mapping of DstPReg
raisedValues->setPhysRegSSAValue(DstPReg, MBBNo, SI);
Success = true;
} break;
default:
assert(false && "Unhandled move reg-to-reg instruction");
break;
}
return Success;
}
bool X86MachineInstructionRaiser::raiseLEAMachineInstr(const MachineInstr &MI) {
unsigned int Opcode = MI.getOpcode();
assert(MI.getNumExplicitOperands() == 6 &&
"Unexpected number of arguments of lea instruction");
// Get dest operand
MachineOperand DestOp = MI.getOperand(0);
assert(DestOp.isReg() &&
"Unhandled non-register destination operand in lea instruction");
unsigned int DestReg = DestOp.getReg();
int OpIndex = X86II::getMemoryOperandNo(MI.getDesc().TSFlags);
assert(OpIndex >= 0 && "Failed to get first operand of addressing-mode "
"expression in lea instruction");
MachineOperand BaseRegOp = MI.getOperand(OpIndex + X86::AddrBaseReg);
assert(BaseRegOp.isReg() &&
"Unhandled non-register BaseReg operand in lea instruction");
unsigned int BaseReg = BaseRegOp.getReg();
Value *EffectiveAddrValue = nullptr;
// If the basereg refers stack, get the stack allocated object value
uint64_t BaseSupReg = find64BitSuperReg(BaseReg);
if ((BaseSupReg == x86RegisterInfo->getStackRegister()) ||
(BaseSupReg == x86RegisterInfo->getFramePtr())) {
// Get index of memory reference in the instruction.
int memoryRefOpIndex = getMemoryRefOpIndex(MI);
// Should have found the index of the memory reference operand
assert(memoryRefOpIndex != -1 && "Unable to find memory reference "
"operand of a load/store instruction");
X86AddressMode memRef = llvm::getAddressFromInstr(&MI, memoryRefOpIndex);
EffectiveAddrValue = getStackAllocatedValue(MI, memRef, false);
} else {
MachineOperand ScaleAmtOp = MI.getOperand(OpIndex + X86::AddrScaleAmt);
assert(ScaleAmtOp.isImm() &&
"Unhandled non-immediate ScaleAmt operand in lea instruction");
MachineOperand IndexRegOp = MI.getOperand(OpIndex + X86::AddrIndexReg);
assert(IndexRegOp.isReg() &&
"Unhandled non-register IndexReg operand in lea instruction");
unsigned int IndexReg = IndexRegOp.getReg();
MachineOperand SegmentRegOp = MI.getOperand(OpIndex + X86::AddrSegmentReg);
assert(SegmentRegOp.getReg() == X86::NoRegister &&
"Unhandled vaule of SegmentReg operand in lea instruction");
MachineOperand Disp = MI.getOperand(OpIndex + X86::AddrDisp);
assert(Disp.isImm() &&
"Unhandled non-immediate Disp operand in lea instruction");
// Check the sanity of register sizes
if ((Opcode == X86::LEA64r) || (Opcode == X86::LEA64_32r)) {
// lea64mem (see LEA64 and LEA64_32r description in
// X86InstrArithmetic.td)
assert((is64BitPhysReg(BaseReg) || BaseReg == X86::NoRegister) &&
"Unexpected non-64 bit base register in lea instruction");
assert(((IndexReg == X86::NoRegister) || is64BitPhysReg(IndexReg)) &&
"Unexpected index register type in lea instruction");
assert(IndexReg != x86RegisterInfo->getStackRegister() &&
"Unexpected stack pointer register as indexReg operand of lea "
"instruction");
if (Opcode == X86::LEA64_32r) {
assert(is32BitPhysReg(DestReg) &&
"Unexpected non-32 bit destination register in lea "
"instruction");
} else {
assert(is64BitPhysReg(DestReg) &&
"Unexpected non-32 bit dest register in lea instruction");
}
} else if (Opcode == X86::LEA32r) {
assert((is32BitPhysReg(BaseReg) || BaseReg == X86::NoRegister) &&
"Unexpected non-32 bit base register in lea instruction");
assert(((IndexReg == X86::NoRegister) || is32BitPhysReg(IndexReg)) &&
"Unexpected indext register type in lea instruction");
assert(is32BitPhysReg(DestReg) &&
"Unexpected non-32 bit dest register in lea instruction");
} else if (Opcode == X86::LEA16r) {
assert((is16BitPhysReg(BaseReg) || BaseReg == X86::NoRegister) &&
"Unexpected non-16 bit source register in lea instruction");
assert(((IndexReg == X86::NoRegister) || is16BitPhysReg(IndexReg)) &&
"Unexpected indext register type in lea instruction");
assert(is16BitPhysReg(DestReg) &&
"Unexpected non-16 bit dest register in lea instruction");
}
if (BaseReg == X86::RIP)
EffectiveAddrValue = createPCRelativeAccesssValue(MI);
else
EffectiveAddrValue = getMemoryAddressExprValue(MI);
}
assert((EffectiveAddrValue != nullptr) &&
"Failed to get effective address value");
unsigned DestRegSize = getPhysRegSizeInBits(DestReg);
Type *DstTy = Type::getIntNTy(MF.getFunction().getContext(), DestRegSize);
// Get the BasicBlock corresponding to MachineBasicBlock of MI.
BasicBlock *RaisedBB = getRaisedBasicBlock(MI.getParent());
// Cast the result as needed
EffectiveAddrValue = castValue(EffectiveAddrValue, DstTy, RaisedBB);
// Update the value mapping of DestReg
raisedValues->setPhysRegSSAValue(DestReg, MI.getParent()->getNumber(),
EffectiveAddrValue);
return true;
}
bool X86MachineInstructionRaiser::raiseBinaryOpRegToRegMachineInstr(
const MachineInstr &MI) {
auto MCID = MI.getDesc();
// Get the BasicBlock corresponding to MachineBasicBlock of MI.
// Raised instruction is added to this BasicBlock.
BasicBlock *RaisedBB = getRaisedBasicBlock(MI.getParent());
// Convenience variables for instructions with a dest and one or two
// operands
const unsigned DestOpIndex = 0, UseOp1Index = 1, UseOp2Index = 2;
std::vector<Value *> Uses;
int MBBNo = MI.getParent()->getNumber();
for (const MachineOperand &MO : MI.explicit_uses()) {
assert(MO.isReg() &&
"Unexpected non-register operand in binary op instruction");
auto UseOpIndex = MI.findRegisterUseOperandIdx(MO.getReg(), false, nullptr);
Value *SrcValue = getRegOperandValue(MI, UseOpIndex);
Uses.push_back(SrcValue);
}
// Verify the instruction has 1 or 2 use operands
assert((Uses.size() == 1 || ((Uses.size() == 2))) &&
"Unexpected number of operands in register binary op instruction");
// If the instruction has two use operands, ensure that their values are
// of the same type and non-pointer type.
if (Uses.size() == 2) {
Value *Src1Value = Uses.at(0);
Value *Src2Value = Uses.at(1);
// The user operand values can be null if the instruction is 'xor op
// op'. See below.
if ((Src1Value != nullptr) && (Src2Value != nullptr)) {
// If this is a pointer type, convert it to int type
while (Src1Value->getType()->isPointerTy()) {
PtrToIntInst *ConvPtrToInst = new PtrToIntInst(
Src1Value, Src1Value->getType()->getPointerElementType());
RaisedBB->getInstList().push_back(ConvPtrToInst);
Src1Value = ConvPtrToInst;
}
// If this is a pointer type, convert it to int type
while (Src2Value->getType()->isPointerTy()) {
PtrToIntInst *ConvPtrToInst = new PtrToIntInst(
Src2Value, Src2Value->getType()->getPointerElementType());
RaisedBB->getInstList().push_back(ConvPtrToInst);
Src2Value = ConvPtrToInst;
}
assert(Src1Value->getType()->isIntegerTy() &&
Src2Value->getType()->isIntegerTy() &&
"Unhandled operand value types in reg-to-reg binary op "
"instruction");
if (Src1Value->getType() != Src2Value->getType()) {
// Cast the second operand to the type of second.
// NOTE : The choice of target cast type is rather arbitrary. May
// need a closer look.
Type *DestValueTy = Src1Value->getType();
Instruction *CInst = CastInst::Create(
CastInst::getCastOpcode(Src2Value, false, DestValueTy, false),
Src2Value, DestValueTy);
RaisedBB->getInstList().push_back(CInst);
Src2Value = CInst;
}
Uses[0] = Src1Value;
Uses[1] = Src2Value;
}
}
// Figure out the destination register, corresponding value and the
// binary operator.
unsigned int dstReg = X86::NoRegister;
Value *dstValue = nullptr;
unsigned opc = MI.getOpcode();
// Construct the appropriate binary operation instruction
switch (opc) {
case X86::ADD8rr:
case X86::ADD32rr:
case X86::ADD64rr:
// Verify the def operand is a register.
assert(MI.getOperand(DestOpIndex).isReg() &&
"Expecting destination of add instruction to be a register "
"operand");
assert((MCID.getNumDefs() == 1) &&
"Unexpected number of defines in an add instruction");
assert((Uses.at(0) != nullptr) && (Uses.at(1) != nullptr) &&
"Unhandled situation: register is used before initialization in "
"add");
dstReg = MI.getOperand(DestOpIndex).getReg();
dstValue = BinaryOperator::CreateNSWAdd(Uses.at(0), Uses.at(1));
if (isa<Instruction>(dstValue))
RaisedBB->getInstList().push_back(dyn_cast<Instruction>(dstValue));
// Set SF and ZF based on dstValue; technically OF, AF, CF and PF also
// needs to be set but ignoring for now.
raisedValues->testAndSetEflagSSAValue(EFLAGS::SF, MBBNo, dstValue);
raisedValues->testAndSetEflagSSAValue(EFLAGS::ZF, MBBNo, dstValue);
// Update the value of dstReg
raisedValues->setPhysRegSSAValue(dstReg, MBBNo, dstValue);
break;
case X86::IMUL16rr:
case X86::IMUL32rr:
case X86::IMUL64rr:
// Verify the def operand is a register.
assert(MI.getOperand(DestOpIndex).isReg() &&
"Expecting destination of mul instruction to be a register "
"operand");
assert((MCID.getNumDefs() == 1) &&
"Unexpected number of defines in a mul instruction");
assert((Uses.at(0) != nullptr) && (Uses.at(1) != nullptr) &&
"Unhandled situation: register is used before initialization in "
"mul");
dstReg = MI.getOperand(DestOpIndex).getReg();
dstValue = BinaryOperator::CreateNSWMul(Uses.at(0), Uses.at(1));
if (isa<Instruction>(dstValue))
RaisedBB->getInstList().push_back(dyn_cast<Instruction>(dstValue));
// Setting EFLAG bits does not seem to matter, so not setting
// Set the dstReg value
raisedValues->setPhysRegSSAValue(dstReg, MBBNo, dstValue);
break;
case X86::IMUL64r: {
assert(MCID.getNumDefs() == 0 && MCID.getNumImplicitDefs() == 3 &&
MCID.getNumImplicitUses() == 1 &&
"Unexpected operands in imul instruction");
// Find first source operand - this is the implicit operand AL/AX/EAX/RAX
const MCPhysReg Src1Reg = MCID.ImplicitUses[0];
assert(find64BitSuperReg(Src1Reg) == X86::RAX &&
"Unexpected implicit register in imul instruction");
// Find second operand - this is the explicit operand of the instruction
std::vector<MCPhysReg> SrcRegs;
for (const MachineOperand &MO : MI.explicit_uses()) {
assert(MO.isReg() &&
"Unexpected non-register operand in binary op instruction");
SrcRegs.push_back(MO.getReg());
}
// Ensure that there is only one explicit source operand
assert(SrcRegs.size() == 1 &&
"Unexpected number of source register operands in imul instruction");
// Check the sizes of source operands are the same
const MCPhysReg Src2Reg = SrcRegs[0];
unsigned int SrcOpSize = getPhysRegSizeInBits(Src1Reg);
assert(getPhysRegSizeInBits(Src1Reg) == getPhysRegSizeInBits(Src2Reg) &&
"Mismatched size of implicit source register and explicit source "
"register");
// Get the value of Src1Reg and Src2Reg
Value *Src1Value = getRegOrArgValue(Src1Reg, MBBNo);
Value *Src2Value = getRegOrArgValue(Src2Reg, MBBNo);
assert((Src1Value != nullptr) && (Src2Value != nullptr) &&
"Unexpected null source operand value in imul instruction");
assert(Src1Value->getType()->isIntegerTy() &&
Src2Value->getType()->isIntegerTy() &&
"Unexpected non-integer type source operands in imul instruction");
LLVMContext &Ctx(MF.getFunction().getContext());
// Widen the source values since the result of th emultiplication
Type *WideTy = Type::getIntNTy(Ctx, SrcOpSize * 2);
CastInst *Src1ValueDT =
CastInst::Create(CastInst::getCastOpcode(Src1Value, true, WideTy, true),
Src1Value, WideTy);
RaisedBB->getInstList().push_back(Src1ValueDT);
CastInst *Src2ValueDT =
CastInst::Create(CastInst::getCastOpcode(Src2Value, true, WideTy, true),
Src2Value, WideTy);
RaisedBB->getInstList().push_back(Src2ValueDT);
// Multiply the values
Instruction *FullProductValue =
BinaryOperator::CreateNSWMul(Src1ValueDT, Src2ValueDT);
RaisedBB->getInstList().push_back(FullProductValue);
// Shift amount equal to size of source operand
Value *ShiftAmountVal =
ConstantInt::get(FullProductValue->getType(), SrcOpSize);
Value *ZeroValueDT =
ConstantInt::get(FullProductValue->getType(), 0, false /* isSigned */);
// Split the value into ImplicitDefs[0]:ImplicitDefs[1]
// Compute shr of FullProductValue
Instruction *ShrDT =
BinaryOperator::CreateLShr(FullProductValue, ShiftAmountVal);
RaisedBB->getInstList().push_back(ShrDT);
// Now generate ShrDT OR 0
Instruction *OrDT = BinaryOperator::CreateOr(ShrDT, ZeroValueDT);
RaisedBB->getInstList().push_back(OrDT);
// Cast OrValDT to SrcOpSize
Type *SrcValTy = Src1Value->getType();
CastInst *ProductUpperValue = CastInst::Create(
CastInst::getCastOpcode(OrDT, true, SrcValTy, true), OrDT, SrcValTy);
RaisedBB->getInstList().push_back(ProductUpperValue);
// Set the value of ImplicitDef[0] as ProductLowreHalfValue
raisedValues->setPhysRegSSAValue(MCID.ImplicitDefs[0], MBBNo,
ProductUpperValue);
// Now generate and instruction to get lower half value
Value *MaskValue = Constant::getAllOnesValue(SrcValTy);
Instruction *MaskValDT =
CastInst::Create(CastInst::getCastOpcode(MaskValue, true, WideTy, true),
MaskValue, WideTy);
RaisedBB->getInstList().push_back(MaskValDT);
Instruction *AndValDT =
BinaryOperator::CreateAnd(FullProductValue, MaskValDT);
RaisedBB->getInstList().push_back(AndValDT);
// Cast AndValDT to SrcOpSize
CastInst *ProductLowerHalfValue = CastInst::Create(
CastInst::getCastOpcode(AndValDT, true, SrcValTy, true), AndValDT,
SrcValTy);
RaisedBB->getInstList().push_back(ProductLowerHalfValue);
// Set the value of ImplicitDef[1] as ProductLowerHalfValue
raisedValues->setPhysRegSSAValue(MCID.ImplicitDefs[1], MBBNo,
ProductLowerHalfValue);
// Set OF and CF flags to 0 if upper half of the result is 0; else to 1.
Value *ZeroValue = ConstantInt::get(SrcValTy, 0, false /* isSigned */);
Instruction *ZFTest =
new ICmpInst(CmpInst::Predicate::ICMP_EQ, ProductLowerHalfValue,
ZeroValue, "Test_Zero");
RaisedBB->getInstList().push_back(ZFTest);
raisedValues->setPhysRegSSAValue(X86RegisterUtils::EFLAGS::OF, MBBNo,
ZFTest);
raisedValues->setPhysRegSSAValue(X86RegisterUtils::EFLAGS::SF, MBBNo,
ZFTest);
} break;
case X86::AND8rr:
case X86::AND16rr:
case X86::AND32rr:
case X86::AND64rr:
case X86::OR8rr:
case X86::OR16rr:
case X86::OR32rr:
case X86::OR64rr:
case X86::XOR8rr:
case X86::XOR16rr:
case X86::XOR32rr:
case X86::XOR64rr: {
// Verify the def operand is a register.
const MachineOperand &DestOp = MI.getOperand(DestOpIndex);
const MachineOperand &Use2Op = MI.getOperand(UseOp2Index);
assert(DestOp.isReg() && "Expecting destination of xor instruction to "
"be a register operand");
assert((MCID.getNumDefs() == 1) &&
MCID.hasImplicitDefOfPhysReg(X86::EFLAGS) &&
"Unexpected defines in a xor instruction");
dstReg = DestOp.getReg();
// Generate an or instruction to set the zero flag if the
// operands are the same. An instruction such as 'xor $ecx, ecx' is
// generated to set the register value to 0.
if ((MI.findTiedOperandIdx(1) == 0) && (dstReg == Use2Op.getReg())) {
// No instruction to generate. Just set destReg value to 0.
Type *DestTy = getPhysRegOperandType(MI, 0);
Value *Val = ConstantInt::get(DestTy, 0, false /* isSigned */);
dstValue = Val;
// Set SF and ZF knowing that the value is 0
raisedValues->setEflagValue(EFLAGS::SF, MBBNo, false);
raisedValues->setEflagValue(EFLAGS::ZF, MBBNo, true);
} else {
assert((Uses.at(0) != nullptr) && (Uses.at(1) != nullptr) &&
"Unhandled situation: register used before initialization in "
"xor");
switch (opc) {
case X86::AND8rr:
case X86::AND16rr:
case X86::AND32rr:
case X86::AND64rr:
dstValue = BinaryOperator::CreateAnd(Uses.at(0), Uses.at(1));
break;
case X86::OR8rr:
case X86::OR16rr:
case X86::OR32rr:
case X86::OR64rr:
dstValue = BinaryOperator::CreateOr(Uses.at(0), Uses.at(1));
break;
case X86::XOR8rr:
case X86::XOR16rr:
case X86::XOR32rr:
case X86::XOR64rr:
dstValue = BinaryOperator::CreateXor(Uses.at(0), Uses.at(1));
break;
default:
assert(false && "Reached unexpected location");
}
if (isa<Instruction>(dstValue))
RaisedBB->getInstList().push_back(dyn_cast<Instruction>(dstValue));
// Set SF and ZF based on dstValue; technically PF also needs
// to be set but ignoring for now.
raisedValues->testAndSetEflagSSAValue(EFLAGS::SF, MBBNo, dstValue);
raisedValues->testAndSetEflagSSAValue(EFLAGS::ZF, MBBNo, dstValue);
}
// Clear OF and CF
raisedValues->setEflagValue(EFLAGS::OF, MBBNo, false);
raisedValues->setEflagValue(EFLAGS::CF, MBBNo, false);
// Update the value of dstReg
raisedValues->setPhysRegSSAValue(dstReg, MBBNo, dstValue);
} break;
case X86::TEST8rr:
case X86::TEST16rr:
case X86::TEST32rr:
case X86::TEST64rr:
assert((MCID.getNumDefs() == 0) &&
MCID.hasImplicitDefOfPhysReg(X86::EFLAGS) &&
"Unexpected defines in a test instruction");
assert((Uses.at(0) != nullptr) && (Uses.at(1) != nullptr) &&
"Unhandled situation: register is used before initialization in "
"test");
dstReg = X86::EFLAGS;
dstValue = BinaryOperator::CreateAnd(Uses.at(0), Uses.at(1));
if (isa<Instruction>(dstValue))
RaisedBB->getInstList().push_back(dyn_cast<Instruction>(dstValue));
// Clear OF and CF
raisedValues->setEflagValue(EFLAGS::OF, MBBNo, false);
raisedValues->setEflagValue(EFLAGS::CF, MBBNo, false);
// Set SF and ZF based on dstValue; technically PF also needs
// to be set but ignoring for now.
raisedValues->testAndSetEflagSSAValue(EFLAGS::SF, MBBNo, dstValue);
raisedValues->testAndSetEflagSSAValue(EFLAGS::ZF, MBBNo, dstValue);