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Sebastien Bourdeauducq
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Mar 6, 2012
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Original file line number | Diff line number | Diff line change |
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from migen.fhdl.structure import * | ||
from migen.sim.generic import Simulator, TopLevel | ||
from migen.sim.icarus import Runner | ||
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class Mem: | ||
def __init__(self): | ||
self.a = Signal(BV(12)) | ||
self.d = Signal(BV(16)) | ||
p = MemoryPort(self.a, self.d) | ||
self.mem = Memory(16, 2**12, p, init=list(range(20))) | ||
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def do_simulation(self, s): | ||
if s.cycle_counter >= 0: | ||
value = s.rd(self.mem, s.cycle_counter) | ||
print(value) | ||
if value == 10: | ||
s.interrupt = True | ||
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def get_fragment(self): | ||
return Fragment(memories=[self.mem], sim=[self.do_simulation]) | ||
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def main(): | ||
dut = Mem() | ||
sim = Simulator(dut.get_fragment(), Runner()) | ||
sim.run() | ||
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main() |
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