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simd-intrinsics.c
2644 lines (2384 loc) · 92.9 KB
/
simd-intrinsics.c
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/**
* \file
* simd support for intrinsics
*
* Author:
* Rodrigo Kumpera (rkumpera@novell.com)
*
* (C) 2008 Novell, Inc.
*/
#include <config.h>
#include <stdio.h>
#include "mini.h"
#include "ir-emit.h"
#include <mono/metadata/abi-details.h>
#include <mono/metadata/reflection-internals.h>
#include <mono/utils/mono-compiler.h>
#include <mono/utils/bsearch.h>
/*
General notes on SIMD intrinsics
TODO handle operands with non SIMD args, such as op_Addition (Vector4f, float)
TODO optimize r4const in .ctor so it doesn't go into the FP stack first
TODO extend op_to_op_dest_membase to handle simd ops
TODO add support for indexed versions of simd ops
TODO to an amd64 port and figure out how to properly handle extractors/.ctor
TODO make sure locals, arguments and spills are properly aligned.
TODO add support for fusing a XMOVE into a simd op in mono_spill_global_vars.
TODO add stuff to man pages
TODO document this under /docs
TODO make passing a xmm as argument not cause it to be LDADDR'ed (introduce an OP_XPUSH)
TODO revamp the .ctor sequence as it looks very fragile, maybe use a var just like move_i4_to_f. (or just pinst sse ops)
TODO figure out what's wrong with OP_STOREX_MEMBASE_REG and OP_STOREX_MEMBASE (the 2nd is for imm operands)
TODO maybe add SSE3 emulation on top of SSE2, or just implement the corresponding functions using SSE2 intrinsics.
TODO pass simd arguments in registers or, at least, add SSE support for pushing large (>=16) valuetypes
TODO pass simd args byval to a non-intrinsic method cause some useless local var load/store to happen.
TODO check if we need to init the SSE control word with better precision.
TODO add support for 3 reg sources in mini without slowing the common path. Or find a way to make MASKMOVDQU work.
TODO make SimdRuntime.get_AccelMode work under AOT
TODO patterns such as "a ^= b" generate slower code as the LDADDR op will be copied to a tmp first. Look at adding a indirection reduction pass after the dce pass.
TODO extend bounds checking code to support for range checking.
General notes for SIMD intrinsics.
-Bad extractor and constructor performance
Extracting a float from a XMM is a complete disaster if you are passing it as an argument.
It will be loaded in the FP stack just to be pushed on the call stack.
A similar thing happens with Vector4f constructor that require float vars to be
The fix for this issue is similar to the one required for r4const as method args. Avoiding the
trip to the FP stack is desirable.
-Extractor and constructor code doesn't make sense under amd64. Both currently assume separate banks
for simd and fp.
-Promote OP_EXTRACT_I4 to a STORE op
The advantage of this change is that it could have a _membase version and promote further optimizations.
-Create a MONO_INST_DONT_REGALLOC and use it in all places that MONO_INST_INDIRECT is used
without a OP_LDADDR.
*/
#if defined (MONO_ARCH_SIMD_INTRINSICS)
#if defined (DISABLE_JIT)
void
mono_simd_intrinsics_init (void)
{
}
#else
//#define IS_DEBUG_ON(cfg) (0)
#define IS_DEBUG_ON(cfg) ((cfg)->verbose_level >= 3)
#define DEBUG(a) do { if (IS_DEBUG_ON(cfg)) { a; } } while (0)
/*
This enum MUST be kept in sync with its managed mirror Mono.Simd.AccelMode.
*/
enum {
SIMD_VERSION_SSE1 = 1 << 0,
SIMD_VERSION_SSE2 = 1 << 1,
SIMD_VERSION_SSE3 = 1 << 2,
SIMD_VERSION_SSSE3 = 1 << 3,
SIMD_VERSION_SSE41 = 1 << 4,
SIMD_VERSION_SSE42 = 1 << 5,
SIMD_VERSION_SSE4a = 1 << 6,
};
enum {
SIMD_EMIT_BINARY,
SIMD_EMIT_UNARY,
SIMD_EMIT_SETTER,
SIMD_EMIT_GETTER,
SIMD_EMIT_GETTER_QWORD,
SIMD_EMIT_CTOR,
SIMD_EMIT_CAST,
SIMD_EMIT_SHUFFLE,
SIMD_EMIT_SHIFT,
SIMD_EMIT_EQUALITY,
SIMD_EMIT_LOAD_ALIGNED,
SIMD_EMIT_STORE,
SIMD_EMIT_EXTRACT_MASK,
SIMD_EMIT_PREFETCH
};
// This, instead of an array of pointers, to optimize away a pointer and a relocation per string.
#define MSGSTRFIELD(line) MSGSTRFIELD1(line)
#define MSGSTRFIELD1(line) str##line
static const struct msgstr_t {
#define SIMD_METHOD(str,name) char MSGSTRFIELD(__LINE__) [sizeof (str)];
#include "simd-methods.h"
#undef SIMD_METHOD
} method_names = {
#define SIMD_METHOD(str,name) str,
#include "simd-methods.h"
#undef SIMD_METHOD
};
enum {
#define SIMD_METHOD(str,name) name = offsetof (struct msgstr_t, MSGSTRFIELD(__LINE__)),
#include "simd-methods.h"
};
#define method_name(idx) ((const char*)&method_names + (idx))
typedef struct {
guint16 name;
guint16 opcode;
guint32 simd_version;
guint8 simd_emit_mode : 4;
guint8 flags : 4;
} SimdIntrinsic;
static const SimdIntrinsic vector4f_intrinsics[] = {
{ SN_ctor, OP_EXPAND_R4, MONO_CPU_X86_SSE, SIMD_EMIT_CTOR },
{ SN_AddSub, OP_ADDSUBPS, MONO_CPU_X86_SSE3, SIMD_EMIT_BINARY},
{ SN_AndNot, OP_ANDNPS, MONO_CPU_X86_SSE, SIMD_EMIT_BINARY},
{ SN_CompareEqual, OP_COMPPS, MONO_CPU_X86_SSE, SIMD_EMIT_BINARY, SIMD_COMP_EQ },
{ SN_CompareLessEqual, OP_COMPPS, MONO_CPU_X86_SSE, SIMD_EMIT_BINARY, SIMD_COMP_LE },
{ SN_CompareLessThan, OP_COMPPS, MONO_CPU_X86_SSE, SIMD_EMIT_BINARY, SIMD_COMP_LT },
{ SN_CompareNotEqual, OP_COMPPS, MONO_CPU_X86_SSE, SIMD_EMIT_BINARY, SIMD_COMP_NEQ },
{ SN_CompareNotLessEqual, OP_COMPPS, MONO_CPU_X86_SSE, SIMD_EMIT_BINARY, SIMD_COMP_NLE },
{ SN_CompareNotLessThan, OP_COMPPS, MONO_CPU_X86_SSE, SIMD_EMIT_BINARY, SIMD_COMP_NLT },
{ SN_CompareOrdered, OP_COMPPS, MONO_CPU_X86_SSE, SIMD_EMIT_BINARY, SIMD_COMP_ORD },
{ SN_CompareUnordered, OP_COMPPS, MONO_CPU_X86_SSE, SIMD_EMIT_BINARY, SIMD_COMP_UNORD },
{ SN_ConvertToDouble, OP_CVTPS2PD, MONO_CPU_X86_SSE2, SIMD_EMIT_UNARY },
{ SN_ConvertToInt, OP_CVTPS2DQ, MONO_CPU_X86_SSE2, SIMD_EMIT_UNARY },
{ SN_ConvertToIntTruncated, OP_CVTTPS2DQ, MONO_CPU_X86_SSE2, SIMD_EMIT_UNARY },
{ SN_DuplicateHigh, OP_DUPPS_HIGH, MONO_CPU_X86_SSE3, SIMD_EMIT_UNARY },
{ SN_DuplicateLow, OP_DUPPS_LOW, MONO_CPU_X86_SSE3, SIMD_EMIT_UNARY },
{ SN_HorizontalAdd, OP_HADDPS, MONO_CPU_X86_SSE3, SIMD_EMIT_BINARY },
{ SN_HorizontalSub, OP_HSUBPS, MONO_CPU_X86_SSE3, SIMD_EMIT_BINARY },
{ SN_InterleaveHigh, OP_UNPACK_HIGHPS, MONO_CPU_X86_SSE, SIMD_EMIT_BINARY },
{ SN_InterleaveLow, OP_UNPACK_LOWPS, MONO_CPU_X86_SSE, SIMD_EMIT_BINARY },
{ SN_InvSqrt, OP_RSQRTPS, MONO_CPU_X86_SSE, SIMD_EMIT_UNARY },
{ SN_LoadAligned, 0, MONO_CPU_X86_SSE, SIMD_EMIT_LOAD_ALIGNED },
{ SN_Max, OP_MAXPS, MONO_CPU_X86_SSE, SIMD_EMIT_BINARY },
{ SN_Min, OP_MINPS, MONO_CPU_X86_SSE, SIMD_EMIT_BINARY },
{ SN_PrefetchTemporalAllCacheLevels, 0, MONO_CPU_X86_SSE, SIMD_EMIT_PREFETCH, SIMD_PREFETCH_MODE_0 },
{ SN_PrefetchTemporal1stLevelCache, 0, MONO_CPU_X86_SSE, SIMD_EMIT_PREFETCH, SIMD_PREFETCH_MODE_1 },
{ SN_PrefetchTemporal2ndLevelCache, 0, MONO_CPU_X86_SSE, SIMD_EMIT_PREFETCH, SIMD_PREFETCH_MODE_2 },
{ SN_PrefetchNonTemporal, 0, MONO_CPU_X86_SSE, SIMD_EMIT_PREFETCH, SIMD_PREFETCH_MODE_NTA },
{ SN_Reciprocal, OP_RCPPS, MONO_CPU_X86_SSE, SIMD_EMIT_UNARY },
{ SN_Shuffle, OP_PSHUFLED, MONO_CPU_X86_SSE, SIMD_EMIT_SHUFFLE },
{ SN_Sqrt, OP_SQRTPS, MONO_CPU_X86_SSE, SIMD_EMIT_UNARY },
{ SN_StoreAligned, OP_STOREX_ALIGNED_MEMBASE_REG, MONO_CPU_X86_SSE, SIMD_EMIT_STORE },
{ SN_StoreNonTemporal, OP_STOREX_NTA_MEMBASE_REG, MONO_CPU_X86_SSE, SIMD_EMIT_STORE },
{ SN_get_W, 3, MONO_CPU_X86_SSE, SIMD_EMIT_GETTER },
{ SN_get_X, 0, MONO_CPU_X86_SSE, SIMD_EMIT_GETTER },
{ SN_get_Y, 1, MONO_CPU_X86_SSE, SIMD_EMIT_GETTER },
{ SN_get_Z, 2, MONO_CPU_X86_SSE, SIMD_EMIT_GETTER },
{ SN_op_Addition, OP_ADDPS, MONO_CPU_X86_SSE, SIMD_EMIT_BINARY },
{ SN_op_BitwiseAnd, OP_ANDPS, MONO_CPU_X86_SSE, SIMD_EMIT_BINARY },
{ SN_op_BitwiseOr, OP_ORPS, MONO_CPU_X86_SSE, SIMD_EMIT_BINARY },
{ SN_op_Division, OP_DIVPS, MONO_CPU_X86_SSE, SIMD_EMIT_BINARY },
{ SN_op_Equality, OP_COMPPS, MONO_CPU_X86_SSE, SIMD_EMIT_EQUALITY, SIMD_COMP_EQ },
{ SN_op_ExclusiveOr, OP_XORPS, MONO_CPU_X86_SSE, SIMD_EMIT_BINARY },
{ SN_op_Explicit, 0, MONO_CPU_X86_SSE, SIMD_EMIT_CAST },
{ SN_op_Inequality, OP_COMPPS, MONO_CPU_X86_SSE, SIMD_EMIT_EQUALITY, SIMD_COMP_NEQ },
{ SN_op_Multiply, OP_MULPS, MONO_CPU_X86_SSE, SIMD_EMIT_BINARY },
{ SN_op_Subtraction, OP_SUBPS, MONO_CPU_X86_SSE, SIMD_EMIT_BINARY },
{ SN_set_W, 3, MONO_CPU_X86_SSE, SIMD_EMIT_SETTER },
{ SN_set_X, 0, MONO_CPU_X86_SSE, SIMD_EMIT_SETTER },
{ SN_set_Y, 1, MONO_CPU_X86_SSE, SIMD_EMIT_SETTER },
{ SN_set_Z, 2, MONO_CPU_X86_SSE, SIMD_EMIT_SETTER }
};
static const SimdIntrinsic vector2d_intrinsics[] = {
{ SN_ctor, OP_EXPAND_R8, MONO_CPU_X86_SSE, SIMD_EMIT_CTOR },
{ SN_AddSub, OP_ADDSUBPD, MONO_CPU_X86_SSE3, SIMD_EMIT_BINARY,},
{ SN_AndNot, OP_ANDNPD, MONO_CPU_X86_SSE, SIMD_EMIT_BINARY },
{ SN_CompareEqual, OP_COMPPD, MONO_CPU_X86_SSE, SIMD_EMIT_BINARY, SIMD_COMP_EQ },
{ SN_CompareLessEqual, OP_COMPPD, MONO_CPU_X86_SSE, SIMD_EMIT_BINARY, SIMD_COMP_LE },
{ SN_CompareLessThan, OP_COMPPD, MONO_CPU_X86_SSE, SIMD_EMIT_BINARY, SIMD_COMP_LT },
{ SN_CompareNotEqual, OP_COMPPD, MONO_CPU_X86_SSE, SIMD_EMIT_BINARY, SIMD_COMP_NEQ },
{ SN_CompareNotLessEqual, OP_COMPPD, MONO_CPU_X86_SSE, SIMD_EMIT_BINARY, SIMD_COMP_NLE },
{ SN_CompareNotLessThan, OP_COMPPD, MONO_CPU_X86_SSE, SIMD_EMIT_BINARY, SIMD_COMP_NLT },
{ SN_CompareOrdered, OP_COMPPD, MONO_CPU_X86_SSE, SIMD_EMIT_BINARY, SIMD_COMP_ORD },
{ SN_CompareUnordered, OP_COMPPD, MONO_CPU_X86_SSE, SIMD_EMIT_BINARY, SIMD_COMP_UNORD },
{ SN_ConvertToFloat, OP_CVTPD2PS, MONO_CPU_X86_SSE2, SIMD_EMIT_UNARY },
{ SN_ConvertToInt, OP_CVTPD2DQ, MONO_CPU_X86_SSE2, SIMD_EMIT_UNARY },
{ SN_ConvertToIntTruncated, OP_CVTTPD2DQ, MONO_CPU_X86_SSE2, SIMD_EMIT_UNARY },
{ SN_Duplicate, OP_DUPPD, MONO_CPU_X86_SSE3, SIMD_EMIT_UNARY },
{ SN_HorizontalAdd, OP_HADDPD, MONO_CPU_X86_SSE3, SIMD_EMIT_BINARY },
{ SN_HorizontalSub, OP_HSUBPD, MONO_CPU_X86_SSE3, SIMD_EMIT_BINARY },
{ SN_InterleaveHigh, OP_UNPACK_HIGHPD, MONO_CPU_X86_SSE, SIMD_EMIT_BINARY },
{ SN_InterleaveLow, OP_UNPACK_LOWPD, MONO_CPU_X86_SSE, SIMD_EMIT_BINARY },
{ SN_LoadAligned, 0, MONO_CPU_X86_SSE, SIMD_EMIT_LOAD_ALIGNED },
{ SN_Max, OP_MAXPD, MONO_CPU_X86_SSE, SIMD_EMIT_BINARY },
{ SN_Min, OP_MINPD, MONO_CPU_X86_SSE, SIMD_EMIT_BINARY },
{ SN_PrefetchTemporalAllCacheLevels, 0, MONO_CPU_X86_SSE, SIMD_EMIT_PREFETCH, SIMD_PREFETCH_MODE_0 },
{ SN_PrefetchTemporal1stLevelCache, 0, MONO_CPU_X86_SSE, SIMD_EMIT_PREFETCH, SIMD_PREFETCH_MODE_1 },
{ SN_PrefetchTemporal2ndLevelCache, 0, MONO_CPU_X86_SSE, SIMD_EMIT_PREFETCH, SIMD_PREFETCH_MODE_2 },
{ SN_PrefetchNonTemporal, 0, MONO_CPU_X86_SSE, SIMD_EMIT_PREFETCH, SIMD_PREFETCH_MODE_NTA },
{ SN_Shuffle, OP_SHUFPD, MONO_CPU_X86_SSE, SIMD_EMIT_SHUFFLE },
{ SN_Sqrt, OP_SQRTPD, MONO_CPU_X86_SSE, SIMD_EMIT_UNARY },
{ SN_StoreAligned, OP_STOREX_ALIGNED_MEMBASE_REG, MONO_CPU_X86_SSE, SIMD_EMIT_STORE },
{ SN_get_X, 0, MONO_CPU_X86_SSE, SIMD_EMIT_GETTER_QWORD },
{ SN_get_Y, 1, MONO_CPU_X86_SSE, SIMD_EMIT_GETTER_QWORD },
{ SN_op_Addition, OP_ADDPD, MONO_CPU_X86_SSE, SIMD_EMIT_BINARY },
{ SN_op_BitwiseAnd, OP_ANDPD, MONO_CPU_X86_SSE, SIMD_EMIT_BINARY },
{ SN_op_BitwiseOr, OP_ORPD, MONO_CPU_X86_SSE, SIMD_EMIT_BINARY },
{ SN_op_Division, OP_DIVPD, MONO_CPU_X86_SSE, SIMD_EMIT_BINARY },
{ SN_op_ExclusiveOr, OP_XORPD, MONO_CPU_X86_SSE, SIMD_EMIT_BINARY },
{ SN_op_Explicit, 0, MONO_CPU_X86_SSE, SIMD_EMIT_CAST },
{ SN_op_Multiply, OP_MULPD, MONO_CPU_X86_SSE, SIMD_EMIT_BINARY },
{ SN_op_Subtraction, OP_SUBPD, MONO_CPU_X86_SSE, SIMD_EMIT_BINARY },
{ SN_set_X, 0, MONO_CPU_X86_SSE, SIMD_EMIT_SETTER },
{ SN_set_Y, 1, MONO_CPU_X86_SSE, SIMD_EMIT_SETTER },
};
static const SimdIntrinsic vector2ul_intrinsics[] = {
{ SN_ctor, OP_EXPAND_I8, MONO_CPU_X86_SSE, SIMD_EMIT_CTOR },
{ SN_CompareEqual, OP_PCMPEQQ, MONO_CPU_X86_SSE41, SIMD_EMIT_BINARY },
{ SN_LoadAligned, 0, MONO_CPU_X86_SSE, SIMD_EMIT_LOAD_ALIGNED },
{ SN_PrefetchTemporalAllCacheLevels, 0, MONO_CPU_X86_SSE, SIMD_EMIT_PREFETCH, SIMD_PREFETCH_MODE_0 },
{ SN_PrefetchTemporal1stLevelCache, 0, MONO_CPU_X86_SSE, SIMD_EMIT_PREFETCH, SIMD_PREFETCH_MODE_1 },
{ SN_PrefetchTemporal2ndLevelCache, 0, MONO_CPU_X86_SSE, SIMD_EMIT_PREFETCH, SIMD_PREFETCH_MODE_2 },
{ SN_PrefetchNonTemporal, 0, MONO_CPU_X86_SSE, SIMD_EMIT_PREFETCH, SIMD_PREFETCH_MODE_NTA },
{ SN_Shuffle, OP_SHUFPD, MONO_CPU_X86_SSE, SIMD_EMIT_SHUFFLE },
{ SN_StoreAligned, OP_STOREX_ALIGNED_MEMBASE_REG, MONO_CPU_X86_SSE, SIMD_EMIT_STORE },
{ SN_UnpackHigh, OP_UNPACK_HIGHQ, MONO_CPU_X86_SSE, SIMD_EMIT_BINARY },
{ SN_UnpackLow, OP_UNPACK_LOWQ, MONO_CPU_X86_SSE, SIMD_EMIT_BINARY },
{ SN_get_X, 0, MONO_CPU_X86_SSE, SIMD_EMIT_GETTER_QWORD },
{ SN_get_Y, 1, MONO_CPU_X86_SSE, SIMD_EMIT_GETTER_QWORD },
{ SN_op_Addition, OP_PADDQ, MONO_CPU_X86_SSE, SIMD_EMIT_BINARY },
{ SN_op_BitwiseAnd, OP_PAND, MONO_CPU_X86_SSE, SIMD_EMIT_BINARY },
{ SN_op_BitwiseOr, OP_POR, MONO_CPU_X86_SSE, SIMD_EMIT_BINARY },
{ SN_op_ExclusiveOr, OP_PXOR, SIMD_EMIT_BINARY, MONO_CPU_X86_SSE },
{ SN_op_Explicit, 0, MONO_CPU_X86_SSE, SIMD_EMIT_CAST },
{ SN_op_LeftShift, OP_PSHLQ, MONO_CPU_X86_SSE, SIMD_EMIT_SHIFT },
{ SN_op_Multiply, OP_PMULQ, MONO_CPU_X86_SSE, SIMD_EMIT_BINARY },
{ SN_op_RightShift, OP_PSHRQ, MONO_CPU_X86_SSE, SIMD_EMIT_SHIFT },
{ SN_op_Subtraction, OP_PSUBQ, MONO_CPU_X86_SSE, SIMD_EMIT_BINARY },
{ SN_set_X, 0, MONO_CPU_X86_SSE, SIMD_EMIT_SETTER },
{ SN_set_Y, 1, MONO_CPU_X86_SSE, SIMD_EMIT_SETTER },
};
static const SimdIntrinsic vector2l_intrinsics[] = {
{ SN_ctor, OP_EXPAND_I8, MONO_CPU_X86_SSE, SIMD_EMIT_CTOR },
{ SN_CompareEqual, OP_PCMPEQQ, MONO_CPU_X86_SSE41, SIMD_EMIT_BINARY },
{ SN_CompareGreaterThan, OP_PCMPGTQ, MONO_CPU_X86_SSE42, SIMD_EMIT_BINARY },
{ SN_LoadAligned, 0, MONO_CPU_X86_SSE, SIMD_EMIT_LOAD_ALIGNED },
{ SN_LogicalRightShift, OP_PSHRQ, MONO_CPU_X86_SSE, SIMD_EMIT_SHIFT },
{ SN_PrefetchTemporalAllCacheLevels, 0, MONO_CPU_X86_SSE, SIMD_EMIT_PREFETCH, SIMD_PREFETCH_MODE_0 },
{ SN_PrefetchTemporal1stLevelCache, 0, MONO_CPU_X86_SSE, SIMD_EMIT_PREFETCH, SIMD_PREFETCH_MODE_1 },
{ SN_PrefetchTemporal2ndLevelCache, 0, MONO_CPU_X86_SSE, SIMD_EMIT_PREFETCH, SIMD_PREFETCH_MODE_2 },
{ SN_PrefetchNonTemporal, 0, MONO_CPU_X86_SSE, SIMD_EMIT_PREFETCH, SIMD_PREFETCH_MODE_NTA },
{ SN_Shuffle, OP_SHUFPD, MONO_CPU_X86_SSE, SIMD_EMIT_SHUFFLE },
{ SN_StoreAligned, OP_STOREX_ALIGNED_MEMBASE_REG, MONO_CPU_X86_SSE, SIMD_EMIT_STORE },
{ SN_UnpackHigh, OP_UNPACK_HIGHQ, MONO_CPU_X86_SSE, SIMD_EMIT_BINARY },
{ SN_UnpackLow, OP_UNPACK_LOWQ, MONO_CPU_X86_SSE, SIMD_EMIT_BINARY },
{ SN_get_X, 0, MONO_CPU_X86_SSE, SIMD_EMIT_GETTER_QWORD },
{ SN_get_Y, 1, MONO_CPU_X86_SSE, SIMD_EMIT_GETTER_QWORD },
{ SN_op_Addition, OP_PADDQ, MONO_CPU_X86_SSE, SIMD_EMIT_BINARY },
{ SN_op_BitwiseAnd, OP_PAND, MONO_CPU_X86_SSE, SIMD_EMIT_BINARY },
{ SN_op_BitwiseOr, OP_POR, MONO_CPU_X86_SSE, SIMD_EMIT_BINARY },
{ SN_op_ExclusiveOr, OP_PXOR, MONO_CPU_X86_SSE, SIMD_EMIT_BINARY },
{ SN_op_Explicit, 0, MONO_CPU_X86_SSE, SIMD_EMIT_CAST },
{ SN_op_LeftShift, OP_PSHLQ, MONO_CPU_X86_SSE, SIMD_EMIT_SHIFT },
{ SN_op_Multiply, OP_PMULQ, MONO_CPU_X86_SSE, SIMD_EMIT_BINARY },
{ SN_op_Subtraction, OP_PSUBQ, MONO_CPU_X86_SSE, SIMD_EMIT_BINARY },
{ SN_set_X, 0, MONO_CPU_X86_SSE, SIMD_EMIT_SETTER },
{ SN_set_Y, 1, MONO_CPU_X86_SSE, SIMD_EMIT_SETTER },
};
static const SimdIntrinsic vector4ui_intrinsics[] = {
{ SN_ctor, OP_EXPAND_I4, MONO_CPU_X86_SSE, SIMD_EMIT_CTOR },
{ SN_ArithmeticRightShift, OP_PSARD, MONO_CPU_X86_SSE, SIMD_EMIT_SHIFT },
{ SN_CompareEqual, OP_PCMPEQD, MONO_CPU_X86_SSE, SIMD_EMIT_BINARY },
{ SN_LoadAligned, 0, MONO_CPU_X86_SSE, SIMD_EMIT_LOAD_ALIGNED },
{ SN_Max, OP_PMAXD_UN, MONO_CPU_X86_SSE41, SIMD_EMIT_BINARY },
{ SN_Min, OP_PMIND_UN, MONO_CPU_X86_SSE41, SIMD_EMIT_BINARY },
{ SN_PrefetchTemporalAllCacheLevels, 0, MONO_CPU_X86_SSE, SIMD_EMIT_PREFETCH, SIMD_PREFETCH_MODE_0 },
{ SN_PrefetchTemporal1stLevelCache, 0, MONO_CPU_X86_SSE, SIMD_EMIT_PREFETCH, SIMD_PREFETCH_MODE_1 },
{ SN_PrefetchTemporal2ndLevelCache, 0, MONO_CPU_X86_SSE, SIMD_EMIT_PREFETCH, SIMD_PREFETCH_MODE_2 },
{ SN_PrefetchNonTemporal, 0, MONO_CPU_X86_SSE, SIMD_EMIT_PREFETCH, SIMD_PREFETCH_MODE_NTA },
{ SN_Shuffle, OP_PSHUFLED, MONO_CPU_X86_SSE, SIMD_EMIT_SHUFFLE },
{ SN_SignedPackWithSignedSaturation, OP_PACKD, MONO_CPU_X86_SSE, SIMD_EMIT_BINARY },
{ SN_SignedPackWithUnsignedSaturation, OP_PACKD_UN, MONO_CPU_X86_SSE41, SIMD_EMIT_BINARY },
{ SN_StoreAligned, OP_STOREX_ALIGNED_MEMBASE_REG, MONO_CPU_X86_SSE, SIMD_EMIT_STORE },
{ SN_UnpackHigh, OP_UNPACK_HIGHD, MONO_CPU_X86_SSE, SIMD_EMIT_BINARY },
{ SN_UnpackLow, OP_UNPACK_LOWD, MONO_CPU_X86_SSE, SIMD_EMIT_BINARY },
{ SN_get_W, 3, MONO_CPU_X86_SSE, SIMD_EMIT_GETTER },
{ SN_get_X, 0, MONO_CPU_X86_SSE, SIMD_EMIT_GETTER },
{ SN_get_Y, 1, MONO_CPU_X86_SSE, SIMD_EMIT_GETTER },
{ SN_get_Z, 2, MONO_CPU_X86_SSE, SIMD_EMIT_GETTER },
{ SN_op_Addition, OP_PADDD, MONO_CPU_X86_SSE, SIMD_EMIT_BINARY },
{ SN_op_BitwiseAnd, OP_PAND, MONO_CPU_X86_SSE, SIMD_EMIT_BINARY },
{ SN_op_BitwiseOr, OP_POR, MONO_CPU_X86_SSE, SIMD_EMIT_BINARY },
{ SN_op_Equality, OP_PCMPEQD, MONO_CPU_X86_SSE, SIMD_EMIT_EQUALITY, SIMD_COMP_EQ },
{ SN_op_ExclusiveOr, OP_PXOR, MONO_CPU_X86_SSE, SIMD_EMIT_BINARY },
{ SN_op_Explicit, 0, MONO_CPU_X86_SSE, SIMD_EMIT_CAST },
{ SN_op_Inequality, OP_PCMPEQD, MONO_CPU_X86_SSE, SIMD_EMIT_EQUALITY, SIMD_COMP_NEQ },
{ SN_op_LeftShift, OP_PSHLD, MONO_CPU_X86_SSE, SIMD_EMIT_SHIFT },
{ SN_op_Multiply, OP_PMULD, MONO_CPU_X86_SSE41, SIMD_EMIT_BINARY },
{ SN_op_RightShift, OP_PSHRD, MONO_CPU_X86_SSE, SIMD_EMIT_SHIFT },
{ SN_op_Subtraction, OP_PSUBD, MONO_CPU_X86_SSE, SIMD_EMIT_BINARY },
{ SN_set_W, 3, MONO_CPU_X86_SSE, SIMD_EMIT_SETTER },
{ SN_set_X, 0, MONO_CPU_X86_SSE, SIMD_EMIT_SETTER },
{ SN_set_Y, 1, MONO_CPU_X86_SSE, SIMD_EMIT_SETTER },
{ SN_set_Z, 2, MONO_CPU_X86_SSE, SIMD_EMIT_SETTER },
};
static const SimdIntrinsic vector4i_intrinsics[] = {
{ SN_ctor, OP_EXPAND_I4, MONO_CPU_X86_SSE, SIMD_EMIT_CTOR },
{ SN_CompareEqual, OP_PCMPEQD, MONO_CPU_X86_SSE, SIMD_EMIT_BINARY },
{ SN_CompareGreaterThan, OP_PCMPGTD, MONO_CPU_X86_SSE, SIMD_EMIT_BINARY },
{ SN_ConvertToDouble, OP_CVTDQ2PD, MONO_CPU_X86_SSE2, SIMD_EMIT_UNARY },
{ SN_ConvertToFloat, OP_CVTDQ2PS, MONO_CPU_X86_SSE2, SIMD_EMIT_UNARY },
{ SN_LoadAligned, 0, MONO_CPU_X86_SSE, SIMD_EMIT_LOAD_ALIGNED },
{ SN_LogicalRightShift, OP_PSHRD, MONO_CPU_X86_SSE, SIMD_EMIT_SHIFT },
{ SN_Max, OP_PMAXD, MONO_CPU_X86_SSE41, SIMD_EMIT_BINARY },
{ SN_Min, OP_PMIND, MONO_CPU_X86_SSE41, SIMD_EMIT_BINARY },
{ SN_PackWithSignedSaturation, OP_PACKD, MONO_CPU_X86_SSE, SIMD_EMIT_BINARY },
{ SN_PackWithUnsignedSaturation, OP_PACKD_UN, MONO_CPU_X86_SSE41, SIMD_EMIT_BINARY },
{ SN_PrefetchTemporalAllCacheLevels, 0, MONO_CPU_X86_SSE, SIMD_EMIT_PREFETCH, SIMD_PREFETCH_MODE_0 },
{ SN_PrefetchTemporal1stLevelCache, 0, MONO_CPU_X86_SSE, SIMD_EMIT_PREFETCH, SIMD_PREFETCH_MODE_1 },
{ SN_PrefetchTemporal2ndLevelCache, 0, MONO_CPU_X86_SSE, SIMD_EMIT_PREFETCH, SIMD_PREFETCH_MODE_2 },
{ SN_PrefetchNonTemporal, 0, MONO_CPU_X86_SSE, SIMD_EMIT_PREFETCH, SIMD_PREFETCH_MODE_NTA },
{ SN_Shuffle, OP_PSHUFLED, MONO_CPU_X86_SSE, SIMD_EMIT_SHUFFLE },
{ SN_StoreAligned, OP_STOREX_ALIGNED_MEMBASE_REG, MONO_CPU_X86_SSE, SIMD_EMIT_STORE },
{ SN_UnpackHigh, OP_UNPACK_HIGHD, MONO_CPU_X86_SSE, SIMD_EMIT_BINARY },
{ SN_UnpackLow, OP_UNPACK_LOWD, MONO_CPU_X86_SSE, SIMD_EMIT_BINARY },
{ SN_get_W, 3, MONO_CPU_X86_SSE, SIMD_EMIT_GETTER },
{ SN_get_X, 0, MONO_CPU_X86_SSE, SIMD_EMIT_GETTER },
{ SN_get_Y, 1, MONO_CPU_X86_SSE, SIMD_EMIT_GETTER },
{ SN_get_Z, 2, MONO_CPU_X86_SSE, SIMD_EMIT_GETTER },
{ SN_op_Addition, OP_PADDD, MONO_CPU_X86_SSE, SIMD_EMIT_BINARY },
{ SN_op_BitwiseAnd, OP_PAND, MONO_CPU_X86_SSE, SIMD_EMIT_BINARY },
{ SN_op_BitwiseOr, OP_POR, MONO_CPU_X86_SSE, SIMD_EMIT_BINARY },
{ SN_op_Equality, OP_PCMPEQD, MONO_CPU_X86_SSE, SIMD_EMIT_EQUALITY, SIMD_COMP_EQ },
{ SN_op_ExclusiveOr, OP_PXOR, MONO_CPU_X86_SSE, SIMD_EMIT_BINARY },
{ SN_op_Explicit, 0, MONO_CPU_X86_SSE, SIMD_EMIT_CAST },
{ SN_op_Inequality, OP_PCMPEQD, MONO_CPU_X86_SSE, SIMD_EMIT_EQUALITY, SIMD_COMP_NEQ },
{ SN_op_LeftShift, OP_PSHLD, MONO_CPU_X86_SSE, SIMD_EMIT_SHIFT },
{ SN_op_Multiply, OP_PMULD, MONO_CPU_X86_SSE41, SIMD_EMIT_BINARY },
{ SN_op_RightShift, OP_PSARD, MONO_CPU_X86_SSE, SIMD_EMIT_SHIFT },
{ SN_op_Subtraction, OP_PSUBD, MONO_CPU_X86_SSE, SIMD_EMIT_BINARY },
{ SN_set_W, 3, MONO_CPU_X86_SSE, SIMD_EMIT_SETTER },
{ SN_set_X, 0, MONO_CPU_X86_SSE, SIMD_EMIT_SETTER },
{ SN_set_Y, 1, MONO_CPU_X86_SSE, SIMD_EMIT_SETTER },
{ SN_set_Z, 2, MONO_CPU_X86_SSE, SIMD_EMIT_SETTER },
};
static const SimdIntrinsic vector8us_intrinsics[] = {
{ SN_ctor, OP_EXPAND_I2, MONO_CPU_X86_SSE, SIMD_EMIT_CTOR },
{ SN_AddWithSaturation, OP_PADDW_SAT_UN, MONO_CPU_X86_SSE, SIMD_EMIT_BINARY },
{ SN_ArithmeticRightShift, OP_PSARW, MONO_CPU_X86_SSE, SIMD_EMIT_SHIFT },
{ SN_Average, OP_PAVGW_UN, MONO_CPU_X86_SSE, SIMD_EMIT_BINARY },
{ SN_CompareEqual, OP_PCMPEQW, MONO_CPU_X86_SSE, SIMD_EMIT_BINARY, MONO_CPU_X86_SSE },
{ SN_LoadAligned, 0, MONO_CPU_X86_SSE, SIMD_EMIT_LOAD_ALIGNED },
{ SN_Max, OP_PMAXW_UN, MONO_CPU_X86_SSE41, SIMD_EMIT_BINARY },
{ SN_Min, OP_PMINW_UN, MONO_CPU_X86_SSE41, SIMD_EMIT_BINARY },
{ SN_MultiplyStoreHigh, OP_PMULW_HIGH_UN, MONO_CPU_X86_SSE, SIMD_EMIT_BINARY },
{ SN_PrefetchTemporalAllCacheLevels, 0, MONO_CPU_X86_SSE, SIMD_EMIT_PREFETCH, SIMD_PREFETCH_MODE_0 },
{ SN_PrefetchTemporal1stLevelCache, 0, MONO_CPU_X86_SSE, SIMD_EMIT_PREFETCH, SIMD_PREFETCH_MODE_1 },
{ SN_PrefetchTemporal2ndLevelCache, 0, MONO_CPU_X86_SSE, SIMD_EMIT_PREFETCH, SIMD_PREFETCH_MODE_2 },
{ SN_PrefetchNonTemporal, 0, MONO_CPU_X86_SSE, SIMD_EMIT_PREFETCH, SIMD_PREFETCH_MODE_NTA },
{ SN_ShuffleHigh, OP_PSHUFLEW_HIGH, MONO_CPU_X86_SSE, SIMD_EMIT_SHUFFLE },
{ SN_ShuffleLow, OP_PSHUFLEW_LOW, MONO_CPU_X86_SSE, SIMD_EMIT_SHUFFLE },
{ SN_SignedPackWithSignedSaturation, OP_PACKW, MONO_CPU_X86_SSE, SIMD_EMIT_BINARY },
{ SN_SignedPackWithUnsignedSaturation, OP_PACKW_UN, MONO_CPU_X86_SSE, SIMD_EMIT_BINARY },
{ SN_StoreAligned, OP_STOREX_ALIGNED_MEMBASE_REG, MONO_CPU_X86_SSE, SIMD_EMIT_STORE },
{ SN_SubtractWithSaturation, OP_PSUBW_SAT_UN, MONO_CPU_X86_SSE, SIMD_EMIT_BINARY },
{ SN_UnpackHigh, OP_UNPACK_HIGHW, MONO_CPU_X86_SSE, SIMD_EMIT_BINARY },
{ SN_UnpackLow, OP_UNPACK_LOWW, MONO_CPU_X86_SSE, SIMD_EMIT_BINARY },
{ SN_get_V0, 0, MONO_CPU_X86_SSE, SIMD_EMIT_GETTER },
{ SN_get_V1, 1, MONO_CPU_X86_SSE, SIMD_EMIT_GETTER },
{ SN_get_V2, 2, MONO_CPU_X86_SSE, SIMD_EMIT_GETTER },
{ SN_get_V3, 3, MONO_CPU_X86_SSE, SIMD_EMIT_GETTER },
{ SN_get_V4, 4, MONO_CPU_X86_SSE, SIMD_EMIT_GETTER },
{ SN_get_V5, 5, MONO_CPU_X86_SSE, SIMD_EMIT_GETTER },
{ SN_get_V6, 6, MONO_CPU_X86_SSE, SIMD_EMIT_GETTER },
{ SN_get_V7, 7, MONO_CPU_X86_SSE, SIMD_EMIT_GETTER },
{ SN_op_Addition, OP_PADDW, MONO_CPU_X86_SSE, SIMD_EMIT_BINARY },
{ SN_op_BitwiseAnd, OP_PAND, MONO_CPU_X86_SSE, SIMD_EMIT_BINARY },
{ SN_op_BitwiseOr, OP_POR, MONO_CPU_X86_SSE, SIMD_EMIT_BINARY },
{ SN_op_Equality, OP_PCMPEQW, MONO_CPU_X86_SSE, SIMD_EMIT_EQUALITY, SIMD_COMP_EQ },
{ SN_op_ExclusiveOr, OP_PXOR, MONO_CPU_X86_SSE, SIMD_EMIT_BINARY },
{ SN_op_Explicit, 0, MONO_CPU_X86_SSE, SIMD_EMIT_CAST },
{ SN_op_Inequality, OP_PCMPEQW, MONO_CPU_X86_SSE, SIMD_EMIT_EQUALITY, SIMD_COMP_NEQ },
{ SN_op_LeftShift, OP_PSHLW, MONO_CPU_X86_SSE, SIMD_EMIT_SHIFT },
{ SN_op_Multiply, OP_PMULW, MONO_CPU_X86_SSE, SIMD_EMIT_BINARY },
{ SN_op_RightShift, OP_PSHRW, MONO_CPU_X86_SSE, SIMD_EMIT_SHIFT },
{ SN_op_Subtraction, OP_PSUBW, MONO_CPU_X86_SSE, SIMD_EMIT_BINARY },
{ SN_set_V0, 0, MONO_CPU_X86_SSE, SIMD_EMIT_SETTER },
{ SN_set_V1, 1, MONO_CPU_X86_SSE, SIMD_EMIT_SETTER },
{ SN_set_V2, 2, MONO_CPU_X86_SSE, SIMD_EMIT_SETTER },
{ SN_set_V3, 3, MONO_CPU_X86_SSE, SIMD_EMIT_SETTER },
{ SN_set_V4, 4, MONO_CPU_X86_SSE, SIMD_EMIT_SETTER },
{ SN_set_V5, 5, MONO_CPU_X86_SSE, SIMD_EMIT_SETTER },
{ SN_set_V6, 6, MONO_CPU_X86_SSE, SIMD_EMIT_SETTER },
{ SN_set_V7, 7, MONO_CPU_X86_SSE, SIMD_EMIT_SETTER },
};
static const SimdIntrinsic vector8s_intrinsics[] = {
{ SN_ctor, OP_EXPAND_I2, MONO_CPU_X86_SSE, SIMD_EMIT_CTOR },
{ SN_AddWithSaturation, OP_PADDW_SAT, MONO_CPU_X86_SSE, SIMD_EMIT_BINARY },
{ SN_CompareEqual, OP_PCMPEQW, MONO_CPU_X86_SSE, SIMD_EMIT_BINARY },
{ SN_CompareGreaterThan, OP_PCMPGTW, MONO_CPU_X86_SSE, SIMD_EMIT_BINARY },
{ SN_LoadAligned, 0, MONO_CPU_X86_SSE, SIMD_EMIT_LOAD_ALIGNED },
{ SN_LogicalRightShift, OP_PSHRW, MONO_CPU_X86_SSE, SIMD_EMIT_SHIFT },
{ SN_Max, OP_PMAXW, MONO_CPU_X86_SSE, SIMD_EMIT_BINARY },
{ SN_Min, OP_PMINW, MONO_CPU_X86_SSE, SIMD_EMIT_BINARY },
{ SN_MultiplyStoreHigh, OP_PMULW_HIGH, MONO_CPU_X86_SSE, SIMD_EMIT_BINARY },
{ SN_PackWithSignedSaturation, OP_PACKW, MONO_CPU_X86_SSE, SIMD_EMIT_BINARY },
{ SN_PackWithUnsignedSaturation, OP_PACKW_UN, MONO_CPU_X86_SSE, SIMD_EMIT_BINARY },
{ SN_PrefetchTemporalAllCacheLevels, 0, MONO_CPU_X86_SSE, SIMD_EMIT_PREFETCH, SIMD_PREFETCH_MODE_0 },
{ SN_PrefetchTemporal1stLevelCache, 0, MONO_CPU_X86_SSE, SIMD_EMIT_PREFETCH, SIMD_PREFETCH_MODE_1 },
{ SN_PrefetchTemporal2ndLevelCache, 0, MONO_CPU_X86_SSE, SIMD_EMIT_PREFETCH, SIMD_PREFETCH_MODE_2 },
{ SN_PrefetchNonTemporal, 0, MONO_CPU_X86_SSE, SIMD_EMIT_PREFETCH, SIMD_PREFETCH_MODE_NTA },
{ SN_ShuffleHigh, OP_PSHUFLEW_HIGH, MONO_CPU_X86_SSE, SIMD_EMIT_SHUFFLE },
{ SN_ShuffleLow, OP_PSHUFLEW_LOW, MONO_CPU_X86_SSE, SIMD_EMIT_SHUFFLE },
{ SN_StoreAligned, OP_STOREX_ALIGNED_MEMBASE_REG, MONO_CPU_X86_SSE, SIMD_EMIT_STORE },
{ SN_SubtractWithSaturation, OP_PSUBW_SAT_UN, MONO_CPU_X86_SSE, SIMD_EMIT_BINARY },
{ SN_UnpackHigh, OP_UNPACK_HIGHW, MONO_CPU_X86_SSE, SIMD_EMIT_BINARY },
{ SN_UnpackLow, OP_UNPACK_LOWW, MONO_CPU_X86_SSE, SIMD_EMIT_BINARY },
{ SN_get_V0, 0, MONO_CPU_X86_SSE, SIMD_EMIT_GETTER },
{ SN_get_V1, 1, MONO_CPU_X86_SSE, SIMD_EMIT_GETTER },
{ SN_get_V2, 2, MONO_CPU_X86_SSE, SIMD_EMIT_GETTER },
{ SN_get_V3, 3, MONO_CPU_X86_SSE, SIMD_EMIT_GETTER },
{ SN_get_V4, 4, MONO_CPU_X86_SSE, SIMD_EMIT_GETTER },
{ SN_get_V5, 5, MONO_CPU_X86_SSE, SIMD_EMIT_GETTER },
{ SN_get_V6, 6, MONO_CPU_X86_SSE, SIMD_EMIT_GETTER },
{ SN_get_V7, 7, MONO_CPU_X86_SSE, SIMD_EMIT_GETTER },
{ SN_op_Addition, OP_PADDW, MONO_CPU_X86_SSE, SIMD_EMIT_BINARY },
{ SN_op_BitwiseAnd, OP_PAND, MONO_CPU_X86_SSE, SIMD_EMIT_BINARY },
{ SN_op_BitwiseOr, OP_POR, MONO_CPU_X86_SSE, SIMD_EMIT_BINARY },
{ SN_op_Equality, OP_PCMPEQW, MONO_CPU_X86_SSE, SIMD_EMIT_EQUALITY, SIMD_COMP_EQ },
{ SN_op_ExclusiveOr, OP_PXOR, MONO_CPU_X86_SSE, SIMD_EMIT_BINARY },
{ SN_op_Explicit, 0, MONO_CPU_X86_SSE, SIMD_EMIT_CAST },
{ SN_op_Inequality, OP_PCMPEQW, MONO_CPU_X86_SSE, SIMD_EMIT_EQUALITY, SIMD_COMP_NEQ },
{ SN_op_LeftShift, OP_PSHLW, MONO_CPU_X86_SSE, SIMD_EMIT_SHIFT },
{ SN_op_Multiply, OP_PMULW, MONO_CPU_X86_SSE, SIMD_EMIT_BINARY },
{ SN_op_RightShift, OP_PSARW, MONO_CPU_X86_SSE, SIMD_EMIT_SHIFT },
{ SN_op_Subtraction, OP_PSUBW, MONO_CPU_X86_SSE, SIMD_EMIT_BINARY },
{ SN_set_V0, 0, MONO_CPU_X86_SSE, SIMD_EMIT_SETTER },
{ SN_set_V1, 1, MONO_CPU_X86_SSE, SIMD_EMIT_SETTER },
{ SN_set_V2, 2, MONO_CPU_X86_SSE, SIMD_EMIT_SETTER },
{ SN_set_V3, 3, MONO_CPU_X86_SSE, SIMD_EMIT_SETTER },
{ SN_set_V4, 4, MONO_CPU_X86_SSE, SIMD_EMIT_SETTER },
{ SN_set_V5, 5, MONO_CPU_X86_SSE, SIMD_EMIT_SETTER },
{ SN_set_V6, 6, MONO_CPU_X86_SSE, SIMD_EMIT_SETTER },
{ SN_set_V7, 7, MONO_CPU_X86_SSE, SIMD_EMIT_SETTER },
};
static const SimdIntrinsic vector16b_intrinsics[] = {
{ SN_ctor, OP_EXPAND_I1, MONO_CPU_X86_SSE, SIMD_EMIT_CTOR },
{ SN_AddWithSaturation, OP_PADDB_SAT_UN, MONO_CPU_X86_SSE, SIMD_EMIT_BINARY },
{ SN_Average, OP_PAVGB_UN, MONO_CPU_X86_SSE, SIMD_EMIT_BINARY },
{ SN_CompareEqual, OP_PCMPEQB, MONO_CPU_X86_SSE, SIMD_EMIT_BINARY },
{ SN_ExtractByteMask, 0, MONO_CPU_X86_SSE, SIMD_EMIT_EXTRACT_MASK },
{ SN_LoadAligned, 0, MONO_CPU_X86_SSE, SIMD_EMIT_LOAD_ALIGNED },
{ SN_Max, OP_PMAXB_UN, MONO_CPU_X86_SSE, SIMD_EMIT_BINARY },
{ SN_Min, OP_PMINB_UN, MONO_CPU_X86_SSE, SIMD_EMIT_BINARY },
{ SN_PrefetchTemporalAllCacheLevels, 0, MONO_CPU_X86_SSE, SIMD_EMIT_PREFETCH, SIMD_PREFETCH_MODE_0 },
{ SN_PrefetchTemporal1stLevelCache, 0, MONO_CPU_X86_SSE, SIMD_EMIT_PREFETCH, SIMD_PREFETCH_MODE_1 },
{ SN_PrefetchTemporal2ndLevelCache, 0, MONO_CPU_X86_SSE, SIMD_EMIT_PREFETCH, SIMD_PREFETCH_MODE_2 },
{ SN_PrefetchNonTemporal, 0, MONO_CPU_X86_SSE, SIMD_EMIT_PREFETCH, SIMD_PREFETCH_MODE_NTA },
{ SN_StoreAligned, OP_STOREX_ALIGNED_MEMBASE_REG, MONO_CPU_X86_SSE, SIMD_EMIT_STORE },
{ SN_SubtractWithSaturation, OP_PSUBB_SAT_UN, MONO_CPU_X86_SSE, SIMD_EMIT_BINARY },
{ SN_SumOfAbsoluteDifferences, OP_PSUM_ABS_DIFF, MONO_CPU_X86_SSE, SIMD_EMIT_BINARY },
{ SN_UnpackHigh, OP_UNPACK_HIGHB, MONO_CPU_X86_SSE, SIMD_EMIT_BINARY },
{ SN_UnpackLow, OP_UNPACK_LOWB, MONO_CPU_X86_SSE, SIMD_EMIT_BINARY },
{ SN_get_V0, 0, MONO_CPU_X86_SSE, SIMD_EMIT_GETTER },
{ SN_get_V1, 1, MONO_CPU_X86_SSE, SIMD_EMIT_GETTER },
{ SN_get_V10, 10, MONO_CPU_X86_SSE, SIMD_EMIT_GETTER },
{ SN_get_V11, 11, MONO_CPU_X86_SSE, SIMD_EMIT_GETTER },
{ SN_get_V12, 12, MONO_CPU_X86_SSE, SIMD_EMIT_GETTER },
{ SN_get_V13, 13, MONO_CPU_X86_SSE, SIMD_EMIT_GETTER },
{ SN_get_V14, 14, MONO_CPU_X86_SSE, SIMD_EMIT_GETTER },
{ SN_get_V15, 15, MONO_CPU_X86_SSE, SIMD_EMIT_GETTER },
{ SN_get_V2, 2, MONO_CPU_X86_SSE, SIMD_EMIT_GETTER },
{ SN_get_V3, 3, MONO_CPU_X86_SSE, SIMD_EMIT_GETTER },
{ SN_get_V4, 4, MONO_CPU_X86_SSE, SIMD_EMIT_GETTER },
{ SN_get_V5, 5, MONO_CPU_X86_SSE, SIMD_EMIT_GETTER },
{ SN_get_V6, 6, MONO_CPU_X86_SSE, SIMD_EMIT_GETTER },
{ SN_get_V7, 7, MONO_CPU_X86_SSE, SIMD_EMIT_GETTER },
{ SN_get_V8, 8, MONO_CPU_X86_SSE, SIMD_EMIT_GETTER },
{ SN_get_V9, 9, MONO_CPU_X86_SSE, SIMD_EMIT_GETTER },
{ SN_op_Addition, OP_PADDB, MONO_CPU_X86_SSE, SIMD_EMIT_BINARY },
{ SN_op_BitwiseAnd, OP_PAND, MONO_CPU_X86_SSE, SIMD_EMIT_BINARY },
{ SN_op_BitwiseOr, OP_POR, MONO_CPU_X86_SSE, SIMD_EMIT_BINARY },
{ SN_op_Equality, OP_PCMPEQB, MONO_CPU_X86_SSE, SIMD_EMIT_EQUALITY, SIMD_COMP_EQ },
{ SN_op_ExclusiveOr, OP_PXOR, MONO_CPU_X86_SSE, SIMD_EMIT_BINARY },
{ SN_op_Explicit, 0, MONO_CPU_X86_SSE, SIMD_EMIT_CAST },
{ SN_op_Inequality, OP_PCMPEQB, MONO_CPU_X86_SSE, SIMD_EMIT_EQUALITY, SIMD_COMP_NEQ },
{ SN_op_Subtraction, OP_PSUBB, MONO_CPU_X86_SSE, SIMD_EMIT_BINARY },
{ SN_set_V0, 0, MONO_CPU_X86_SSE, SIMD_EMIT_SETTER },
{ SN_set_V1, 1, MONO_CPU_X86_SSE, SIMD_EMIT_SETTER },
{ SN_set_V10, 10, MONO_CPU_X86_SSE, SIMD_EMIT_SETTER },
{ SN_set_V11, 11, MONO_CPU_X86_SSE, SIMD_EMIT_SETTER },
{ SN_set_V12, 12, MONO_CPU_X86_SSE, SIMD_EMIT_SETTER },
{ SN_set_V13, 13, MONO_CPU_X86_SSE, SIMD_EMIT_SETTER },
{ SN_set_V14, 14, MONO_CPU_X86_SSE, SIMD_EMIT_SETTER },
{ SN_set_V15, 15, MONO_CPU_X86_SSE, SIMD_EMIT_SETTER },
{ SN_set_V2, 2, MONO_CPU_X86_SSE, SIMD_EMIT_SETTER },
{ SN_set_V3, 3, MONO_CPU_X86_SSE, SIMD_EMIT_SETTER },
{ SN_set_V4, 4, MONO_CPU_X86_SSE, SIMD_EMIT_SETTER },
{ SN_set_V5, 5, MONO_CPU_X86_SSE, SIMD_EMIT_SETTER },
{ SN_set_V6, 6, MONO_CPU_X86_SSE, SIMD_EMIT_SETTER },
{ SN_set_V7, 7, MONO_CPU_X86_SSE, SIMD_EMIT_SETTER },
{ SN_set_V8, 8, MONO_CPU_X86_SSE, SIMD_EMIT_SETTER },
{ SN_set_V9, 9, MONO_CPU_X86_SSE, SIMD_EMIT_SETTER },
};
/*
Missing:
setters
*/
static const SimdIntrinsic vector16sb_intrinsics[] = {
{ SN_ctor, OP_EXPAND_I1, MONO_CPU_X86_SSE, SIMD_EMIT_CTOR },
{ SN_AddWithSaturation, OP_PADDB_SAT, MONO_CPU_X86_SSE, SIMD_EMIT_BINARY },
{ SN_CompareEqual, OP_PCMPEQB, MONO_CPU_X86_SSE, SIMD_EMIT_BINARY },
{ SN_CompareGreaterThan, OP_PCMPGTB, MONO_CPU_X86_SSE, SIMD_EMIT_BINARY },
{ SN_ExtractByteMask, 0, MONO_CPU_X86_SSE, SIMD_EMIT_EXTRACT_MASK },
{ SN_LoadAligned, 0, MONO_CPU_X86_SSE, SIMD_EMIT_LOAD_ALIGNED },
{ SN_Max, OP_PMAXB, MONO_CPU_X86_SSE41, SIMD_EMIT_BINARY },
{ SN_Min, OP_PMINB, MONO_CPU_X86_SSE41, SIMD_EMIT_BINARY },
{ SN_PrefetchTemporalAllCacheLevels, 0, MONO_CPU_X86_SSE, SIMD_EMIT_PREFETCH, SIMD_PREFETCH_MODE_0 },
{ SN_PrefetchTemporal1stLevelCache, 0, MONO_CPU_X86_SSE, SIMD_EMIT_PREFETCH, SIMD_PREFETCH_MODE_1 },
{ SN_PrefetchTemporal2ndLevelCache, 0, MONO_CPU_X86_SSE, SIMD_EMIT_PREFETCH, SIMD_PREFETCH_MODE_2 },
{ SN_PrefetchNonTemporal, 0, MONO_CPU_X86_SSE, SIMD_EMIT_PREFETCH, SIMD_PREFETCH_MODE_NTA },
{ SN_StoreAligned, OP_STOREX_ALIGNED_MEMBASE_REG, MONO_CPU_X86_SSE, SIMD_EMIT_STORE },
{ SN_SubtractWithSaturation, OP_PSUBB_SAT, MONO_CPU_X86_SSE, SIMD_EMIT_BINARY },
{ SN_UnpackHigh, OP_UNPACK_HIGHB, MONO_CPU_X86_SSE, SIMD_EMIT_BINARY },
{ SN_UnpackLow, OP_UNPACK_LOWB, MONO_CPU_X86_SSE, SIMD_EMIT_BINARY },
{ SN_get_V0, 0, MONO_CPU_X86_SSE, SIMD_EMIT_GETTER },
{ SN_get_V1, 1, MONO_CPU_X86_SSE, SIMD_EMIT_GETTER },
{ SN_get_V10, 10, MONO_CPU_X86_SSE, SIMD_EMIT_GETTER },
{ SN_get_V11, 11, MONO_CPU_X86_SSE, SIMD_EMIT_GETTER },
{ SN_get_V12, 12, MONO_CPU_X86_SSE, SIMD_EMIT_GETTER },
{ SN_get_V13, 13, MONO_CPU_X86_SSE, SIMD_EMIT_GETTER },
{ SN_get_V14, 14, MONO_CPU_X86_SSE, SIMD_EMIT_GETTER },
{ SN_get_V15, 15, MONO_CPU_X86_SSE, SIMD_EMIT_GETTER },
{ SN_get_V2, 2, MONO_CPU_X86_SSE, SIMD_EMIT_GETTER },
{ SN_get_V3, 3, MONO_CPU_X86_SSE, SIMD_EMIT_GETTER },
{ SN_get_V4, 4, MONO_CPU_X86_SSE, SIMD_EMIT_GETTER },
{ SN_get_V5, 5, MONO_CPU_X86_SSE, SIMD_EMIT_GETTER },
{ SN_get_V6, 6, MONO_CPU_X86_SSE, SIMD_EMIT_GETTER },
{ SN_get_V7, 7, MONO_CPU_X86_SSE, SIMD_EMIT_GETTER },
{ SN_get_V8, 8, MONO_CPU_X86_SSE, SIMD_EMIT_GETTER },
{ SN_get_V9, 9, MONO_CPU_X86_SSE, SIMD_EMIT_GETTER },
{ SN_op_Addition, OP_PADDB, MONO_CPU_X86_SSE, SIMD_EMIT_BINARY },
{ SN_op_BitwiseAnd, OP_PAND, MONO_CPU_X86_SSE, SIMD_EMIT_BINARY },
{ SN_op_BitwiseOr, OP_POR, MONO_CPU_X86_SSE, SIMD_EMIT_BINARY },
{ SN_op_Equality, OP_PCMPEQB, MONO_CPU_X86_SSE, SIMD_EMIT_EQUALITY, SIMD_COMP_EQ },
{ SN_op_ExclusiveOr, OP_PXOR, MONO_CPU_X86_SSE, SIMD_EMIT_BINARY },
{ SN_op_Explicit, 0, MONO_CPU_X86_SSE, SIMD_EMIT_CAST },
{ SN_op_Inequality, OP_PCMPEQB, MONO_CPU_X86_SSE, SIMD_EMIT_EQUALITY, SIMD_COMP_NEQ },
{ SN_op_Subtraction, OP_PSUBB, MONO_CPU_X86_SSE, SIMD_EMIT_BINARY },
{ SN_set_V0, 0, MONO_CPU_X86_SSE, SIMD_EMIT_SETTER },
{ SN_set_V1, 1, MONO_CPU_X86_SSE, SIMD_EMIT_SETTER },
{ SN_set_V10, 10, MONO_CPU_X86_SSE, SIMD_EMIT_SETTER },
{ SN_set_V11, 11, MONO_CPU_X86_SSE, SIMD_EMIT_SETTER },
{ SN_set_V12, 12, MONO_CPU_X86_SSE, SIMD_EMIT_SETTER },
{ SN_set_V13, 13, MONO_CPU_X86_SSE, SIMD_EMIT_SETTER },
{ SN_set_V14, 14, MONO_CPU_X86_SSE, SIMD_EMIT_SETTER },
{ SN_set_V15, 15, MONO_CPU_X86_SSE, SIMD_EMIT_SETTER },
{ SN_set_V2, 2, MONO_CPU_X86_SSE, SIMD_EMIT_SETTER },
{ SN_set_V3, 3, MONO_CPU_X86_SSE, SIMD_EMIT_SETTER },
{ SN_set_V4, 4, MONO_CPU_X86_SSE, SIMD_EMIT_SETTER },
{ SN_set_V5, 5, MONO_CPU_X86_SSE, SIMD_EMIT_SETTER },
{ SN_set_V6, 6, MONO_CPU_X86_SSE, SIMD_EMIT_SETTER },
{ SN_set_V7, 7, MONO_CPU_X86_SSE, SIMD_EMIT_SETTER },
{ SN_set_V8, 8, MONO_CPU_X86_SSE, SIMD_EMIT_SETTER },
{ SN_set_V9, 9, MONO_CPU_X86_SSE, SIMD_EMIT_SETTER },
};
static MonoInst* emit_sys_numerics_intrinsics (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args);
static MonoInst* emit_sys_numerics_vectors_intrinsics (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args);
/*TODO match using number of parameters as well*/
static int
simd_intrinsic_compare_by_name (const void *key, const void *value)
{
return strcmp ((const char*)key, method_name (((SimdIntrinsic *)value)->name));
}
typedef enum {
VREG_USED = 0x01,
VREG_HAS_XZERO_BB0 = 0x02,
VREG_HAS_OTHER_OP_BB0 = 0x04,
VREG_SINGLE_BB_USE = 0x08,
VREG_MANY_BB_USE = 0x10,
} KillFlags;
void
mono_simd_intrinsics_init (void)
{
}
static gboolean
apply_vreg_first_block_interference (MonoCompile *cfg, MonoInst *ins, int reg, int max_vreg, char *vreg_flags)
{
if (reg != -1 && reg <= max_vreg && vreg_flags [reg]) {
vreg_flags [reg] &= ~VREG_HAS_XZERO_BB0;
vreg_flags [reg] |= VREG_HAS_OTHER_OP_BB0;
DEBUG (printf ("[simd-simplify] R%d used: ", reg); mono_print_ins(ins));
return TRUE;
}
return FALSE;
}
static gboolean
apply_vreg_following_block_interference (MonoCompile *cfg, MonoInst *ins, int reg, MonoBasicBlock *bb, int max_vreg, char *vreg_flags, MonoBasicBlock **target_bb)
{
if (reg == -1 || reg > max_vreg || !(vreg_flags [reg] & VREG_HAS_XZERO_BB0) || target_bb [reg] == bb)
return FALSE;
if (vreg_flags [reg] & VREG_SINGLE_BB_USE) {
vreg_flags [reg] &= ~VREG_SINGLE_BB_USE;
vreg_flags [reg] |= VREG_MANY_BB_USE;
DEBUG (printf ("[simd-simplify] R%d used by many bb: ", reg); mono_print_ins(ins));
return TRUE;
} else if (!(vreg_flags [reg] & VREG_MANY_BB_USE)) {
vreg_flags [reg] |= VREG_SINGLE_BB_USE;
target_bb [reg] = bb;
DEBUG (printf ("[simd-simplify] R%d first used by: ", reg); mono_print_ins(ins));
return TRUE;
}
return FALSE;
}
/*
This pass recalculate which vars need MONO_INST_INDIRECT.
We cannot do this for non SIMD vars since code like mono_get_vtable_var
uses MONO_INST_INDIRECT to signal that the variable must be stack allocated.
*/
void
mono_simd_simplify_indirection (MonoCompile *cfg)
{
int i, max_vreg = 0;
MonoBasicBlock *bb, *first_bb = NULL, **target_bb;
MonoInst *ins;
char *vreg_flags;
for (i = 0; i < cfg->num_varinfo; i++) {
MonoInst *var = cfg->varinfo [i];
if (m_class_is_simd_type (var->klass)) {
var->flags &= ~MONO_INST_INDIRECT;
max_vreg = MAX (var->dreg, max_vreg);
}
}
for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
if (!first_bb && bb->code)
first_bb = bb;
for (ins = bb->code; ins; ins = ins->next) {
if (ins->opcode == OP_LDADDR) {
MonoInst *var = (MonoInst*)ins->inst_p0;
if (m_class_is_simd_type (var->klass)) {
var->flags |= MONO_INST_INDIRECT;
}
}
}
}
DEBUG (printf ("[simd-simplify] max vreg is %d\n", max_vreg));
vreg_flags = (char *)g_malloc0 (max_vreg + 1);
target_bb = g_new0 (MonoBasicBlock*, max_vreg + 1);
for (i = 0; i < cfg->num_varinfo; i++) {
MonoInst *var = cfg->varinfo [i];
if (m_class_is_simd_type (var->klass) && !(var->flags & (MONO_INST_INDIRECT|MONO_INST_VOLATILE))) {
vreg_flags [var->dreg] = VREG_USED;
DEBUG (printf ("[simd-simplify] processing var %d with vreg %d\n", i, var->dreg));
}
}
/*Scan the first basic block looking xzeros not used*/
for (ins = first_bb->code; ins; ins = ins->next) {
int num_sregs;
int sregs [MONO_MAX_SRC_REGS];
if (ins->opcode == OP_XZERO) {
if (!(vreg_flags [ins->dreg] & VREG_HAS_OTHER_OP_BB0)) {
DEBUG (printf ("[simd-simplify] R%d has vzero: ", ins->dreg); mono_print_ins(ins));
vreg_flags [ins->dreg] |= VREG_HAS_XZERO_BB0;
}
continue;
}
if (ins->opcode == OP_LDADDR && apply_vreg_first_block_interference (cfg, ins, ((MonoInst*)ins->inst_p0)->dreg, max_vreg, vreg_flags))
continue;
if (apply_vreg_first_block_interference (cfg, ins, ins->dreg, max_vreg, vreg_flags))
continue;
num_sregs = mono_inst_get_src_registers (ins, sregs);
for (i = 0; i < num_sregs; ++i) {
if (apply_vreg_first_block_interference (cfg, ins, sregs [i], max_vreg, vreg_flags))
break;
}
}
if (IS_DEBUG_ON (cfg)) {
for (i = 0; i < cfg->num_varinfo; i++) {
MonoInst *var = cfg->varinfo [i];
if (m_class_is_simd_type (var->klass)) {
if ((vreg_flags [var->dreg] & VREG_HAS_XZERO_BB0))
DEBUG (printf ("[simd-simplify] R%d has xzero only\n", var->dreg));
if ((vreg_flags [var->dreg] & VREG_HAS_OTHER_OP_BB0))
DEBUG (printf ("[simd-simplify] R%d has other ops on bb0\n", var->dreg));
}
}
}
/*TODO stop here if no var is xzero only*/
/*
Scan all other bb and check if it has only one other use
Ideally this would be done after an extended bb formation pass
FIXME This pass could use dominator information to properly
place the XZERO on the bb that dominates all uses of the var,
but this will have zero effect with the current local reg alloc
TODO simply the use of flags.
*/
for (bb = first_bb->next_bb; bb; bb = bb->next_bb) {
for (ins = bb->code; ins; ins = ins->next) {
int num_sregs;
int sregs [MONO_MAX_SRC_REGS];
if (ins->opcode == OP_LDADDR && apply_vreg_following_block_interference (cfg, ins, ((MonoInst*)ins->inst_p0)->dreg, bb, max_vreg, vreg_flags, target_bb))
continue;
if (apply_vreg_following_block_interference (cfg, ins, ins->dreg, bb, max_vreg, vreg_flags, target_bb))
continue;
num_sregs = mono_inst_get_src_registers (ins, sregs);
for (i = 0; i < num_sregs; ++i) {
if (apply_vreg_following_block_interference (cfg, ins, sregs [i], bb,
max_vreg, vreg_flags, target_bb))
continue;
}
}
}
for (i = 0; i < cfg->num_varinfo; i++) {
MonoInst *var = cfg->varinfo [i];
if (!m_class_is_simd_type (var->klass))
continue;
if ((vreg_flags [var->dreg] & VREG_SINGLE_BB_USE))
DEBUG (printf ("[simd-simplify] R%d has single bb use\n", var->dreg));
if ((vreg_flags [var->dreg] & VREG_MANY_BB_USE))
DEBUG (printf ("[simd-simplify] R%d has many bb in use\n", var->dreg));
if (!(vreg_flags [var->dreg] & VREG_SINGLE_BB_USE))
continue;
for (ins = target_bb [var->dreg]->code; ins; ins = ins->next) {
int num_sregs, j;
int sregs [MONO_MAX_SRC_REGS];
gboolean found = FALSE;
num_sregs = mono_inst_get_src_registers (ins, sregs);
for (j = 0; j < num_sregs; ++j) {
if (sregs [j] == var->dreg)
found = TRUE;
}
/*We can avoid inserting the XZERO if the first use doesn't depend on the zero'ed value.*/
if (ins->dreg == var->dreg && !found) {
DEBUG (printf ("[simd-simplify] INGORING R%d on BB %d because first op is a def", i, target_bb [var->dreg]->block_num););
break;
} else if (found) {
DEBUG (printf ("[simd-simplify] Adding XZERO for R%d on BB %d: ", i, target_bb [var->dreg]->block_num); );
MonoInst *tmp;
MONO_INST_NEW (cfg, tmp, OP_XZERO);
tmp->dreg = var->dreg;
tmp->type = STACK_VTYPE;
tmp->klass = var->klass;
mono_bblock_insert_before_ins (target_bb [var->dreg], ins, tmp);
break;
}
}
}
for (ins = first_bb->code; ins; ins = ins->next) {
if (ins->opcode == OP_XZERO && (vreg_flags [ins->dreg] & VREG_SINGLE_BB_USE)) {
DEBUG (printf ("[simd-simplify] Nullify %d on first BB: ", ins->dreg); mono_print_ins(ins));
NULLIFY_INS (ins);
}
}
g_free (vreg_flags);
g_free (target_bb);
}
/*
* Windows x64 value type ABI uses reg/stack references (ArgValuetypeAddrInIReg/ArgValuetypeAddrOnStack)
* for function arguments. When using SIMD intrinsics arguments optimized into OP_ARG needs to be decomposed
* into correspondig SIMD LOADX/STOREX instructions.
*/
#if defined(TARGET_WIN32) && defined(TARGET_AMD64)
static gboolean
decompose_vtype_opt_uses_simd_intrinsics (MonoCompile *cfg, MonoInst *ins)
{
if (cfg->uses_simd_intrinsics & MONO_CFG_USES_SIMD_INTRINSICS_DECOMPOSE_VTYPE)
return TRUE;
switch (ins->opcode) {
case OP_XMOVE:
case OP_XZERO:
case OP_LOADX_MEMBASE:
case OP_LOADX_ALIGNED_MEMBASE:
case OP_STOREX_MEMBASE:
case OP_STOREX_ALIGNED_MEMBASE_REG:
return TRUE;
default:
return FALSE;
}
}
static void
decompose_vtype_opt_load_arg (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst *ins, gint32 *sreg_int32)
{
guint32 *sreg = (guint32*)sreg_int32;
MonoInst *src_var = get_vreg_to_inst (cfg, *sreg);
if (src_var && src_var->opcode == OP_ARG && src_var->klass && MONO_CLASS_IS_SIMD (cfg, src_var->klass)) {
MonoInst *varload_ins, *load_ins;
NEW_VARLOADA (cfg, varload_ins, src_var, src_var->inst_vtype);
mono_bblock_insert_before_ins (bb, ins, varload_ins);
MONO_INST_NEW (cfg, load_ins, OP_LOADX_MEMBASE);
load_ins->klass = src_var->klass;
load_ins->type = STACK_VTYPE;
load_ins->sreg1 = varload_ins->dreg;
load_ins->dreg = alloc_xreg (cfg);
mono_bblock_insert_after_ins (bb, varload_ins, load_ins);
*sreg = load_ins->dreg;
}
}
void
mono_simd_decompose_intrinsic (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst *ins)
{
if (cfg->opt & MONO_OPT_SIMD && decompose_vtype_opt_uses_simd_intrinsics (cfg, ins)) {
decompose_vtype_opt_load_arg (cfg, bb, ins, &(ins->sreg1));
decompose_vtype_opt_load_arg (cfg, bb, ins, &(ins->sreg2));
decompose_vtype_opt_load_arg (cfg, bb, ins, &(ins->sreg3));
MonoInst *dest_var = get_vreg_to_inst (cfg, ins->dreg);
if (dest_var && dest_var->opcode == OP_ARG && dest_var->klass && MONO_CLASS_IS_SIMD (cfg, dest_var->klass)) {
MonoInst *varload_ins, *store_ins;
ins->dreg = alloc_xreg (cfg);
NEW_VARLOADA (cfg, varload_ins, dest_var, dest_var->inst_vtype);
mono_bblock_insert_after_ins (bb, ins, varload_ins);
MONO_INST_NEW (cfg, store_ins, OP_STOREX_MEMBASE);
store_ins->klass = dest_var->klass;
store_ins->type = STACK_VTYPE;
store_ins->sreg1 = ins->dreg;
store_ins->dreg = varload_ins->dreg;
mono_bblock_insert_after_ins (bb, varload_ins, store_ins);
}
}
}
#else
void
mono_simd_decompose_intrinsic (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst *ins)
{
}
#endif /*defined(TARGET_WIN32) && defined(TARGET_AMD64)*/
/*
* This function expect that src be a value.
*/
static int
get_simd_vreg (MonoCompile *cfg, MonoMethod *cmethod, MonoInst *src)
{
const char *spec = INS_INFO (src->opcode);
if (src->opcode == OP_XMOVE) {
return src->sreg1;
} else if (spec [MONO_INST_DEST] == 'x') {
return src->dreg;
} else if (src->opcode == OP_VCALL || src->opcode == OP_VCALL_MEMBASE) {
return src->dreg;
}
g_warning ("get_simd_vreg:: could not infer source simd vreg for op");
mono_print_ins (src);
g_assert_not_reached ();
}
/*
* This function will load the value if needed.
*/
static int
load_simd_vreg_class (MonoCompile *cfg, MonoClass *klass, MonoInst *src, gboolean *indirect)
{
const char *spec = INS_INFO (src->opcode);
if (indirect)
*indirect = FALSE;
if (src->opcode == OP_XMOVE) {
return src->sreg1;
} else if (src->opcode == OP_LDADDR) {
int res = ((MonoInst*)src->inst_p0)->dreg;
return res;
} else if (spec [MONO_INST_DEST] == 'x') {
return src->dreg;
} else if (src->type == STACK_PTR || src->type == STACK_MP) {
MonoInst *ins;
if (indirect)
*indirect = TRUE;
MONO_INST_NEW (cfg, ins, OP_LOADX_MEMBASE);
ins->klass = klass;
ins->sreg1 = src->dreg;
ins->type = STACK_VTYPE;
ins->dreg = alloc_ireg (cfg);
MONO_ADD_INS (cfg->cbb, ins);
return ins->dreg;
}
g_warning ("load_simd_vreg:: could not infer source simd (%d) vreg for op", src->type);
mono_print_ins (src);
g_assert_not_reached ();
}
static int
load_simd_vreg (MonoCompile *cfg, MonoMethod *cmethod, MonoInst *src, gboolean *indirect)
{
return load_simd_vreg_class (cfg, cmethod->klass, src, indirect);
}
/*We share the var with fconv_to_r8_x to save some stack space.*/
static MonoInst*
get_double_spill_area (MonoCompile *cfg)
{
if (!cfg->fconv_to_r8_x_var) {
cfg->fconv_to_r8_x_var = mono_compile_create_var (cfg, m_class_get_byval_arg (mono_defaults.double_class), OP_LOCAL);
cfg->fconv_to_r8_x_var->flags |= MONO_INST_VOLATILE; /*FIXME, use the don't regalloc flag*/
}
return cfg->fconv_to_r8_x_var;
}
static MonoInst*
get_simd_ctor_spill_area (MonoCompile *cfg, MonoClass *avector_klass)
{
if (!cfg->simd_ctor_var) {
cfg->simd_ctor_var = mono_compile_create_var (cfg, m_class_get_byval_arg (avector_klass), OP_LOCAL);
cfg->simd_ctor_var->flags |= MONO_INST_VOLATILE; /*FIXME, use the don't regalloc flag*/
}
return cfg->simd_ctor_var;
}
static int
mono_type_to_expand_op (MonoType *type)
{
switch (type->type) {
case MONO_TYPE_I1:
case MONO_TYPE_U1:
return OP_EXPAND_I1;
case MONO_TYPE_I2:
case MONO_TYPE_U2:
return OP_EXPAND_I2;
case MONO_TYPE_I4:
case MONO_TYPE_U4:
return OP_EXPAND_I4;
case MONO_TYPE_I8:
case MONO_TYPE_U8:
return OP_EXPAND_I8;
case MONO_TYPE_R4:
return OP_EXPAND_R4;
case MONO_TYPE_R8:
return OP_EXPAND_R8;
default:
g_assert_not_reached ();
}
}
static int
type_to_comp_op (MonoType *t)
{
switch (t->type) {
case MONO_TYPE_I1:
case MONO_TYPE_U1:
return OP_PCMPEQB;