forked from blackmagic-debug/blackmagic
-
Notifications
You must be signed in to change notification settings - Fork 0
/
nrf51.c
335 lines (284 loc) · 10.9 KB
/
nrf51.c
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
/*
* This file is part of the Black Magic Debug project.
*
* Copyright (C) 2014 Mike Walters <mike@flomp.net>
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/* This file implements nRF51 target specific functions for detecting
* the device, providing the XML memory map and Flash memory programming.
*/
#include "general.h"
#include "target.h"
#include "target_internal.h"
#include "cortexm.h"
static int nrf51_flash_erase(struct target_flash *f, target_addr addr, size_t len);
static int nrf51_flash_write(struct target_flash *f,
target_addr dest, const void *src, size_t len);
static bool nrf51_cmd_erase_all(target *t);
static bool nrf51_cmd_read_hwid(target *t);
static bool nrf51_cmd_read_fwid(target *t);
static bool nrf51_cmd_read_deviceid(target *t);
static bool nrf51_cmd_read_deviceaddr(target *t);
static bool nrf51_cmd_read_help(target *t);
static bool nrf51_cmd_read(target *t, int argc, const char *argv[]);
const struct command_s nrf51_cmd_list[] = {
{"erase_mass", (cmd_handler)nrf51_cmd_erase_all, "Erase entire flash memory"},
{"read", (cmd_handler)nrf51_cmd_read, "Read device parameters"},
{NULL, NULL, NULL}
};
const struct command_s nrf51_read_cmd_list[] = {
{"help", (cmd_handler)nrf51_cmd_read_help, "Display help for read commands"},
{"hwid", (cmd_handler)nrf51_cmd_read_hwid, "Read hardware identification number"},
{"fwid", (cmd_handler)nrf51_cmd_read_fwid, "Read pre-loaded firmware ID"},
{"deviceid", (cmd_handler)nrf51_cmd_read_deviceid, "Read unique device ID"},
{"deviceaddr", (cmd_handler)nrf51_cmd_read_deviceaddr, "Read device address"},
{NULL, NULL, NULL}
};
/* Non-Volatile Memory Controller (NVMC) Registers */
#define NRF51_NVMC 0x4001E000
#define NRF51_NVMC_READY (NRF51_NVMC + 0x400)
#define NRF51_NVMC_CONFIG (NRF51_NVMC + 0x504)
#define NRF51_NVMC_ERASEPAGE (NRF51_NVMC + 0x508)
#define NRF51_NVMC_ERASEALL (NRF51_NVMC + 0x50C)
#define NRF51_NVMC_ERASEUICR (NRF51_NVMC + 0x514)
#define NRF51_NVMC_CONFIG_REN 0x0 // Read only access
#define NRF51_NVMC_CONFIG_WEN 0x1 // Write enable
#define NRF51_NVMC_CONFIG_EEN 0x2 // Erase enable
/* Factory Information Configuration Registers (FICR) */
#define NRF51_FICR 0x10000000
#define NRF51_FICR_CODEPAGESIZE (NRF51_FICR + 0x010)
#define NRF51_FICR_CODESIZE (NRF51_FICR + 0x014)
#define NRF51_FICR_CONFIGID (NRF51_FICR + 0x05C)
#define NRF51_FICR_DEVICEID_LOW (NRF51_FICR + 0x060)
#define NRF51_FICR_DEVICEID_HIGH (NRF51_FICR + 0x064)
#define NRF51_FICR_DEVICEADDRTYPE (NRF51_FICR + 0x0A0)
#define NRF51_FICR_DEVICEADDR_LOW (NRF51_FICR + 0x0A4)
#define NRF51_FICR_DEVICEADDR_HIGH (NRF51_FICR + 0x0A8)
/* User Information Configuration Registers (UICR) */
#define NRF51_UICR 0x10001000
#define NRF51_PAGE_SIZE 1024
#define NRF52_PAGE_SIZE 4096
#define SRAM_BASE 0x20000000
#define STUB_BUFFER_BASE (SRAM_BASE + 0x28)
static const uint16_t nrf51_flash_write_stub[] = {
#include "flashstub/nrf51.stub"
};
static void nrf51_add_flash(target *t,
uint32_t addr, size_t length, size_t erasesize)
{
struct target_flash *f = calloc(1, sizeof(*f));
f->start = addr;
f->length = length;
f->blocksize = erasesize;
f->erase = nrf51_flash_erase;
f->write = nrf51_flash_write;
f->align = 4;
f->erased = 0xff;
target_add_flash(t, f);
}
bool nrf51_probe(target *t)
{
t->idcode = target_mem_read32(t, NRF51_FICR_CONFIGID) & 0xFFFF;
switch (t->idcode) {
case 0x001D: /* nRF51822 (rev 1) QFAA CA/C0 */
case 0x001E: /* nRF51422 (rev 1) QFAA CA */
case 0x0020: /* nRF51822 (rev 1) CEAA BA */
case 0x0024: /* nRF51422 (rev 1) QFAA C0 */
case 0x002A: /* nRF51822 (rev 2) QFAA FA0 */
case 0x002D: /* nRF51422 (rev 2) QFAA DAA */
case 0x002E: /* nRF51422 (rev 2) QFAA E0 */
case 0x002F: /* nRF51822 (rev 1) CEAA B0 */
case 0x0031: /* nRF51422 (rev 1) CEAA A0A */
case 0x003C: /* nRF51822 (rev 2) QFAA G0 */
case 0x0057: /* nRF51422 (rev 2) QFAA G2 */
case 0x0040: /* nRF51822 (rev 2) CEAA CA0 */
case 0x0044: /* nRF51822 (rev 2) QFAA GC0 */
case 0x0047: /* nRF51822 (rev 2) CEAA DA0 */
case 0x004D: /* nRF51822 (rev 2) CEAA D00 */
case 0x0050: /* nRF51422 (rev 2) CEAA B0 */
case 0x0072: /* nRF51822 (rev 3) QFAA H0 */
case 0x0073: /* nRF51422 (rev 3) QFAA F0 */
case 0x0079: /* nRF51822 (rev 3) CEAA E0 */
case 0x007A: /* nRF51422 (rev 3) CEAA C0 */
case 0x008F: /* nRF51822 (rev 3) QFAA H1 See https://devzone.nordicsemi.com/question/97769/can-someone-conform-the-config-id-code-for-the-nrf51822qfaah1/ */
t->driver = "Nordic nRF51";
target_add_ram(t, 0x20000000, 0x4000);
nrf51_add_flash(t, 0x00000000, 0x40000, NRF51_PAGE_SIZE);
nrf51_add_flash(t, NRF51_UICR, 0x100, 0x100);
target_add_commands(t, nrf51_cmd_list, "nRF51");
return true;
case 0x0026: /* nRF51822 (rev 1) QFAB AA */
case 0x0027: /* nRF51822 (rev 1) QFAB A0 */
case 0x004C: /* nRF51822 (rev 2) QFAB B0 */
case 0x0061: /* nRF51422 (rev 2) QFAB A00 */
case 0x007B: /* nRF51822 (rev 3) QFAB C0 */
case 0x007C: /* nRF51422 (rev 3) QFAB B0 */
case 0x007D: /* nRF51822 (rev 3) CDAB A0 */
case 0x007E: /* nRF51422 (rev 3) CDAB A0 */
t->driver = "Nordic nRF51";
target_add_ram(t, 0x20000000, 0x4000);
nrf51_add_flash(t, 0x00000000, 0x20000, NRF51_PAGE_SIZE);
nrf51_add_flash(t, NRF51_UICR, 0x100, 0x100);
target_add_commands(t, nrf51_cmd_list, "nRF51");
return true;
case 0x0071: /* nRF51422 (rev 3) QFAC AB */
case 0x0083: /* nRF51822 (rev 3) QFAC A0 */
case 0x0084: /* nRF51422 (rev 3) QFAC A1 */
case 0x0085: /* nRF51422 (rev 3) QFAC A0 */
case 0x0086: /* nRF51422 (rev 3) QFAC A1 */
case 0x0087: /* nRF51822 (rev 3) CFAC A0 */
case 0x0088: /* nRF51422 (rev 3) CFAC A0 */
t->driver = "Nordic nRF51";
target_add_ram(t, 0x20000000, 0x8000);
nrf51_add_flash(t, 0x00000000, 0x40000, NRF51_PAGE_SIZE);
nrf51_add_flash(t, NRF51_UICR, 0x100, 0x100);
target_add_commands(t, nrf51_cmd_list, "nRF51");
return true;
case 0x00AC: /* nRF52832 Preview QFAA BA0 */
case 0x00C7: /* nRF52832 Revision 1 QFAA B00 */
t->driver = "Nordic nRF52";
target_add_ram(t, 0x20000000, 64*1024);
nrf51_add_flash(t, 0x00000000, 512*1024, NRF52_PAGE_SIZE);
nrf51_add_flash(t, NRF51_UICR, 0x100, 0x100);
target_add_commands(t, nrf51_cmd_list, "nRF52");
return true;
}
return false;
}
static int nrf51_flash_erase(struct target_flash *f, target_addr addr, size_t len)
{
target *t = f->t;
/* Enable erase */
target_mem_write32(t, NRF51_NVMC_CONFIG, NRF51_NVMC_CONFIG_EEN);
/* Poll for NVMC_READY */
while (target_mem_read32(t, NRF51_NVMC_READY) == 0)
if(target_check_error(t))
return -1;
while (len) {
if (addr == NRF51_UICR) { // Special Case
/* Write to the ERASE_UICR register to erase */
target_mem_write32(t, NRF51_NVMC_ERASEUICR, 0x1);
} else { // Standard Flash Page
/* Write address of first word in page to erase it */
target_mem_write32(t, NRF51_NVMC_ERASEPAGE, addr);
}
/* Poll for NVMC_READY */
while (target_mem_read32(t, NRF51_NVMC_READY) == 0)
if(target_check_error(t))
return -1;
addr += f->blocksize;
len -= f->blocksize;
}
/* Return to read-only */
target_mem_write32(t, NRF51_NVMC_CONFIG, NRF51_NVMC_CONFIG_REN);
/* Poll for NVMC_READY */
while (target_mem_read32(t, NRF51_NVMC_READY) == 0)
if(target_check_error(t))
return -1;
return 0;
}
static int nrf51_flash_write(struct target_flash *f,
target_addr dest, const void *src, size_t len)
{
target *t = f->t;
uint32_t data[2 + len/4];
/* FIXME rewrite stub to use register args */
/* Construct data buffer used by stub */
data[0] = dest;
data[1] = len; /* length must always be a multiple of 4 */
memcpy((uint8_t *)&data[2], src, len);
/* Enable write */
target_mem_write32(t, NRF51_NVMC_CONFIG, NRF51_NVMC_CONFIG_WEN);
/* Poll for NVMC_READY */
while (target_mem_read32(t, NRF51_NVMC_READY) == 0)
if(target_check_error(t))
return -1;
/* Write stub and data to target ram and call stub */
target_mem_write(t, SRAM_BASE, nrf51_flash_write_stub,
sizeof(nrf51_flash_write_stub));
target_mem_write(t, STUB_BUFFER_BASE, data, len + 8);
cortexm_run_stub(t, SRAM_BASE, 0, 0, 0, 0);
/* Return to read-only */
target_mem_write32(t, NRF51_NVMC_CONFIG, NRF51_NVMC_CONFIG_REN);
return 0;
}
static bool nrf51_cmd_erase_all(target *t)
{
tc_printf(t, "erase..\n");
/* Enable erase */
target_mem_write32(t, NRF51_NVMC_CONFIG, NRF51_NVMC_CONFIG_EEN);
/* Poll for NVMC_READY */
while (target_mem_read32(t, NRF51_NVMC_READY) == 0)
if(target_check_error(t))
return false;
/* Erase all */
target_mem_write32(t, NRF51_NVMC_ERASEALL, 1);
/* Poll for NVMC_READY */
while (target_mem_read32(t, NRF51_NVMC_READY) == 0)
if(target_check_error(t))
return false;
return true;
}
static bool nrf51_cmd_read_hwid(target *t)
{
uint32_t hwid = target_mem_read32(t, NRF51_FICR_CONFIGID) & 0xFFFF;
tc_printf(t, "Hardware ID: 0x%04X\n", hwid);
return true;
}
static bool nrf51_cmd_read_fwid(target *t)
{
uint32_t fwid = (target_mem_read32(t, NRF51_FICR_CONFIGID) >> 16) & 0xFFFF;
tc_printf(t, "Firmware ID: 0x%04X\n", fwid);
return true;
}
static bool nrf51_cmd_read_deviceid(target *t)
{
uint32_t deviceid_low = target_mem_read32(t, NRF51_FICR_DEVICEID_LOW);
uint32_t deviceid_high = target_mem_read32(t, NRF51_FICR_DEVICEID_HIGH);
tc_printf(t, "Device ID: 0x%08X%08X\n", deviceid_high, deviceid_low);
return true;
}
static bool nrf51_cmd_read_deviceaddr(target *t)
{
uint32_t addr_type = target_mem_read32(t, NRF51_FICR_DEVICEADDRTYPE);
uint32_t addr_low = target_mem_read32(t, NRF51_FICR_DEVICEADDR_LOW);
uint32_t addr_high = target_mem_read32(t, NRF51_FICR_DEVICEADDR_HIGH) & 0xFFFF;
if ((addr_type & 1) == 0) {
tc_printf(t, "Publicly Listed Address: 0x%04X%08X\n", addr_high, addr_low);
} else {
tc_printf(t, "Randomly Assigned Address: 0x%04X%08X\n", addr_high, addr_low);
}
return true;
}
static bool nrf51_cmd_read_help(target *t)
{
const struct command_s *c;
tc_printf(t, "Read commands:\n");
for(c = nrf51_read_cmd_list; c->cmd; c++)
tc_printf(t, "\t%s -- %s\n", c->cmd, c->help);
return true;
}
static bool nrf51_cmd_read(target *t, int argc, const char *argv[])
{
const struct command_s *c;
for(c = nrf51_read_cmd_list; c->cmd; c++) {
/* Accept a partial match as GDB does.
* So 'mon ver' will match 'monitor version'
*/
if(!strncmp(argv[1], c->cmd, strlen(argv[1])))
return !c->handler(t, argc - 1, &argv[1]);
}
return nrf51_cmd_read_help(t);
}