This branch contains the following VHDL/Verilog IP Code:
Project name: configurable_cordic_core_in_verilog
Project category: arithmetic_core
Project branch: arithmetic_core_configurable_cordic_core_in_verilog
This whole github repository is huge and, since IP cores are stored in separate branches, it is a good idea to just download the branch that you are interested in. This branch can be downloaded with the git command.
git clone -b arithmetic_core_configurable_cordic_core_in_verilog --single-branch https://github.com/fabriziotappero/ip-cores.git
A cool searchable index of the whole repo is available from www.freerangefactory.org.
This code of each IP core was taken "as is" from the website opencores.org. The copyright owner of each IP code is the author of the code itself. For more information refer to the index.html or go to the website opencores.org
This code is free software; you can redistribute it and/or modify it under the terms of the http://www.gnu.org/licenses/gpl.html (GNU General Public License) as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version.
This code is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.