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ZYNQ7010_DMA_NO_SG.xpr
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ZYNQ7010_DMA_NO_SG.xpr
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<?xml version="1.0" encoding="UTF-8"?>
<!-- Product Version: Vivado v2022.1 (64-bit) -->
<!-- -->
<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -->
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<MsgAttr Name="Id" Val="BD 41-1348"/>
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<MsgAttr Name="CreatedTimestamp" Val=""/>
<MsgAttr Name="StringsToMatch" Val="CRITICAL WARNING: [BD 41-1348] Reset pin /axi_dma_0/axi_resetn (associated clock /axi_dma_0/s_axi_lite_aclk) is connected to asynchronous reset source /PSys/FCLK_RESET1_N.
This may prevent design from meeting timing. Please add Processor System Reset module to create a reset that is synchronous to the associated clock source /PSys/FCLK_CLK0."/>
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<Dashboard Name="default_dashboard">
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<Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
</Gadget>
<Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
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<Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
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<Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
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