Consider trading conditional branch ranges for more type D instructions

[mbitsnbites]

We currently have 8 conditional branches. We could combine all branch instructions into a single type-D instructions by reducing the branch range by 3 bits (from 21 bits to 18 bits).

Motivation:

• Type-D instruction space is very limited.
• Conditional branches typically do not need a very wide address range.

[mbitsnbites]

Another thing to consider for conditional branch instructions is a branch-hint field (provided that we have bits to spare and we're going for a completely new instruction encoding format anyway). It would typically require two bits, e.g.:

Hint	Meaning
00	No hint
01	No hint (reserved)
10	The branch is very likely not to be taken
11	The branch is very likely to be taken

[mbitsnbites]

Yet another thing to consider is if we want to reserve a bit in the instruction encoding for the possibility to use a vector register as a branch condition (see https://www.bitsnbites.eu/ideas-for-mrisc32-vector-operations/).