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Enable arbitrary (multiple of 2) dividers for clock generation #8
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Here some statistics from the logic-analyzer when running from a divider of 1 to a divider of 1024
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So we have not a Power of 2 but a multiple of 2 Rule! |
The data should be in the repo shortly. Here how it was created:
(Using: http://github.com/KnCMiner/spi-test.git as the test tool) Here is how the data has been analyzed:
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Implemented 5b853b4 with the "multiple of 2" divider approach |
The documentation says that the clock multiplier should be of power 2 while experimentation shows that a multiple of 2 is sufficient
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