forked from hemanth-VP/SystemVerilog_Course
-
Notifications
You must be signed in to change notification settings - Fork 0
/
rand_log.log
37 lines (37 loc) · 1.46 KB
/
rand_log.log
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
# vsim rand_var -l rand_log.log -c -do "run -all; exit;"
# Start time: 04:37:55 on Sep 16,2022
# ** Note: (vsim-8009) Loading existing optimized design _opt
# // Questa Sim
# // Version 10.6c linux Jul 25 2017
# //
# // Copyright 1991-2017 Mentor Graphics Corporation
# // All Rights Reserved.
# //
# // QuestaSim and its associated documentation contain trade
# // secrets and commercial or financial information that are the property of
# // Mentor Graphics Corporation and are privileged, confidential,
# // and exempt from disclosure under the Freedom of Information Act,
# // 5 U.S.C. Section 552. Furthermore, this information
# // is prohibited from disclosure under the Trade Secrets Act,
# // 18 U.S.C. Section 1905.
# //
# Loading sv_std.std
# Loading work.rand_sv_unit(fast)
# Loading work.rand_var(fast)
# run -all
# rand - Randomizing the value of the variable in non cycling form
# Iterantion = 0 Random value of a = 0
# Iterantion = 1 Random value of a = 1
# Iterantion = 2 Random value of a = 1
# Iterantion = 3 Random value of a = 3
# Iterantion = 4 Random value of a = 4
# Iterantion = 5 Random value of a = 5
# Iterantion = 6 Random value of a = 5
# Iterantion = 7 Random value of a = 2
# Iterantion = 8 Random value of a = 1
# Iterantion = 9 Random value of a = 7
# Iterantion = 10 Random value of a = 2
# -----------------------------------------------------------------
# exit
# End time: 04:37:55 on Sep 16,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0