forked from hemanth-VP/SystemVerilog_Course
-
Notifications
You must be signed in to change notification settings - Fork 0
/
code.log
98 lines (98 loc) · 1.51 KB
/
code.log
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
# vsim top -l code.log -c -do "run -all;quit;"
# Start time: 18:50:36 on Sep 27,2022
# ** Note: (vsim-8009) Loading existing optimized design _opt
# // Questa Sim
# // Version 10.6c linux Jul 25 2017
# //
# // Copyright 1991-2017 Mentor Graphics Corporation
# // All Rights Reserved.
# //
# // QuestaSim and its associated documentation contain trade
# // secrets and commercial or financial information that are the property of
# // Mentor Graphics Corporation and are privileged, confidential,
# // and exempt from disclosure under the Freedom of Information Act,
# // 5 U.S.C. Section 552. Furthermore, this information
# // is prohibited from disclosure under the Trade Secrets Act,
# // 18 U.S.C. Section 1905.
# //
# Loading sv_std.std
# Loading work.top(fast)
# run -all
#
# // Parameterised interface example
#
# count=0
#
# count=1
#
# count=2
#
# count=3
#
# count=4
#
# count=5
#
# count=6
#
# count=7
#
# count=0
#
# count=1
#
# count=2
#
# count=3
#
# count=4
#
# count=5
#
# count=6
#
# count=7
#
# count=0
#
# count=1
#
# count=2
#
# count=3
#
# count=4
#
# count=5
#
# count=6
#
# count=7
#
# count=0
#
# count=1
#
# count=2
#
# count=3
#
# count=4
#
# count=5
#
# count=6
#
# count=7
#
# count=0
#
# count=1
#
# count=2
#
# count=3
# ** Note: $finish : /hwetools/work_area/frontend/dilip_B7/interface/interface/inter_face/parameter/test.sv(16)
# Time: 370 ns Iteration: 0 Instance: /top/u2
# End time: 18:50:37 on Sep 27,2022, Elapsed time: 0:00:01
# Errors: 0, Warnings: 0