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new_dynarec.c
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new_dynarec.c
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/* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
* Mupen64plus - new_dynarec.c *
* Copyright (C) 2009-2011 Ari64 *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program; if not, write to the *
* Free Software Foundation, Inc., *
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. *
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
#include <stdio.h>
#include <stdint.h>
#include <stdlib.h>
#include <string.h>
#include <assert.h>
#if defined(__APPLE__)
#include <sys/types.h> // needed for u_int, u_char, etc
#define MAP_ANONYMOUS MAP_ANON
#endif
#include "new_dynarec.h"
#include "api/m64p_types.h"
#include "api/callbacks.h"
#include "main/main.h"
#include "main/rom.h"
#include "device/memory/memory.h"
#include "device/r4300/cached_interp.h"
#include "device/r4300/cp0.h"
#include "device/r4300/cp1.h"
#include "device/r4300/interrupt.h"
#include "device/r4300/tlb.h"
#include "device/r4300/fpu.h"
#include "device/rcp/mi/mi_controller.h"
#include "device/rcp/rsp/rsp_core.h"
#if !defined(WIN32)
#include <sys/mman.h>
#endif
#if defined(RECOMPILER_DEBUG) && !defined(RECOMP_DBG)
void recomp_dbg_init(void);
void recomp_dbg_cleanup(void);
void recomp_dbg_block(int addr);
#endif
#if NEW_DYNAREC == NEW_DYNAREC_X86
#include "x86/assem_x86.h"
#elif NEW_DYNAREC == NEW_DYNAREC_X64
#include "x64/assem_x64.h"
#elif NEW_DYNAREC == NEW_DYNAREC_ARM
#include "arm/arm_cpu_features.h"
#include "arm/assem_arm.h"
#elif NEW_DYNAREC == NEW_DYNAREC_ARM64
#include "arm64/assem_arm64.h"
#else
#error Unsupported dynarec architecture
#endif
/* debug */
#define ASSEM_DEBUG 0
#define INV_DEBUG 0
#define COUNT_NOTCOMPILEDS 0
//#define INTERPRET_LOAD
//#define INTERPRET_STORE
//#define INTERPRET_C1LS
//#define INTERPRET_LOADLR
//#define INTERPRET_STORELR
//#define INTERPRET_MULT
//#define INTERPRET_DIV
//#define INTERPRET_MULT64
//#define INTERPRET_DIV64
//#define INTERPRET_FCONV
//#define INTERPRET_FLOAT
//#define INTERPRET_FCOMP
#if ASSEM_DEBUG
#define assem_debug(...) DebugMessage(M64MSG_VERBOSE, __VA_ARGS__)
#else
#define assem_debug(...)
#endif
#if INV_DEBUG
#define inv_debug(...) DebugMessage(M64MSG_VERBOSE, __VA_ARGS__)
#else
#define inv_debug(...)
#endif
#ifdef NDEBUG
#define assem_strcpy(...)
#else
#define assem_strcpy strcpy
#endif
/* registers that may be allocated */
/* 1-31 gpr */
#define HIREG 32 // hi
#define LOREG 33 // lo
#define FSREG 34 // FPU status (FCSR)
#define CSREG 35 // Coprocessor status
#define CCREG 36 // Cycle count
#define INVCP 37 // Pointer to invalid_code
#define MMREG 38 // Pointer to memory_map
#define ROREG 39 // ram offset (if rdram!=0x80000000)
#define TEMPREG 40
#define FTEMP 40 // FPU temporary register
#define PTEMP 41 // Prefetch temporary register
#define TLREG 42 // TLB mapping offset
#define RHASH 43 // Return address hash
#define RHTBL 44 // Return address hash table address
#define RTEMP 45 // JR/JALR address register
#define MAXREG 45
#define AGEN1 46 // Address generation temporary register
#define AGEN2 47 // Address generation temporary register
#define MGEN1 48 // Maptable address generation temporary register
#define MGEN2 49 // Maptable address generation temporary register
#define BTREG 50 // Branch target temporary register
/* instruction types */
#define NOP 0 // No operation
#define LOAD 1 // Load
#define STORE 2 // Store
#define LOADLR 3 // Unaligned load
#define STORELR 4 // Unaligned store
#define MOV 5 // Move
#define ALU 6 // Arithmetic/logic
#define MULTDIV 7 // Multiply/divide
#define SHIFT 8 // Shift by register
#define SHIFTIMM 9// Shift by immediate
#define IMM16 10 // 16-bit immediate
#define RJUMP 11 // Unconditional jump to register
#define UJUMP 12 // Unconditional jump
#define CJUMP 13 // Conditional branch (BEQ/BNE/BGTZ/BLEZ)
#define SJUMP 14 // Conditional branch (regimm format)
#define COP0 15 // Coprocessor 0
#define COP1 16 // Coprocessor 1
#define C1LS 17 // Coprocessor 1 load/store
#define FJUMP 18 // Conditional branch (floating point)
#define FLOAT 19 // Floating point unit
#define FCONV 20 // Convert integer to float
#define FCOMP 21 // Floating point compare (sets FSREG)
#define SYSCALL 22// SYSCALL
#define OTHER 23 // Other
#define SPAN 24 // Branch/delay slot spans 2 pages
#define NI 25 // Not implemented
/* stubs */
#define CC_STUB 1
#define FP_STUB 2
#define LOADB_STUB 3
#define LOADH_STUB 4
#define LOADW_STUB 5
#define LOADD_STUB 6
#define LOADBU_STUB 7
#define LOADHU_STUB 8
#define LOADWU_STUB 9
#define STOREB_STUB 10
#define STOREH_STUB 11
#define STOREW_STUB 12
#define STORED_STUB 13
#define LOADWR_STUB 14
#define LOADWL_STUB 15
#define LOADDR_STUB 16
#define LOADDL_STUB 17
#define STOREWL_STUB 18
#define STOREWR_STUB 19
#define STOREDL_STUB 20
#define STOREDR_STUB 21
#define INVCODE_STUB 22
/* branch codes */
#define TAKEN 1
#define NOTTAKEN 2
#define NULLDS 3
#define MAXBLOCK 4096
#define MAX_OUTPUT_BLOCK_SIZE 262144
#define CLOCK_DIVIDER g_dev.r4300.cp0.count_per_op
struct regstat
{
signed char regmap_entry[HOST_REGS];
signed char regmap[HOST_REGS];
uint64_t was32;
uint64_t is32;
uint64_t wasdirty;
uint64_t dirty;
uint64_t u;
uint64_t uu;
u_int wasconst;
u_int isconst;
uint64_t constmap[HOST_REGS];
};
struct ll_entry
{
void *addr;
void *clean_addr;
void *copy;
struct ll_entry *next;
u_int vaddr;
u_int reg32;
u_int start;
u_int length;
};
/* linkage */
void verify_code(void);
void cc_interrupt(void);
void do_interrupt(void);
void fp_exception(void);
void jump_syscall(void);
void jump_eret(void);
void dyna_linker(void);
void dyna_linker_ds(void);
void breakpoint(void);
int new_recompile_block(int addr);
void invalidate_block(u_int block);
void *get_addr_ht(u_int vaddr);
void *get_addr_32(u_int vaddr,u_int flags);
static void load_regs_entry(int t);
static void inline_readstub(int type,int i,u_int addr_const,char addr,struct regstat *i_regs,int target,int adj,u_int reglist);
void *base_addr;
void *base_addr_rx;
u_char *out;
unsigned int using_tlb;
unsigned int stop_after_jal;
static u_int start;
static u_int *source;
static u_int pagelimit;
static char insn[MAXBLOCK][10];
static u_char itype[MAXBLOCK];
static u_char opcode[MAXBLOCK];
static u_char opcode2[MAXBLOCK];
static u_char bt[MAXBLOCK];
static u_char rs1[MAXBLOCK];
static u_char rs2[MAXBLOCK];
static u_char rt1[MAXBLOCK];
static u_char rt2[MAXBLOCK];
static u_char us1[MAXBLOCK];
static u_char us2[MAXBLOCK];
static u_char dep1[MAXBLOCK];
static u_char dep2[MAXBLOCK];
static u_char lt1[MAXBLOCK];
static int imm[MAXBLOCK];
static u_int ba[MAXBLOCK];
static char likely[MAXBLOCK];
static char is_ds[MAXBLOCK];
static char ooo[MAXBLOCK];
static uint64_t unneeded_reg[MAXBLOCK];
static uint64_t unneeded_reg_upper[MAXBLOCK];
static uint64_t branch_unneeded_reg[MAXBLOCK];
static uint64_t branch_unneeded_reg_upper[MAXBLOCK];
static uint64_t p32[MAXBLOCK];
static uint64_t pr32[MAXBLOCK];
static signed char regmap_pre[MAXBLOCK][HOST_REGS];
static uint64_t constmap[MAXBLOCK][HOST_REGS];
static struct regstat regs[MAXBLOCK];
static struct regstat branch_regs[MAXBLOCK];
static signed char minimum_free_regs[MAXBLOCK];
static u_int needed_reg[MAXBLOCK];
static uint64_t requires_32bit[MAXBLOCK];
static u_int wont_dirty[MAXBLOCK];
static u_int will_dirty[MAXBLOCK];
static int ccadj[MAXBLOCK];
static int slen;
static uintptr_t instr_addr[MAXBLOCK];
static uintptr_t link_addr[MAXBLOCK][3];
static int linkcount;
static uintptr_t stubs[MAXBLOCK*3][8];
static int stubcount;
static int literalcount;
static int is_delayslot;
static int cop1_usable;
static char *copy;
static int expirep;
static u_int dirty_entry_count;
static u_int copy_size;
static struct ll_entry* hash_table[65536][2];
static struct ll_entry *jump_in[4096];
static struct ll_entry *jump_dirty[4096];
static struct ll_entry *jump_out[4096];
static unsigned char restore_candidate[512];
#if COUNT_NOTCOMPILEDS
static int notcompiledCount = 0;
#endif
#if ASSEM_DEBUG
static signed char regmap[MAXBLOCK][HOST_REGS];
static signed char regmap_entry[MAXBLOCK][HOST_REGS];
#endif
static void clear_all_regs(signed char regmap[])
{
int hr;
for (hr=0;hr<HOST_REGS;hr++) regmap[hr]=-1;
}
static signed char get_reg(signed char regmap[],int r)
{
int hr;
for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&®map[hr]==r) return hr;
return -1;
}
// Find a register that is available for two consecutive cycles
static signed char get_reg2(signed char regmap1[],signed char regmap2[],int r)
{
int hr;
for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&®map1[hr]==r&®map2[hr]==r) return hr;
return -1;
}
static int count_free_regs(signed char regmap[])
{
int count=0;
int hr;
for(hr=0;hr<HOST_REGS;hr++)
{
if(hr!=EXCLUDE_REG) {
if(regmap[hr]<0) count++;
}
}
return count;
}
static void dirty_reg(struct regstat *cur,signed char reg)
{
int hr;
if(!reg) return;
for (hr=0;hr<HOST_REGS;hr++) {
if((cur->regmap[hr]&63)==reg) {
cur->dirty|=1LL<<hr;
}
}
}
// If we dirty the lower half of a 64 bit register which is now being
// sign-extended, we need to dump the upper half.
// Note: Do this only after completion of the instruction, because
// some instructions may need to read the full 64-bit value even if
// overwriting it (eg SLTI, DSRA32).
static void flush_dirty_uppers(struct regstat *cur)
{
int hr,reg;
for (hr=0;hr<HOST_REGS;hr++) {
if((cur->dirty>>hr)&1) {
reg=cur->regmap[hr];
if(reg>=64)
if((cur->is32>>(reg&63))&1) cur->regmap[hr]=-1;
}
}
}
static void set_const(struct regstat *cur,signed char reg,uint64_t value)
{
int hr;
if(!reg) return;
for (hr=0;hr<HOST_REGS;hr++) {
if(cur->regmap[hr]==reg) {
cur->isconst|=1<<hr;
cur->constmap[hr]=value;
}
else if((cur->regmap[hr]^64)==reg) {
cur->isconst|=1<<hr;
cur->constmap[hr]=value>>32;
}
}
}
static void clear_const(struct regstat *cur,signed char reg)
{
int hr;
if(!reg) return;
for (hr=0;hr<HOST_REGS;hr++) {
if((cur->regmap[hr]&63)==reg) {
cur->isconst&=~(1<<hr);
}
}
}
static int is_const(struct regstat *cur,signed char reg)
{
int hr;
if(reg<0) return 0;
if(!reg) return 1;
for (hr=0;hr<HOST_REGS;hr++) {
if((cur->regmap[hr]&63)==reg) {
return (cur->isconst>>hr)&1;
}
}
return 0;
}
static uint64_t get_const(struct regstat *cur,signed char reg)
{
int hr;
if(!reg) return 0;
for (hr=0;hr<HOST_REGS;hr++) {
if(cur->regmap[hr]==reg) {
return cur->constmap[hr];
}
}
DebugMessage(M64MSG_ERROR, "Unknown constant in r%d",reg);
exit(1);
}
// Least soon needed registers
// Look at the next ten instructions and see which registers
// will be used. Try not to reallocate these.
static void lsn(u_char hsn[], int i, int *preferred_reg)
{
int j;
int b=-1;
for(j=0;j<9;j++)
{
if(i+j>=slen) {
j=slen-i-1;
break;
}
if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
{
// Don't go past an unconditional jump
j++;
break;
}
}
for(;j>=0;j--)
{
if(rs1[i+j]) hsn[rs1[i+j]]=j;
if(rs2[i+j]) hsn[rs2[i+j]]=j;
if(rt1[i+j]) hsn[rt1[i+j]]=j;
if(rt2[i+j]) hsn[rt2[i+j]]=j;
if(itype[i+j]==STORE || itype[i+j]==STORELR) {
// Stores can allocate zero
hsn[rs1[i+j]]=j;
hsn[rs2[i+j]]=j;
}
// On some architectures stores need invc_ptr
#if defined(HOST_IMM8) || defined(NEED_INVC_PTR)
if(itype[i+j]==STORE || itype[i+j]==STORELR || (opcode[i+j]&0x3b)==0x39) {
hsn[INVCP]=j;
}
#endif
if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP))
{
hsn[CCREG]=j;
b=j;
}
}
if(b>=0)
{
if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
{
// Follow first branch
int t=(ba[i+b]-start)>>2;
j=7-b;if(t+j>=slen) j=slen-t-1;
for(;j>=0;j--)
{
if(rs1[t+j]) if(hsn[rs1[t+j]]>j+b+2) hsn[rs1[t+j]]=j+b+2;
if(rs2[t+j]) if(hsn[rs2[t+j]]>j+b+2) hsn[rs2[t+j]]=j+b+2;
//if(rt1[t+j]) if(hsn[rt1[t+j]]>j+b+2) hsn[rt1[t+j]]=j+b+2;
//if(rt2[t+j]) if(hsn[rt2[t+j]]>j+b+2) hsn[rt2[t+j]]=j+b+2;
}
}
// TODO: preferred register based on backward branch
}
// Delay slot should preferably not overwrite branch conditions or cycle count
if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)) {
if(rs1[i-1]) if(hsn[rs1[i-1]]>1) hsn[rs1[i-1]]=1;
if(rs2[i-1]) if(hsn[rs2[i-1]]>1) hsn[rs2[i-1]]=1;
hsn[CCREG]=1;
// ...or hash tables
hsn[RHASH]=1;
hsn[RHTBL]=1;
}
// Coprocessor load/store needs FTEMP, even if not declared
if(itype[i]==C1LS) {
hsn[FTEMP]=0;
}
// Load L/R also uses FTEMP as a temporary register
if(itype[i]==LOADLR) {
hsn[FTEMP]=0;
}
// Also 64-bit SDL/SDR
if(opcode[i]==0x2c||opcode[i]==0x2d) {
hsn[FTEMP]=0;
}
// Don't remove the TLB registers either
if(itype[i]==LOAD || itype[i]==LOADLR || itype[i]==STORE || itype[i]==STORELR || itype[i]==C1LS ) {
hsn[TLREG]=0;
}
// Don't remove the miniht registers
if(itype[i]==UJUMP||itype[i]==RJUMP)
{
hsn[RHASH]=0;
hsn[RHTBL]=0;
}
}
// We only want to allocate registers if we're going to use them again soon
static int needed_again(int r, int i)
{
int j;
/*int b=-1;*/
int rn=10;
if(i>0&&(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000))
{
if(ba[i-1]<start || ba[i-1]>start+slen*4-4)
return 0; // Don't need any registers if exiting the block
}
for(j=0;j<9;j++)
{
if(i+j>=slen) {
j=slen-i-1;
break;
}
if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
{
// Don't go past an unconditional jump
j++;
break;
}
if(itype[i+j]==SYSCALL||((source[i+j]&0xfc00003f)==0x0d))
{
break;
}
}
for(;j>=1;j--)
{
if(rs1[i+j]==r) rn=j;
if(rs2[i+j]==r) rn=j;
if((unneeded_reg[i+j]>>r)&1) rn=10;
if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP))
{
/*b=j;*/
}
}
/*
if(b>=0)
{
if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
{
// Follow first branch
int o=rn;
int t=(ba[i+b]-start)>>2;
j=7-b;if(t+j>=slen) j=slen-t-1;
for(;j>=0;j--)
{
if(!((unneeded_reg[t+j]>>r)&1)) {
if(rs1[t+j]==r) if(rn>j+b+2) rn=j+b+2;
if(rs2[t+j]==r) if(rn>j+b+2) rn=j+b+2;
}
else rn=o;
}
}
}*/
if(rn<10) return 1;
return 0;
}
// Try to match register allocations at the end of a loop with those
// at the beginning
static int loop_reg(int i, int r, int hr)
{
int j,k;
for(j=0;j<9;j++)
{
if(i+j>=slen) {
j=slen-i-1;
break;
}
if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
{
// Don't go past an unconditional jump
j++;
break;
}
}
k=0;
if(i>0){
if(itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)
k--;
}
for(;k<j;k++)
{
if(r<64&&((unneeded_reg[i+k]>>r)&1)) return hr;
if(r>64&&((unneeded_reg_upper[i+k]>>r)&1)) return hr;
if(i+k>=0&&(itype[i+k]==UJUMP||itype[i+k]==CJUMP||itype[i+k]==SJUMP||itype[i+k]==FJUMP))
{
if(ba[i+k]>=start && ba[i+k]<(start+i*4))
{
int t=(ba[i+k]-start)>>2;
int reg=get_reg(regs[t].regmap_entry,r);
if(reg>=0) return reg;
//reg=get_reg(regs[t+1].regmap_entry,r);
//if(reg>=0) return reg;
}
}
}
return hr;
}
// Basic liveness analysis for MIPS registers
static void unneeded_registers(int istart,int iend,int r)
{
int i;
uint64_t u,uu,b,bu;
uint64_t temp_u,temp_uu;
uint64_t tdep;
if(iend==slen-1) {
u=1;uu=1;
}else{
u=unneeded_reg[iend+1];
uu=unneeded_reg_upper[iend+1];
u=1;uu=1;
}
for (i=iend;i>=istart;i--)
{
//DebugMessage(M64MSG_VERBOSE, "unneeded registers i=%d (%d,%d) r=%d",i,istart,iend,r);
if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
{
// If subroutine call, flag return address as a possible branch target
if(rt1[i]==31 && i<slen-2) bt[i+2]=1;
if(ba[i]<start || ba[i]>=(start+slen*4))
{
// Branch out of this block, flush all regs
u=1;
uu=1;
/* Hexagon hack
if(itype[i]==UJUMP&&rt1[i]==31)
{
uu=u=0x300C00F; // Discard at, v0-v1, t6-t9
}
if(itype[i]==RJUMP&&rs1[i]==31)
{
uu=u=0x300C0F3; // Discard at, a0-a3, t6-t9
}
if(start>0x80000400&&start<0x80800000) {
if(itype[i]==UJUMP&&rt1[i]==31)
{
//uu=u=0x30300FF0FLL; // Discard at, v0-v1, t0-t9, lo, hi
uu=u=0x300FF0F; // Discard at, v0-v1, t0-t9
}
if(itype[i]==RJUMP&&rs1[i]==31)
{
//uu=u=0x30300FFF3LL; // Discard at, a0-a3, t0-t9, lo, hi
uu=u=0x300FFF3; // Discard at, a0-a3, t0-t9
}
}*/
branch_unneeded_reg[i]=u;
branch_unneeded_reg_upper[i]=uu;
// Merge in delay slot
tdep=(~uu>>rt1[i+1])&1;
u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
uu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
u|=1;uu|=1;
// If branch is "likely" (and conditional)
// then we skip the delay slot on the fall-thru path
if(likely[i]) {
if(i<slen-1) {
u&=unneeded_reg[i+2];
uu&=unneeded_reg_upper[i+2];
}
else
{
u=1;
uu=1;
}
}
}
else
{
// Internal branch, flag target
bt[(ba[i]-start)>>2]=1;
if(ba[i]<=start+i*4) {
// Backward branch
if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
{
// Unconditional branch
temp_u=1;temp_uu=1;
} else {
// Conditional branch (not taken case)
temp_u=unneeded_reg[i+2];
temp_uu=unneeded_reg_upper[i+2];
}
// Merge in delay slot
tdep=(~temp_uu>>rt1[i+1])&1;
temp_u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
temp_uu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
temp_u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
temp_uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
temp_uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
temp_u|=1;temp_uu|=1;
// If branch is "likely" (and conditional)
// then we skip the delay slot on the fall-thru path
if(likely[i]) {
if(i<slen-1) {
temp_u&=unneeded_reg[i+2];
temp_uu&=unneeded_reg_upper[i+2];
}
else
{
temp_u=1;
temp_uu=1;
}
}
tdep=(~temp_uu>>rt1[i])&1;
temp_u|=(1LL<<rt1[i])|(1LL<<rt2[i]);
temp_uu|=(1LL<<rt1[i])|(1LL<<rt2[i]);
temp_u&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
temp_uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
temp_uu&=~((tdep<<dep1[i])|(tdep<<dep2[i]));
temp_u|=1;temp_uu|=1;
unneeded_reg[i]=temp_u;
unneeded_reg_upper[i]=temp_uu;
// Only go three levels deep. This recursion can take an
// excessive amount of time if there are a lot of nested loops.
if(r<2) {
unneeded_registers((ba[i]-start)>>2,i-1,r+1);
}else{
unneeded_reg[(ba[i]-start)>>2]=1;
unneeded_reg_upper[(ba[i]-start)>>2]=1;
}
} /*else*/ if(1) {
if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
{
// Unconditional branch
u=unneeded_reg[(ba[i]-start)>>2];
uu=unneeded_reg_upper[(ba[i]-start)>>2];
branch_unneeded_reg[i]=u;
branch_unneeded_reg_upper[i]=uu;
//u=1;
//uu=1;
//branch_unneeded_reg[i]=u;
//branch_unneeded_reg_upper[i]=uu;
// Merge in delay slot
tdep=(~uu>>rt1[i+1])&1;
u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
uu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
u|=1;uu|=1;
} else {
// Conditional branch
b=unneeded_reg[(ba[i]-start)>>2];
bu=unneeded_reg_upper[(ba[i]-start)>>2];
branch_unneeded_reg[i]=b;
branch_unneeded_reg_upper[i]=bu;
//b=1;
//bu=1;
//branch_unneeded_reg[i]=b;
//branch_unneeded_reg_upper[i]=bu;
// Branch delay slot
tdep=(~uu>>rt1[i+1])&1;
b|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
bu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
b&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
bu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
bu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
b|=1;bu|=1;
// If branch is "likely" then we skip the
// delay slot on the fall-thru path
if(likely[i]) {
u=b;
uu=bu;
if(i<slen-1) {
u&=unneeded_reg[i+2];
uu&=unneeded_reg_upper[i+2];
//u=1;
//uu=1;
}
} else {
u&=b;
uu&=bu;
//u=1;
//uu=1;
}
if(i<slen-1) {
branch_unneeded_reg[i]&=unneeded_reg[i+2];
branch_unneeded_reg_upper[i]&=unneeded_reg_upper[i+2];
//branch_unneeded_reg[i]=1;
//branch_unneeded_reg_upper[i]=1;
} else {
branch_unneeded_reg[i]=1;
branch_unneeded_reg_upper[i]=1;
}
}
}
}
}
else if(itype[i]==SYSCALL)
{
// SYSCALL instruction (software interrupt)
u=1;
uu=1;
}
else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
{
// ERET instruction (return from interrupt)
u=1;
uu=1;
}
//u=uu=1; // DEBUG
tdep=(~uu>>rt1[i])&1;
// Written registers are unneeded
u|=1LL<<rt1[i];
u|=1LL<<rt2[i];
uu|=1LL<<rt1[i];
uu|=1LL<<rt2[i];
// Accessed registers are needed
u&=~(1LL<<rs1[i]);
u&=~(1LL<<rs2[i]);
uu&=~(1LL<<us1[i]);
uu&=~(1LL<<us2[i]);
// Source-target dependencies
uu&=~(tdep<<dep1[i]);
uu&=~(tdep<<dep2[i]);
// R0 is always unneeded
u|=1;uu|=1;
// Save it
unneeded_reg[i]=u;
unneeded_reg_upper[i]=uu;
/*
DebugMessage(M64MSG_VERBOSE, "ur (%d,%d) %x: ",istart,iend,start+i*4);
DebugMessage(M64MSG_VERBOSE, "U:");
int r;
for(r=1;r<=CCREG;r++) {
if((unneeded_reg[i]>>r)&1) {
if(r==HIREG) DebugMessage(M64MSG_VERBOSE, " HI");
else if(r==LOREG) DebugMessage(M64MSG_VERBOSE, " LO");
else DebugMessage(M64MSG_VERBOSE, " r%d",r);
}
}
DebugMessage(M64MSG_VERBOSE, " UU:");
for(r=1;r<=CCREG;r++) {
if(((unneeded_reg_upper[i]&~unneeded_reg[i])>>r)&1) {
if(r==HIREG) DebugMessage(M64MSG_VERBOSE, " HI");
else if(r==LOREG) DebugMessage(M64MSG_VERBOSE, " LO");
else DebugMessage(M64MSG_VERBOSE, " r%d",r);
}
}*/
}
}
// Identify registers which are likely to contain 32-bit values
// This is used to predict whether any branches will jump to a
// location with 64-bit values in registers.
static void provisional_32bit(void)
{
int i,j;
uint64_t is32=1;
uint64_t lastbranch=1;
for(i=0;i<slen;i++)
{
if(i>0) {
if(itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP) {
if(i>1) is32=lastbranch;
else is32=1;
}
}
if(i>1)
{
if(itype[i-2]==CJUMP||itype[i-2]==SJUMP||itype[i-2]==FJUMP) {
if(likely[i-2]) {
if(i>2) is32=lastbranch;
else is32=1;
}
}
if((opcode[i-2]&0x2f)==0x05) // BNE/BNEL
{
if(rs1[i-2]==0||rs2[i-2]==0)
{
if(rs1[i-2]) {
is32|=1LL<<rs1[i-2];
}
if(rs2[i-2]) {
is32|=1LL<<rs2[i-2];
}
}
}
}
// If something jumps here with 64-bit values
// then promote those registers to 64 bits
if(bt[i])
{
uint64_t temp_is32=is32;
for(j=i-1;j>=0;j--)
{
if(ba[j]==start+i*4)
//temp_is32&=branch_regs[j].is32;
temp_is32&=p32[j];
}
for(j=i;j<slen;j++)
{
if(ba[j]==start+i*4)
temp_is32=1;
}
is32=temp_is32;
}
int type=itype[i];
int op=opcode[i];
int op2=opcode2[i];
int rt=rt1[i];
int s1=rs1[i];
int s2=rs2[i];
if(type==UJUMP||type==RJUMP||type==CJUMP||type==SJUMP||type==FJUMP) {
// Branches don't write registers, consider the delay slot instead.
type=itype[i+1];
op=opcode[i+1];
op2=opcode2[i+1];
rt=rt1[i+1];
s1=rs1[i+1];
s2=rs2[i+1];
lastbranch=is32;
}
switch(type) {
case LOAD:
if(opcode[i]==0x27||opcode[i]==0x37|| // LWU/LD
opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
is32&=~(1LL<<rt);
else
is32|=1LL<<rt;
break;
case STORE:
case STORELR:
break;
case LOADLR:
if(op==0x1a||op==0x1b) is32&=~(1LL<<rt); // LDR/LDL
if(op==0x22) is32|=1LL<<rt; // LWL
break;
case IMM16:
if (op==0x08||op==0x09|| // ADDI/ADDIU
op==0x0a||op==0x0b|| // SLTI/SLTIU
op==0x0c|| // ANDI
op==0x0f) // LUI
{
is32|=1LL<<rt;
}
if(op==0x18||op==0x19) { // DADDI/DADDIU
is32&=~(1LL<<rt);
//if(imm[i]==0)
// is32|=((is32>>s1)&1LL)<<rt;
}
if(op==0x0d||op==0x0e) { // ORI/XORI
uint64_t sr=((is32>>s1)&1LL);
is32&=~(1LL<<rt);
is32|=sr<<rt;
}
break;
case UJUMP:
break;
case RJUMP:
break;
case CJUMP:
break;
case SJUMP:
break;
case FJUMP:
break;
case ALU:
if(op2>=0x20&&op2<=0x23) { // ADD/ADDU/SUB/SUBU
is32|=1LL<<rt;
}
if(op2==0x2a||op2==0x2b) { // SLT/SLTU
is32|=1LL<<rt;
}
else if(op2>=0x24&&op2<=0x27) { // AND/OR/XOR/NOR
uint64_t sr=((is32>>s1)&(is32>>s2)&1LL);
is32&=~(1LL<<rt);
is32|=sr<<rt;
}
else if(op2>=0x2c&&op2<=0x2d) { // DADD/DADDU
if(s1==0&&s2==0) {
is32|=1LL<<rt;
}
else if(s2==0) {
uint64_t sr=((is32>>s1)&1LL);
is32&=~(1LL<<rt);