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000-mtk-14-drivers-mtd-add-support-for-MediaTek-SPI-NAND-flash-.patch
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000-mtk-14-drivers-mtd-add-support-for-MediaTek-SPI-NAND-flash-.patch
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From d6c5309185aae3d9ecf80eae8b248522d11a6136 Mon Sep 17 00:00:00 2001
From: Weijie Gao <weijie.gao@mediatek.com>
Date: Tue, 2 Mar 2021 16:58:01 +0800
Subject: [PATCH 04/12] drivers: mtd: add support for MediaTek SPI-NAND flash
controller
Add mtd driver for MediaTek SPI-NAND flash controller
This driver is written from scratch, and uses standard mtd framework, not
the nand framework which only applies for raw parallel nand flashes so that
this driver can have a smaller size in binary.
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
---
drivers/mtd/Kconfig | 2 +
drivers/mtd/Makefile | 2 +
drivers/mtd/mtk-snand/Kconfig | 21 +
drivers/mtd/mtk-snand/Makefile | 11 +
drivers/mtd/mtk-snand/mtk-snand-def.h | 266 ++++
drivers/mtd/mtk-snand/mtk-snand-ecc.c | 264 ++++
drivers/mtd/mtk-snand/mtk-snand-ids.c | 511 +++++++
drivers/mtd/mtk-snand/mtk-snand-mtd.c | 526 ++++++++
drivers/mtd/mtk-snand/mtk-snand-os.c | 39 +
drivers/mtd/mtk-snand/mtk-snand-os.h | 120 ++
drivers/mtd/mtk-snand/mtk-snand.c | 1776 +++++++++++++++++++++++++
drivers/mtd/mtk-snand/mtk-snand.h | 77 ++
12 files changed, 3615 insertions(+)
create mode 100644 drivers/mtd/mtk-snand/Kconfig
create mode 100644 drivers/mtd/mtk-snand/Makefile
create mode 100644 drivers/mtd/mtk-snand/mtk-snand-def.h
create mode 100644 drivers/mtd/mtk-snand/mtk-snand-ecc.c
create mode 100644 drivers/mtd/mtk-snand/mtk-snand-ids.c
create mode 100644 drivers/mtd/mtk-snand/mtk-snand-mtd.c
create mode 100644 drivers/mtd/mtk-snand/mtk-snand-os.c
create mode 100644 drivers/mtd/mtk-snand/mtk-snand-os.h
create mode 100644 drivers/mtd/mtk-snand/mtk-snand.c
create mode 100644 drivers/mtd/mtk-snand/mtk-snand.h
--- a/drivers/mtd/Kconfig
+++ b/drivers/mtd/Kconfig
@@ -116,6 +116,8 @@ config STM32_FLASH
This is the driver of embedded flash for some STMicroelectronics
STM32 MCU.
+source "drivers/mtd/mtk-snand/Kconfig"
+
source "drivers/mtd/nand/Kconfig"
config SYS_NAND_MAX_CHIPS
--- a/drivers/mtd/Makefile
+++ b/drivers/mtd/Makefile
@@ -39,3 +39,5 @@ obj-$(CONFIG_$(SPL_TPL_)SPI_FLASH_SUPPOR
obj-$(CONFIG_SPL_UBI) += ubispl/
endif
+
+obj-$(CONFIG_MTK_SPI_NAND) += mtk-snand/
--- /dev/null
+++ b/drivers/mtd/mtk-snand/Kconfig
@@ -0,0 +1,21 @@
+#
+# Copyright (C) 2020 MediaTek Inc. All rights reserved.
+# Author: Weijie Gao <weijie.gao@mediatek.com>
+#
+# SPDX-License-Identifier: GPL-2.0
+#
+
+config MTK_SPI_NAND
+ tristate "MediaTek SPI NAND flash controller driver"
+ depends on !MTD_SPI_NAND
+ help
+ This option enables access to SPI-NAND flashes through the
+ MediaTek SPI NAND Flash Controller
+
+config MTK_SPI_NAND_MTD
+ tristate "MTD support for MediaTek SPI NAND flash controller"
+ depends on DM_MTD
+ depends on MTK_SPI_NAND
+ help
+ This option enables access to SPI-NAND flashes through the
+ MTD interface of MediaTek SPI NAND Flash Controller
--- /dev/null
+++ b/drivers/mtd/mtk-snand/Makefile
@@ -0,0 +1,11 @@
+#
+# Copyright (C) 2020 MediaTek Inc. All rights reserved.
+# Author: Weijie Gao <weijie.gao@mediatek.com>
+#
+# SPDX-License-Identifier: GPL-2.0
+#
+
+obj-y += mtk-snand.o mtk-snand-ecc.o mtk-snand-ids.o mtk-snand-os.o
+obj-$(CONFIG_MTK_SPI_NAND_MTD) += mtk-snand-mtd.o
+
+ccflags-y += -DPRIVATE_MTK_SNAND_HEADER
--- /dev/null
+++ b/drivers/mtd/mtk-snand/mtk-snand-def.h
@@ -0,0 +1,266 @@
+/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
+/*
+ * Copyright (C) 2020 MediaTek Inc. All Rights Reserved.
+ *
+ * Author: Weijie Gao <weijie.gao@mediatek.com>
+ */
+
+#ifndef _MTK_SNAND_DEF_H_
+#define _MTK_SNAND_DEF_H_
+
+#include "mtk-snand-os.h"
+
+#ifdef PRIVATE_MTK_SNAND_HEADER
+#include "mtk-snand.h"
+#else
+#include <mtk-snand.h>
+#endif
+
+struct mtk_snand_plat_dev;
+
+enum snand_flash_io {
+ SNAND_IO_1_1_1,
+ SNAND_IO_1_1_2,
+ SNAND_IO_1_2_2,
+ SNAND_IO_1_1_4,
+ SNAND_IO_1_4_4,
+
+ __SNAND_IO_MAX
+};
+
+#define SPI_IO_1_1_1 BIT(SNAND_IO_1_1_1)
+#define SPI_IO_1_1_2 BIT(SNAND_IO_1_1_2)
+#define SPI_IO_1_2_2 BIT(SNAND_IO_1_2_2)
+#define SPI_IO_1_1_4 BIT(SNAND_IO_1_1_4)
+#define SPI_IO_1_4_4 BIT(SNAND_IO_1_4_4)
+
+struct snand_opcode {
+ uint8_t opcode;
+ uint8_t dummy;
+};
+
+struct snand_io_cap {
+ uint8_t caps;
+ struct snand_opcode opcodes[__SNAND_IO_MAX];
+};
+
+#define SNAND_OP(_io, _opcode, _dummy) [_io] = { .opcode = (_opcode), \
+ .dummy = (_dummy) }
+
+#define SNAND_IO_CAP(_name, _caps, ...) \
+ struct snand_io_cap _name = { .caps = (_caps), \
+ .opcodes = { __VA_ARGS__ } }
+
+#define SNAND_MAX_ID_LEN 4
+
+enum snand_id_type {
+ SNAND_ID_DYMMY,
+ SNAND_ID_ADDR = SNAND_ID_DYMMY,
+ SNAND_ID_DIRECT,
+
+ __SNAND_ID_TYPE_MAX
+};
+
+struct snand_id {
+ uint8_t type; /* enum snand_id_type */
+ uint8_t len;
+ uint8_t id[SNAND_MAX_ID_LEN];
+};
+
+#define SNAND_ID(_type, ...) \
+ { .type = (_type), .id = { __VA_ARGS__ }, \
+ .len = sizeof((uint8_t[]) { __VA_ARGS__ }) }
+
+struct snand_mem_org {
+ uint16_t pagesize;
+ uint16_t sparesize;
+ uint16_t pages_per_block;
+ uint16_t blocks_per_die;
+ uint16_t planes_per_die;
+ uint16_t ndies;
+};
+
+#define SNAND_MEMORG(_ps, _ss, _ppb, _bpd, _ppd, _nd) \
+ { .pagesize = (_ps), .sparesize = (_ss), .pages_per_block = (_ppb), \
+ .blocks_per_die = (_bpd), .planes_per_die = (_ppd), .ndies = (_nd) }
+
+typedef int (*snand_select_die_t)(struct mtk_snand *snf, uint32_t dieidx);
+
+struct snand_flash_info {
+ const char *model;
+ struct snand_id id;
+ const struct snand_mem_org memorg;
+ const struct snand_io_cap *cap_rd;
+ const struct snand_io_cap *cap_pl;
+ snand_select_die_t select_die;
+};
+
+#define SNAND_INFO(_model, _id, _memorg, _cap_rd, _cap_pl, ...) \
+ { .model = (_model), .id = _id, .memorg = _memorg, \
+ .cap_rd = (_cap_rd), .cap_pl = (_cap_pl), __VA_ARGS__ }
+
+const struct snand_flash_info *snand_flash_id_lookup(enum snand_id_type type,
+ const uint8_t *id);
+
+struct mtk_snand_soc_data {
+ uint16_t sector_size;
+ uint16_t max_sectors;
+ uint16_t fdm_size;
+ uint16_t fdm_ecc_size;
+ uint16_t fifo_size;
+
+ bool bbm_swap;
+ bool empty_page_check;
+ uint32_t mastersta_mask;
+
+ const uint8_t *spare_sizes;
+ uint32_t num_spare_size;
+};
+
+enum mtk_ecc_regs {
+ ECC_DECDONE,
+};
+
+struct mtk_ecc_soc_data {
+ const uint8_t *ecc_caps;
+ uint32_t num_ecc_cap;
+ const uint32_t *regs;
+ uint16_t mode_shift;
+ uint8_t errnum_bits;
+ uint8_t errnum_shift;
+};
+
+struct mtk_snand {
+ struct mtk_snand_plat_dev *pdev;
+
+ void __iomem *nfi_base;
+ void __iomem *ecc_base;
+
+ enum mtk_snand_soc soc;
+ const struct mtk_snand_soc_data *nfi_soc;
+ const struct mtk_ecc_soc_data *ecc_soc;
+ bool snfi_quad_spi;
+ bool quad_spi_op;
+
+ const char *model;
+ uint64_t size;
+ uint64_t die_size;
+ uint32_t erasesize;
+ uint32_t writesize;
+ uint32_t oobsize;
+
+ uint32_t num_dies;
+ snand_select_die_t select_die;
+
+ uint8_t opcode_rfc;
+ uint8_t opcode_pl;
+ uint8_t dummy_rfc;
+ uint8_t mode_rfc;
+ uint8_t mode_pl;
+
+ uint32_t writesize_mask;
+ uint32_t writesize_shift;
+ uint32_t erasesize_mask;
+ uint32_t erasesize_shift;
+ uint64_t die_mask;
+ uint32_t die_shift;
+
+ uint32_t spare_per_sector;
+ uint32_t raw_sector_size;
+ uint32_t ecc_strength;
+ uint32_t ecc_steps;
+ uint32_t ecc_bytes;
+ uint32_t ecc_parity_bits;
+
+ uint8_t *page_cache; /* Used by read/write page */
+ uint8_t *buf_cache; /* Used by block bad/markbad & auto_oob */
+};
+
+enum mtk_snand_log_category {
+ SNAND_LOG_NFI,
+ SNAND_LOG_SNFI,
+ SNAND_LOG_ECC,
+ SNAND_LOG_CHIP,
+
+ __SNAND_LOG_CAT_MAX
+};
+
+int mtk_ecc_setup(struct mtk_snand *snf, void *fmdaddr, uint32_t max_ecc_bytes,
+ uint32_t msg_size);
+int mtk_snand_ecc_encoder_start(struct mtk_snand *snf);
+void mtk_snand_ecc_encoder_stop(struct mtk_snand *snf);
+int mtk_snand_ecc_decoder_start(struct mtk_snand *snf);
+void mtk_snand_ecc_decoder_stop(struct mtk_snand *snf);
+int mtk_ecc_wait_decoder_done(struct mtk_snand *snf);
+int mtk_ecc_check_decode_error(struct mtk_snand *snf, uint32_t page);
+
+int mtk_snand_mac_io(struct mtk_snand *snf, const uint8_t *out, uint32_t outlen,
+ uint8_t *in, uint32_t inlen);
+int mtk_snand_set_feature(struct mtk_snand *snf, uint32_t addr, uint32_t val);
+
+int mtk_snand_log(struct mtk_snand_plat_dev *pdev,
+ enum mtk_snand_log_category cat, const char *fmt, ...);
+
+#define snand_log_nfi(pdev, fmt, ...) \
+ mtk_snand_log(pdev, SNAND_LOG_NFI, fmt, ##__VA_ARGS__)
+
+#define snand_log_snfi(pdev, fmt, ...) \
+ mtk_snand_log(pdev, SNAND_LOG_SNFI, fmt, ##__VA_ARGS__)
+
+#define snand_log_ecc(pdev, fmt, ...) \
+ mtk_snand_log(pdev, SNAND_LOG_ECC, fmt, ##__VA_ARGS__)
+
+#define snand_log_chip(pdev, fmt, ...) \
+ mtk_snand_log(pdev, SNAND_LOG_CHIP, fmt, ##__VA_ARGS__)
+
+/* ffs64 */
+static inline int mtk_snand_ffs64(uint64_t x)
+{
+ if (!x)
+ return 0;
+
+ if (!(x & 0xffffffff))
+ return ffs((uint32_t)(x >> 32)) + 32;
+
+ return ffs((uint32_t)(x & 0xffffffff));
+}
+
+/* NFI dummy commands */
+#define NFI_CMD_DUMMY_READ 0x00
+#define NFI_CMD_DUMMY_WRITE 0x80
+
+/* SPI-NAND opcodes */
+#define SNAND_CMD_RESET 0xff
+#define SNAND_CMD_BLOCK_ERASE 0xd8
+#define SNAND_CMD_READ_FROM_CACHE_QUAD 0xeb
+#define SNAND_CMD_WINBOND_SELECT_DIE 0xc2
+#define SNAND_CMD_READ_FROM_CACHE_DUAL 0xbb
+#define SNAND_CMD_READID 0x9f
+#define SNAND_CMD_READ_FROM_CACHE_X4 0x6b
+#define SNAND_CMD_READ_FROM_CACHE_X2 0x3b
+#define SNAND_CMD_PROGRAM_LOAD_X4 0x32
+#define SNAND_CMD_SET_FEATURE 0x1f
+#define SNAND_CMD_READ_TO_CACHE 0x13
+#define SNAND_CMD_PROGRAM_EXECUTE 0x10
+#define SNAND_CMD_GET_FEATURE 0x0f
+#define SNAND_CMD_READ_FROM_CACHE 0x0b
+#define SNAND_CMD_WRITE_ENABLE 0x06
+#define SNAND_CMD_PROGRAM_LOAD 0x02
+
+/* SPI-NAND feature addresses */
+#define SNAND_FEATURE_MICRON_DIE_ADDR 0xd0
+#define SNAND_MICRON_DIE_SEL_1 BIT(6)
+
+#define SNAND_FEATURE_STATUS_ADDR 0xc0
+#define SNAND_STATUS_OIP BIT(0)
+#define SNAND_STATUS_WEL BIT(1)
+#define SNAND_STATUS_ERASE_FAIL BIT(2)
+#define SNAND_STATUS_PROGRAM_FAIL BIT(3)
+
+#define SNAND_FEATURE_CONFIG_ADDR 0xb0
+#define SNAND_FEATURE_QUAD_ENABLE BIT(0)
+#define SNAND_FEATURE_ECC_EN BIT(4)
+
+#define SNAND_FEATURE_PROTECT_ADDR 0xa0
+
+#endif /* _MTK_SNAND_DEF_H_ */
--- /dev/null
+++ b/drivers/mtd/mtk-snand/mtk-snand-ecc.c
@@ -0,0 +1,264 @@
+// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
+/*
+ * Copyright (C) 2020 MediaTek Inc. All Rights Reserved.
+ *
+ * Author: Weijie Gao <weijie.gao@mediatek.com>
+ */
+
+#include "mtk-snand-def.h"
+
+/* ECC registers */
+#define ECC_ENCCON 0x000
+#define ENC_EN BIT(0)
+
+#define ECC_ENCCNFG 0x004
+#define ENC_MS_S 16
+#define ENC_BURST_EN BIT(8)
+#define ENC_TNUM_S 0
+
+#define ECC_ENCIDLE 0x00c
+#define ENC_IDLE BIT(0)
+
+#define ECC_DECCON 0x100
+#define DEC_EN BIT(0)
+
+#define ECC_DECCNFG 0x104
+#define DEC_EMPTY_EN BIT(31)
+#define DEC_CS_S 16
+#define DEC_CON_S 12
+#define DEC_CON_CORRECT 3
+#define DEC_BURST_EN BIT(8)
+#define DEC_TNUM_S 0
+
+#define ECC_DECIDLE 0x10c
+#define DEC_IDLE BIT(0)
+
+#define ECC_DECENUM0 0x114
+#define ECC_DECENUM(n) (ECC_DECENUM0 + (n) * 4)
+
+/* ECC_ENCIDLE & ECC_DECIDLE */
+#define ECC_IDLE BIT(0)
+
+/* ENC_MODE & DEC_MODE */
+#define ECC_MODE_NFI 1
+
+#define ECC_TIMEOUT 500000
+
+static const uint8_t mt7622_ecc_caps[] = { 4, 6, 8, 10, 12 };
+
+static const uint8_t mt7986_ecc_caps[] = {
+ 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24
+};
+
+static const uint32_t mt7622_ecc_regs[] = {
+ [ECC_DECDONE] = 0x11c,
+};
+
+static const uint32_t mt7986_ecc_regs[] = {
+ [ECC_DECDONE] = 0x124,
+};
+
+static const struct mtk_ecc_soc_data mtk_ecc_socs[__SNAND_SOC_MAX] = {
+ [SNAND_SOC_MT7622] = {
+ .ecc_caps = mt7622_ecc_caps,
+ .num_ecc_cap = ARRAY_SIZE(mt7622_ecc_caps),
+ .regs = mt7622_ecc_regs,
+ .mode_shift = 4,
+ .errnum_bits = 5,
+ .errnum_shift = 5,
+ },
+ [SNAND_SOC_MT7629] = {
+ .ecc_caps = mt7622_ecc_caps,
+ .num_ecc_cap = ARRAY_SIZE(mt7622_ecc_caps),
+ .regs = mt7622_ecc_regs,
+ .mode_shift = 4,
+ .errnum_bits = 5,
+ .errnum_shift = 5,
+ },
+ [SNAND_SOC_MT7986] = {
+ .ecc_caps = mt7986_ecc_caps,
+ .num_ecc_cap = ARRAY_SIZE(mt7986_ecc_caps),
+ .regs = mt7986_ecc_regs,
+ .mode_shift = 5,
+ .errnum_bits = 5,
+ .errnum_shift = 8,
+ },
+};
+
+static inline uint32_t ecc_read32(struct mtk_snand *snf, uint32_t reg)
+{
+ return readl(snf->ecc_base + reg);
+}
+
+static inline void ecc_write32(struct mtk_snand *snf, uint32_t reg,
+ uint32_t val)
+{
+ writel(val, snf->ecc_base + reg);
+}
+
+static inline void ecc_write16(struct mtk_snand *snf, uint32_t reg,
+ uint16_t val)
+{
+ writew(val, snf->ecc_base + reg);
+}
+
+static int mtk_ecc_poll(struct mtk_snand *snf, uint32_t reg, uint32_t bits)
+{
+ uint32_t val;
+
+ return read16_poll_timeout(snf->ecc_base + reg, val, (val & bits), 0,
+ ECC_TIMEOUT);
+}
+
+static int mtk_ecc_wait_idle(struct mtk_snand *snf, uint32_t reg)
+{
+ int ret;
+
+ ret = mtk_ecc_poll(snf, reg, ECC_IDLE);
+ if (ret) {
+ snand_log_ecc(snf->pdev, "ECC engine is busy\n");
+ return -EBUSY;
+ }
+
+ return 0;
+}
+
+int mtk_ecc_setup(struct mtk_snand *snf, void *fmdaddr, uint32_t max_ecc_bytes,
+ uint32_t msg_size)
+{
+ uint32_t i, val, ecc_msg_bits, ecc_strength;
+ int ret;
+
+ snf->ecc_soc = &mtk_ecc_socs[snf->soc];
+
+ snf->ecc_parity_bits = fls(1 + 8 * msg_size);
+ ecc_strength = max_ecc_bytes * 8 / snf->ecc_parity_bits;
+
+ for (i = snf->ecc_soc->num_ecc_cap - 1; i >= 0; i--) {
+ if (snf->ecc_soc->ecc_caps[i] <= ecc_strength)
+ break;
+ }
+
+ if (unlikely(i < 0)) {
+ snand_log_ecc(snf->pdev, "Page size %u+%u is not supported\n",
+ snf->writesize, snf->oobsize);
+ return -ENOTSUPP;
+ }
+
+ snf->ecc_strength = snf->ecc_soc->ecc_caps[i];
+ snf->ecc_bytes = DIV_ROUND_UP(snf->ecc_strength * snf->ecc_parity_bits,
+ 8);
+
+ /* Encoder config */
+ ecc_write16(snf, ECC_ENCCON, 0);
+ ret = mtk_ecc_wait_idle(snf, ECC_ENCIDLE);
+ if (ret)
+ return ret;
+
+ ecc_msg_bits = msg_size * 8;
+ val = (ecc_msg_bits << ENC_MS_S) |
+ (ECC_MODE_NFI << snf->ecc_soc->mode_shift) | i;
+ ecc_write32(snf, ECC_ENCCNFG, val);
+
+ /* Decoder config */
+ ecc_write16(snf, ECC_DECCON, 0);
+ ret = mtk_ecc_wait_idle(snf, ECC_DECIDLE);
+ if (ret)
+ return ret;
+
+ ecc_msg_bits += snf->ecc_strength * snf->ecc_parity_bits;
+ val = DEC_EMPTY_EN | (ecc_msg_bits << DEC_CS_S) |
+ (DEC_CON_CORRECT << DEC_CON_S) |
+ (ECC_MODE_NFI << snf->ecc_soc->mode_shift) | i;
+ ecc_write32(snf, ECC_DECCNFG, val);
+
+ return 0;
+}
+
+int mtk_snand_ecc_encoder_start(struct mtk_snand *snf)
+{
+ int ret;
+
+ ret = mtk_ecc_wait_idle(snf, ECC_ENCIDLE);
+ if (ret) {
+ ecc_write16(snf, ECC_ENCCON, 0);
+ mtk_ecc_wait_idle(snf, ECC_ENCIDLE);
+ }
+
+ ecc_write16(snf, ECC_ENCCON, ENC_EN);
+
+ return 0;
+}
+
+void mtk_snand_ecc_encoder_stop(struct mtk_snand *snf)
+{
+ mtk_ecc_wait_idle(snf, ECC_ENCIDLE);
+ ecc_write16(snf, ECC_ENCCON, 0);
+}
+
+int mtk_snand_ecc_decoder_start(struct mtk_snand *snf)
+{
+ int ret;
+
+ ret = mtk_ecc_wait_idle(snf, ECC_DECIDLE);
+ if (ret) {
+ ecc_write16(snf, ECC_DECCON, 0);
+ mtk_ecc_wait_idle(snf, ECC_DECIDLE);
+ }
+
+ ecc_write16(snf, ECC_DECCON, DEC_EN);
+
+ return 0;
+}
+
+void mtk_snand_ecc_decoder_stop(struct mtk_snand *snf)
+{
+ mtk_ecc_wait_idle(snf, ECC_DECIDLE);
+ ecc_write16(snf, ECC_DECCON, 0);
+}
+
+int mtk_ecc_wait_decoder_done(struct mtk_snand *snf)
+{
+ uint16_t val, step_mask = (1 << snf->ecc_steps) - 1;
+ uint32_t reg = snf->ecc_soc->regs[ECC_DECDONE];
+ int ret;
+
+ ret = read16_poll_timeout(snf->ecc_base + reg, val,
+ (val & step_mask) == step_mask, 0,
+ ECC_TIMEOUT);
+ if (ret)
+ snand_log_ecc(snf->pdev, "ECC decoder is busy\n");
+
+ return ret;
+}
+
+int mtk_ecc_check_decode_error(struct mtk_snand *snf, uint32_t page)
+{
+ uint32_t i, regi, fi, errnum;
+ uint32_t errnum_shift = snf->ecc_soc->errnum_shift;
+ uint32_t errnum_mask = (1 << snf->ecc_soc->errnum_bits) - 1;
+ int ret = 0;
+
+ for (i = 0; i < snf->ecc_steps; i++) {
+ regi = i / 4;
+ fi = i % 4;
+
+ errnum = ecc_read32(snf, ECC_DECENUM(regi));
+ errnum = (errnum >> (fi * errnum_shift)) & errnum_mask;
+ if (!errnum)
+ continue;
+
+ if (errnum <= snf->ecc_strength) {
+ if (ret >= 0)
+ ret += errnum;
+ continue;
+ }
+
+ snand_log_ecc(snf->pdev,
+ "Uncorrectable bitflips in page %u sect %u\n",
+ page, i);
+ ret = -EBADMSG;
+ }
+
+ return ret;
+}
--- /dev/null
+++ b/drivers/mtd/mtk-snand/mtk-snand-ids.c
@@ -0,0 +1,511 @@
+// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
+/*
+ * Copyright (C) 2020 MediaTek Inc. All Rights Reserved.
+ *
+ * Author: Weijie Gao <weijie.gao@mediatek.com>
+ */
+
+#include "mtk-snand-def.h"
+
+static int mtk_snand_winbond_select_die(struct mtk_snand *snf, uint32_t dieidx);
+static int mtk_snand_micron_select_die(struct mtk_snand *snf, uint32_t dieidx);
+
+#define SNAND_MEMORG_512M_2K_64 SNAND_MEMORG(2048, 64, 64, 512, 1, 1)
+#define SNAND_MEMORG_1G_2K_64 SNAND_MEMORG(2048, 64, 64, 1024, 1, 1)
+#define SNAND_MEMORG_2G_2K_64 SNAND_MEMORG(2048, 64, 64, 2048, 1, 1)
+#define SNAND_MEMORG_2G_2K_120 SNAND_MEMORG(2048, 120, 64, 2048, 1, 1)
+#define SNAND_MEMORG_4G_2K_64 SNAND_MEMORG(2048, 64, 64, 4096, 1, 1)
+#define SNAND_MEMORG_1G_2K_120 SNAND_MEMORG(2048, 120, 64, 1024, 1, 1)
+#define SNAND_MEMORG_1G_2K_128 SNAND_MEMORG(2048, 128, 64, 1024, 1, 1)
+#define SNAND_MEMORG_2G_2K_128 SNAND_MEMORG(2048, 128, 64, 2048, 1, 1)
+#define SNAND_MEMORG_4G_2K_128 SNAND_MEMORG(2048, 128, 64, 4096, 1, 1)
+#define SNAND_MEMORG_4G_4K_240 SNAND_MEMORG(4096, 240, 64, 2048, 1, 1)
+#define SNAND_MEMORG_4G_4K_256 SNAND_MEMORG(4096, 256, 64, 2048, 1, 1)
+#define SNAND_MEMORG_8G_4K_256 SNAND_MEMORG(4096, 256, 64, 4096, 1, 1)
+#define SNAND_MEMORG_2G_2K_64_2P SNAND_MEMORG(2048, 64, 64, 2048, 2, 1)
+#define SNAND_MEMORG_2G_2K_64_2D SNAND_MEMORG(2048, 64, 64, 1024, 1, 2)
+#define SNAND_MEMORG_2G_2K_128_2P SNAND_MEMORG(2048, 128, 64, 2048, 2, 1)
+#define SNAND_MEMORG_4G_2K_64_2P SNAND_MEMORG(2048, 64, 64, 4096, 2, 1)
+#define SNAND_MEMORG_4G_2K_128_2P_2D SNAND_MEMORG(2048, 128, 64, 2048, 2, 2)
+#define SNAND_MEMORG_8G_4K_256_2D SNAND_MEMORG(4096, 256, 64, 2048, 1, 2)
+
+static const SNAND_IO_CAP(snand_cap_read_from_cache_quad,
+ SPI_IO_1_1_1 | SPI_IO_1_1_2 | SPI_IO_1_2_2 | SPI_IO_1_1_4 |
+ SPI_IO_1_4_4,
+ SNAND_OP(SNAND_IO_1_1_1, SNAND_CMD_READ_FROM_CACHE, 8),
+ SNAND_OP(SNAND_IO_1_1_2, SNAND_CMD_READ_FROM_CACHE_X2, 8),
+ SNAND_OP(SNAND_IO_1_2_2, SNAND_CMD_READ_FROM_CACHE_DUAL, 4),
+ SNAND_OP(SNAND_IO_1_1_4, SNAND_CMD_READ_FROM_CACHE_X4, 8),
+ SNAND_OP(SNAND_IO_1_4_4, SNAND_CMD_READ_FROM_CACHE_QUAD, 4));
+
+static const SNAND_IO_CAP(snand_cap_read_from_cache_quad_q2d,
+ SPI_IO_1_1_1 | SPI_IO_1_1_2 | SPI_IO_1_2_2 | SPI_IO_1_1_4 |
+ SPI_IO_1_4_4,
+ SNAND_OP(SNAND_IO_1_1_1, SNAND_CMD_READ_FROM_CACHE, 8),
+ SNAND_OP(SNAND_IO_1_1_2, SNAND_CMD_READ_FROM_CACHE_X2, 8),
+ SNAND_OP(SNAND_IO_1_2_2, SNAND_CMD_READ_FROM_CACHE_DUAL, 4),
+ SNAND_OP(SNAND_IO_1_1_4, SNAND_CMD_READ_FROM_CACHE_X4, 8),
+ SNAND_OP(SNAND_IO_1_4_4, SNAND_CMD_READ_FROM_CACHE_QUAD, 2));
+
+static const SNAND_IO_CAP(snand_cap_read_from_cache_quad_a8d,
+ SPI_IO_1_1_1 | SPI_IO_1_1_2 | SPI_IO_1_2_2 | SPI_IO_1_1_4 |
+ SPI_IO_1_4_4,
+ SNAND_OP(SNAND_IO_1_1_1, SNAND_CMD_READ_FROM_CACHE, 8),
+ SNAND_OP(SNAND_IO_1_1_2, SNAND_CMD_READ_FROM_CACHE_X2, 8),
+ SNAND_OP(SNAND_IO_1_2_2, SNAND_CMD_READ_FROM_CACHE_DUAL, 8),
+ SNAND_OP(SNAND_IO_1_1_4, SNAND_CMD_READ_FROM_CACHE_X4, 8),
+ SNAND_OP(SNAND_IO_1_4_4, SNAND_CMD_READ_FROM_CACHE_QUAD, 8));
+
+static const SNAND_IO_CAP(snand_cap_read_from_cache_x4,
+ SPI_IO_1_1_1 | SPI_IO_1_1_2 | SPI_IO_1_1_4,
+ SNAND_OP(SNAND_IO_1_1_1, SNAND_CMD_READ_FROM_CACHE, 8),
+ SNAND_OP(SNAND_IO_1_1_2, SNAND_CMD_READ_FROM_CACHE_X2, 8),
+ SNAND_OP(SNAND_IO_1_1_4, SNAND_CMD_READ_FROM_CACHE_X4, 8));
+
+static const SNAND_IO_CAP(snand_cap_read_from_cache_x4_only,
+ SPI_IO_1_1_1 | SPI_IO_1_1_4,
+ SNAND_OP(SNAND_IO_1_1_1, SNAND_CMD_READ_FROM_CACHE, 8),
+ SNAND_OP(SNAND_IO_1_1_4, SNAND_CMD_READ_FROM_CACHE_X4, 8));
+
+static const SNAND_IO_CAP(snand_cap_program_load_x1,
+ SPI_IO_1_1_1,
+ SNAND_OP(SNAND_IO_1_1_1, SNAND_CMD_PROGRAM_LOAD, 0));
+
+static const SNAND_IO_CAP(snand_cap_program_load_x4,
+ SPI_IO_1_1_1 | SPI_IO_1_1_4,
+ SNAND_OP(SNAND_IO_1_1_1, SNAND_CMD_PROGRAM_LOAD, 0),
+ SNAND_OP(SNAND_IO_1_1_4, SNAND_CMD_PROGRAM_LOAD_X4, 0));
+
+static const struct snand_flash_info snand_flash_ids[] = {
+ SNAND_INFO("W25N512GV", SNAND_ID(SNAND_ID_DYMMY, 0xef, 0xaa, 0x20),
+ SNAND_MEMORG_512M_2K_64,
+ &snand_cap_read_from_cache_quad,
+ &snand_cap_program_load_x4),
+ SNAND_INFO("W25N01GV", SNAND_ID(SNAND_ID_DYMMY, 0xef, 0xaa, 0x21),
+ SNAND_MEMORG_1G_2K_64,
+ &snand_cap_read_from_cache_quad,
+ &snand_cap_program_load_x4),
+ SNAND_INFO("W25M02GV", SNAND_ID(SNAND_ID_DYMMY, 0xef, 0xab, 0x21),
+ SNAND_MEMORG_2G_2K_64_2D,
+ &snand_cap_read_from_cache_quad,
+ &snand_cap_program_load_x4,
+ mtk_snand_winbond_select_die),
+ SNAND_INFO("W25N02KV", SNAND_ID(SNAND_ID_DYMMY, 0xef, 0xaa, 0x22),
+ SNAND_MEMORG_2G_2K_128,
+ &snand_cap_read_from_cache_quad,
+ &snand_cap_program_load_x4),
+
+ SNAND_INFO("GD5F1GQ4UAWxx", SNAND_ID(SNAND_ID_ADDR, 0xc8, 0x10),
+ SNAND_MEMORG_1G_2K_64,
+ &snand_cap_read_from_cache_quad_q2d,
+ &snand_cap_program_load_x4),
+ SNAND_INFO("GD5F1GQ4UExIG", SNAND_ID(SNAND_ID_ADDR, 0xc8, 0xd1),
+ SNAND_MEMORG_1G_2K_128,
+ &snand_cap_read_from_cache_quad_q2d,
+ &snand_cap_program_load_x4),
+ SNAND_INFO("GD5F1GQ4UExxH", SNAND_ID(SNAND_ID_ADDR, 0xc8, 0xd9),
+ SNAND_MEMORG_1G_2K_64,
+ &snand_cap_read_from_cache_quad_q2d,
+ &snand_cap_program_load_x4),
+ SNAND_INFO("GD5F1GQ4xAYIG", SNAND_ID(SNAND_ID_ADDR, 0xc8, 0xf1),
+ SNAND_MEMORG_1G_2K_64,
+ &snand_cap_read_from_cache_quad_q2d,
+ &snand_cap_program_load_x4),
+ SNAND_INFO("GD5F2GQ4UExIG", SNAND_ID(SNAND_ID_ADDR, 0xc8, 0xd2),
+ SNAND_MEMORG_2G_2K_128,
+ &snand_cap_read_from_cache_quad_q2d,
+ &snand_cap_program_load_x4),
+ SNAND_INFO("GD5F2GQ5UExxH", SNAND_ID(SNAND_ID_ADDR, 0xc8, 0x32),
+ SNAND_MEMORG_2G_2K_64,
+ &snand_cap_read_from_cache_quad_a8d,
+ &snand_cap_program_load_x4),
+ SNAND_INFO("GD5F2GQ4xAYIG", SNAND_ID(SNAND_ID_ADDR, 0xc8, 0xf2),
+ SNAND_MEMORG_2G_2K_64,
+ &snand_cap_read_from_cache_quad_q2d,
+ &snand_cap_program_load_x4),
+ SNAND_INFO("GD5F4GQ4UBxIG", SNAND_ID(SNAND_ID_ADDR, 0xc8, 0xd4),
+ SNAND_MEMORG_4G_4K_256,
+ &snand_cap_read_from_cache_quad_q2d,
+ &snand_cap_program_load_x4),
+ SNAND_INFO("GD5F4GQ4xAYIG", SNAND_ID(SNAND_ID_ADDR, 0xc8, 0xf4),
+ SNAND_MEMORG_4G_2K_64,
+ &snand_cap_read_from_cache_quad_q2d,
+ &snand_cap_program_load_x4),
+ SNAND_INFO("GD5F2GQ5UExxG", SNAND_ID(SNAND_ID_DYMMY, 0xc8, 0x52),
+ SNAND_MEMORG_2G_2K_128,
+ &snand_cap_read_from_cache_quad_q2d,
+ &snand_cap_program_load_x4),
+ SNAND_INFO("GD5F4GQ4UCxIG", SNAND_ID(SNAND_ID_DYMMY, 0xc8, 0xb4),
+ SNAND_MEMORG_4G_4K_256,
+ &snand_cap_read_from_cache_quad_q2d,
+ &snand_cap_program_load_x4),
+
+ SNAND_INFO("MX35LF1GE4AB", SNAND_ID(SNAND_ID_DYMMY, 0xc2, 0x12),
+ SNAND_MEMORG_1G_2K_64,
+ &snand_cap_read_from_cache_x4,
+ &snand_cap_program_load_x4),
+ SNAND_INFO("MX35LF1G24AD", SNAND_ID(SNAND_ID_DYMMY, 0xc2, 0x14),
+ SNAND_MEMORG_1G_2K_128,
+ &snand_cap_read_from_cache_quad,
+ &snand_cap_program_load_x4),
+ SNAND_INFO("MX31LF1GE4BC", SNAND_ID(SNAND_ID_DYMMY, 0xc2, 0x1e),
+ SNAND_MEMORG_1G_2K_64,
+ &snand_cap_read_from_cache_x4,
+ &snand_cap_program_load_x4),
+ SNAND_INFO("MX35LF2GE4AB", SNAND_ID(SNAND_ID_DYMMY, 0xc2, 0x22),
+ SNAND_MEMORG_2G_2K_64,
+ &snand_cap_read_from_cache_x4,
+ &snand_cap_program_load_x4),
+ SNAND_INFO("MX35LF2G24AD", SNAND_ID(SNAND_ID_DYMMY, 0xc2, 0x24),
+ SNAND_MEMORG_2G_2K_128,
+ &snand_cap_read_from_cache_quad,
+ &snand_cap_program_load_x4),
+ SNAND_INFO("MX35LF2GE4AD", SNAND_ID(SNAND_ID_DYMMY, 0xc2, 0x26),
+ SNAND_MEMORG_2G_2K_128,
+ &snand_cap_read_from_cache_x4,
+ &snand_cap_program_load_x4),
+ SNAND_INFO("MX35LF2G14AC", SNAND_ID(SNAND_ID_DYMMY, 0xc2, 0x20),
+ SNAND_MEMORG_2G_2K_64,
+ &snand_cap_read_from_cache_x4,
+ &snand_cap_program_load_x4),
+ SNAND_INFO("MX35LF4G24AD", SNAND_ID(SNAND_ID_DYMMY, 0xc2, 0x35),
+ SNAND_MEMORG_4G_4K_256,
+ &snand_cap_read_from_cache_quad,
+ &snand_cap_program_load_x4),
+ SNAND_INFO("MX35LF4GE4AD", SNAND_ID(SNAND_ID_DYMMY, 0xc2, 0x37),
+ SNAND_MEMORG_4G_4K_256,
+ &snand_cap_read_from_cache_x4,
+ &snand_cap_program_load_x4),
+
+ SNAND_INFO("MT29F1G01AAADD", SNAND_ID(SNAND_ID_DYMMY, 0x2c, 0x12),
+ SNAND_MEMORG_1G_2K_64,
+ &snand_cap_read_from_cache_x4,
+ &snand_cap_program_load_x1),
+ SNAND_INFO("MT29F1G01ABAFD", SNAND_ID(SNAND_ID_DYMMY, 0x2c, 0x14),
+ SNAND_MEMORG_1G_2K_128,
+ &snand_cap_read_from_cache_quad,
+ &snand_cap_program_load_x4),
+ SNAND_INFO("MT29F2G01AAAED", SNAND_ID(SNAND_ID_DYMMY, 0x2c, 0x9f),
+ SNAND_MEMORG_2G_2K_64_2P,
+ &snand_cap_read_from_cache_x4,
+ &snand_cap_program_load_x1),
+ SNAND_INFO("MT29F2G01ABAGD", SNAND_ID(SNAND_ID_DYMMY, 0x2c, 0x24),
+ SNAND_MEMORG_2G_2K_128_2P,
+ &snand_cap_read_from_cache_quad,
+ &snand_cap_program_load_x4),
+ SNAND_INFO("MT29F4G01AAADD", SNAND_ID(SNAND_ID_DYMMY, 0x2c, 0x32),
+ SNAND_MEMORG_4G_2K_64_2P,
+ &snand_cap_read_from_cache_x4,
+ &snand_cap_program_load_x1),
+ SNAND_INFO("MT29F4G01ABAFD", SNAND_ID(SNAND_ID_DYMMY, 0x2c, 0x34),
+ SNAND_MEMORG_4G_4K_256,
+ &snand_cap_read_from_cache_quad,
+ &snand_cap_program_load_x4),
+ SNAND_INFO("MT29F4G01ADAGD", SNAND_ID(SNAND_ID_DYMMY, 0x2c, 0x36),
+ SNAND_MEMORG_4G_2K_128_2P_2D,
+ &snand_cap_read_from_cache_quad,
+ &snand_cap_program_load_x4,
+ mtk_snand_micron_select_die),
+ SNAND_INFO("MT29F8G01ADAFD", SNAND_ID(SNAND_ID_DYMMY, 0x2c, 0x46),
+ SNAND_MEMORG_8G_4K_256_2D,
+ &snand_cap_read_from_cache_quad,
+ &snand_cap_program_load_x4,
+ mtk_snand_micron_select_die),
+
+ SNAND_INFO("TC58CVG0S3HRAIG", SNAND_ID(SNAND_ID_DYMMY, 0x98, 0xc2),
+ SNAND_MEMORG_1G_2K_128,
+ &snand_cap_read_from_cache_x4,
+ &snand_cap_program_load_x1),
+ SNAND_INFO("TC58CVG1S3HRAIG", SNAND_ID(SNAND_ID_DYMMY, 0x98, 0xcb),
+ SNAND_MEMORG_2G_2K_128,
+ &snand_cap_read_from_cache_x4,
+ &snand_cap_program_load_x1),
+ SNAND_INFO("TC58CVG2S0HRAIG", SNAND_ID(SNAND_ID_DYMMY, 0x98, 0xcd),
+ SNAND_MEMORG_4G_4K_256,
+ &snand_cap_read_from_cache_x4,
+ &snand_cap_program_load_x1),
+ SNAND_INFO("TC58CVG0S3HRAIJ", SNAND_ID(SNAND_ID_DYMMY, 0x98, 0xe2),
+ SNAND_MEMORG_1G_2K_128,
+ &snand_cap_read_from_cache_x4,
+ &snand_cap_program_load_x4),
+ SNAND_INFO("TC58CVG1S3HRAIJ", SNAND_ID(SNAND_ID_DYMMY, 0x98, 0xeb),
+ SNAND_MEMORG_2G_2K_128,
+ &snand_cap_read_from_cache_x4,
+ &snand_cap_program_load_x4),
+ SNAND_INFO("TC58CVG2S0HRAIJ", SNAND_ID(SNAND_ID_DYMMY, 0x98, 0xed),
+ SNAND_MEMORG_4G_4K_256,
+ &snand_cap_read_from_cache_x4,
+ &snand_cap_program_load_x4),
+ SNAND_INFO("TH58CVG3S0HRAIJ", SNAND_ID(SNAND_ID_DYMMY, 0x98, 0xe4),
+ SNAND_MEMORG_8G_4K_256,
+ &snand_cap_read_from_cache_x4,
+ &snand_cap_program_load_x4),
+
+ SNAND_INFO("F50L512M41A", SNAND_ID(SNAND_ID_DYMMY, 0xc8, 0x20),
+ SNAND_MEMORG_512M_2K_64,
+ &snand_cap_read_from_cache_x4,
+ &snand_cap_program_load_x4),
+ SNAND_INFO("F50L1G41A", SNAND_ID(SNAND_ID_DYMMY, 0xc8, 0x21),
+ SNAND_MEMORG_1G_2K_64,
+ &snand_cap_read_from_cache_x4,
+ &snand_cap_program_load_x4),
+ SNAND_INFO("F50L1G41LB", SNAND_ID(SNAND_ID_DYMMY, 0xc8, 0x01),
+ SNAND_MEMORG_1G_2K_64,
+ &snand_cap_read_from_cache_quad,
+ &snand_cap_program_load_x4),
+ SNAND_INFO("F50L2G41LB", SNAND_ID(SNAND_ID_DYMMY, 0xc8, 0x0a),
+ SNAND_MEMORG_2G_2K_64_2D,
+ &snand_cap_read_from_cache_quad,
+ &snand_cap_program_load_x4,
+ mtk_snand_winbond_select_die),
+
+ SNAND_INFO("CS11G0T0A0AA", SNAND_ID(SNAND_ID_DYMMY, 0x6b, 0x00),
+ SNAND_MEMORG_1G_2K_128,
+ &snand_cap_read_from_cache_quad_q2d,
+ &snand_cap_program_load_x4),
+ SNAND_INFO("CS11G0G0A0AA", SNAND_ID(SNAND_ID_DYMMY, 0x6b, 0x10),
+ SNAND_MEMORG_1G_2K_128,
+ &snand_cap_read_from_cache_quad_q2d,
+ &snand_cap_program_load_x4),
+ SNAND_INFO("CS11G0S0A0AA", SNAND_ID(SNAND_ID_DYMMY, 0x6b, 0x20),
+ SNAND_MEMORG_1G_2K_64,
+ &snand_cap_read_from_cache_quad_q2d,
+ &snand_cap_program_load_x4),
+ SNAND_INFO("CS11G1T0A0AA", SNAND_ID(SNAND_ID_DYMMY, 0x6b, 0x01),
+ SNAND_MEMORG_2G_2K_128,
+ &snand_cap_read_from_cache_quad_q2d,
+ &snand_cap_program_load_x4),
+ SNAND_INFO("CS11G1S0A0AA", SNAND_ID(SNAND_ID_DYMMY, 0x6b, 0x21),
+ SNAND_MEMORG_2G_2K_64,
+ &snand_cap_read_from_cache_quad_q2d,
+ &snand_cap_program_load_x4),
+ SNAND_INFO("CS11G2T0A0AA", SNAND_ID(SNAND_ID_DYMMY, 0x6b, 0x02),
+ SNAND_MEMORG_4G_2K_128,
+ &snand_cap_read_from_cache_quad_q2d,
+ &snand_cap_program_load_x4),
+ SNAND_INFO("CS11G2S0A0AA", SNAND_ID(SNAND_ID_DYMMY, 0x6b, 0x22),
+ SNAND_MEMORG_4G_2K_64,
+ &snand_cap_read_from_cache_quad_q2d,
+ &snand_cap_program_load_x4),
+
+ SNAND_INFO("EM73B044VCA", SNAND_ID(SNAND_ID_DYMMY, 0xd5, 0x01),
+ SNAND_MEMORG_512M_2K_64,
+ &snand_cap_read_from_cache_quad_q2d,
+ &snand_cap_program_load_x4),
+ SNAND_INFO("EM73C044SNB", SNAND_ID(SNAND_ID_DYMMY, 0xd5, 0x11),
+ SNAND_MEMORG_1G_2K_120,
+ &snand_cap_read_from_cache_quad_q2d,
+ &snand_cap_program_load_x4),
+ SNAND_INFO("EM73C044SNF", SNAND_ID(SNAND_ID_DYMMY, 0xd5, 0x09),
+ SNAND_MEMORG_1G_2K_128,
+ &snand_cap_read_from_cache_quad_q2d,
+ &snand_cap_program_load_x4),
+ SNAND_INFO("EM73C044VCA", SNAND_ID(SNAND_ID_DYMMY, 0xd5, 0x18),
+ SNAND_MEMORG_1G_2K_64,
+ &snand_cap_read_from_cache_quad_q2d,
+ &snand_cap_program_load_x4),
+ SNAND_INFO("EM73C044SNA", SNAND_ID(SNAND_ID_DYMMY, 0xd5, 0x19),
+ SNAND_MEMORG(2048, 64, 128, 512, 1, 1),
+ &snand_cap_read_from_cache_quad_q2d,
+ &snand_cap_program_load_x4),
+ SNAND_INFO("EM73C044VCD", SNAND_ID(SNAND_ID_DYMMY, 0xd5, 0x1c),
+ SNAND_MEMORG_1G_2K_64,
+ &snand_cap_read_from_cache_quad_q2d,
+ &snand_cap_program_load_x4),
+ SNAND_INFO("EM73C044SND", SNAND_ID(SNAND_ID_DYMMY, 0xd5, 0x1d),
+ SNAND_MEMORG_1G_2K_64,
+ &snand_cap_read_from_cache_quad_q2d,
+ &snand_cap_program_load_x4),
+ SNAND_INFO("EM73D044SND", SNAND_ID(SNAND_ID_DYMMY, 0xd5, 0x1e),
+ SNAND_MEMORG_2G_2K_64,
+ &snand_cap_read_from_cache_quad_q2d,
+ &snand_cap_program_load_x4),
+ SNAND_INFO("EM73C044VCC", SNAND_ID(SNAND_ID_DYMMY, 0xd5, 0x22),
+ SNAND_MEMORG_1G_2K_64,
+ &snand_cap_read_from_cache_quad_q2d,
+ &snand_cap_program_load_x4),
+ SNAND_INFO("EM73C044VCF", SNAND_ID(SNAND_ID_DYMMY, 0xd5, 0x25),
+ SNAND_MEMORG_1G_2K_64,
+ &snand_cap_read_from_cache_quad_q2d,
+ &snand_cap_program_load_x4),
+ SNAND_INFO("EM73C044SNC", SNAND_ID(SNAND_ID_DYMMY, 0xd5, 0x31),
+ SNAND_MEMORG_1G_2K_128,
+ &snand_cap_read_from_cache_quad_q2d,
+ &snand_cap_program_load_x4),
+ SNAND_INFO("EM73D044SNC", SNAND_ID(SNAND_ID_DYMMY, 0xd5, 0x0a),
+ SNAND_MEMORG_2G_2K_120,
+ &snand_cap_read_from_cache_quad_q2d,
+ &snand_cap_program_load_x4),
+ SNAND_INFO("EM73D044SNA", SNAND_ID(SNAND_ID_DYMMY, 0xd5, 0x12),
+ SNAND_MEMORG_2G_2K_128,
+ &snand_cap_read_from_cache_quad_q2d,
+ &snand_cap_program_load_x4),
+ SNAND_INFO("EM73D044SNF", SNAND_ID(SNAND_ID_DYMMY, 0xd5, 0x10),
+ SNAND_MEMORG_2G_2K_128,
+ &snand_cap_read_from_cache_quad_q2d,
+ &snand_cap_program_load_x4),
+ SNAND_INFO("EM73D044VCA", SNAND_ID(SNAND_ID_DYMMY, 0xd5, 0x13),
+ SNAND_MEMORG_2G_2K_128,
+ &snand_cap_read_from_cache_quad_q2d,
+ &snand_cap_program_load_x4),
+ SNAND_INFO("EM73D044VCB", SNAND_ID(SNAND_ID_DYMMY, 0xd5, 0x14),
+ SNAND_MEMORG_2G_2K_64,
+ &snand_cap_read_from_cache_quad_q2d,
+ &snand_cap_program_load_x4),
+ SNAND_INFO("EM73D044VCD", SNAND_ID(SNAND_ID_DYMMY, 0xd5, 0x17),
+ SNAND_MEMORG_2G_2K_128,
+ &snand_cap_read_from_cache_quad_q2d,
+ &snand_cap_program_load_x4),
+ SNAND_INFO("EM73D044VCH", SNAND_ID(SNAND_ID_DYMMY, 0xd5, 0x1b),
+ SNAND_MEMORG_2G_2K_64,
+ &snand_cap_read_from_cache_quad_q2d,
+ &snand_cap_program_load_x4),
+ SNAND_INFO("EM73D044SND", SNAND_ID(SNAND_ID_DYMMY, 0xd5, 0x1d),
+ SNAND_MEMORG_2G_2K_64,
+ &snand_cap_read_from_cache_quad_q2d,
+ &snand_cap_program_load_x4),