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ar8216.c
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ar8216.c
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/*
* ar8216.c: AR8216 switch driver
*
* Copyright (C) 2009 Felix Fietkau <nbd@nbd.name>
* Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <linux/if.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/list.h>
#include <linux/if_ether.h>
#include <linux/skbuff.h>
#include <linux/netdevice.h>
#include <linux/netlink.h>
#include <linux/of_device.h>
#include <linux/of_mdio.h>
#include <linux/of_net.h>
#include <linux/bitops.h>
#include <net/genetlink.h>
#include <linux/switch.h>
#include <linux/delay.h>
#include <linux/phy.h>
#include <linux/etherdevice.h>
#include <linux/lockdep.h>
#include <linux/ar8216_platform.h>
#include <linux/workqueue.h>
#include <linux/version.h>
#include "ar8216.h"
extern const struct ar8xxx_chip ar8327_chip;
extern const struct ar8xxx_chip ar8337_chip;
#define MIB_DESC_BASIC(_s , _o, _n) \
{ \
.size = (_s), \
.offset = (_o), \
.name = (_n), \
.type = AR8XXX_MIB_BASIC, \
}
#define MIB_DESC_EXT(_s , _o, _n) \
{ \
.size = (_s), \
.offset = (_o), \
.name = (_n), \
.type = AR8XXX_MIB_EXTENDED, \
}
static const struct ar8xxx_mib_desc ar8216_mibs[] = {
MIB_DESC_EXT(1, AR8216_STATS_RXBROAD, "RxBroad"),
MIB_DESC_EXT(1, AR8216_STATS_RXPAUSE, "RxPause"),
MIB_DESC_EXT(1, AR8216_STATS_RXMULTI, "RxMulti"),
MIB_DESC_EXT(1, AR8216_STATS_RXFCSERR, "RxFcsErr"),
MIB_DESC_EXT(1, AR8216_STATS_RXALIGNERR, "RxAlignErr"),
MIB_DESC_EXT(1, AR8216_STATS_RXRUNT, "RxRunt"),
MIB_DESC_EXT(1, AR8216_STATS_RXFRAGMENT, "RxFragment"),
MIB_DESC_EXT(1, AR8216_STATS_RX64BYTE, "Rx64Byte"),
MIB_DESC_EXT(1, AR8216_STATS_RX128BYTE, "Rx128Byte"),
MIB_DESC_EXT(1, AR8216_STATS_RX256BYTE, "Rx256Byte"),
MIB_DESC_EXT(1, AR8216_STATS_RX512BYTE, "Rx512Byte"),
MIB_DESC_EXT(1, AR8216_STATS_RX1024BYTE, "Rx1024Byte"),
MIB_DESC_EXT(1, AR8216_STATS_RXMAXBYTE, "RxMaxByte"),
MIB_DESC_EXT(1, AR8216_STATS_RXTOOLONG, "RxTooLong"),
MIB_DESC_BASIC(2, AR8216_STATS_RXGOODBYTE, "RxGoodByte"),
MIB_DESC_EXT(2, AR8216_STATS_RXBADBYTE, "RxBadByte"),
MIB_DESC_EXT(1, AR8216_STATS_RXOVERFLOW, "RxOverFlow"),
MIB_DESC_EXT(1, AR8216_STATS_FILTERED, "Filtered"),
MIB_DESC_EXT(1, AR8216_STATS_TXBROAD, "TxBroad"),
MIB_DESC_EXT(1, AR8216_STATS_TXPAUSE, "TxPause"),
MIB_DESC_EXT(1, AR8216_STATS_TXMULTI, "TxMulti"),
MIB_DESC_EXT(1, AR8216_STATS_TXUNDERRUN, "TxUnderRun"),
MIB_DESC_EXT(1, AR8216_STATS_TX64BYTE, "Tx64Byte"),
MIB_DESC_EXT(1, AR8216_STATS_TX128BYTE, "Tx128Byte"),
MIB_DESC_EXT(1, AR8216_STATS_TX256BYTE, "Tx256Byte"),
MIB_DESC_EXT(1, AR8216_STATS_TX512BYTE, "Tx512Byte"),
MIB_DESC_EXT(1, AR8216_STATS_TX1024BYTE, "Tx1024Byte"),
MIB_DESC_EXT(1, AR8216_STATS_TXMAXBYTE, "TxMaxByte"),
MIB_DESC_EXT(1, AR8216_STATS_TXOVERSIZE, "TxOverSize"),
MIB_DESC_BASIC(2, AR8216_STATS_TXBYTE, "TxByte"),
MIB_DESC_EXT(1, AR8216_STATS_TXCOLLISION, "TxCollision"),
MIB_DESC_EXT(1, AR8216_STATS_TXABORTCOL, "TxAbortCol"),
MIB_DESC_EXT(1, AR8216_STATS_TXMULTICOL, "TxMultiCol"),
MIB_DESC_EXT(1, AR8216_STATS_TXSINGLECOL, "TxSingleCol"),
MIB_DESC_EXT(1, AR8216_STATS_TXEXCDEFER, "TxExcDefer"),
MIB_DESC_EXT(1, AR8216_STATS_TXDEFER, "TxDefer"),
MIB_DESC_EXT(1, AR8216_STATS_TXLATECOL, "TxLateCol"),
};
const struct ar8xxx_mib_desc ar8236_mibs[39] = {
MIB_DESC_EXT(1, AR8236_STATS_RXBROAD, "RxBroad"),
MIB_DESC_EXT(1, AR8236_STATS_RXPAUSE, "RxPause"),
MIB_DESC_EXT(1, AR8236_STATS_RXMULTI, "RxMulti"),
MIB_DESC_EXT(1, AR8236_STATS_RXFCSERR, "RxFcsErr"),
MIB_DESC_EXT(1, AR8236_STATS_RXALIGNERR, "RxAlignErr"),
MIB_DESC_EXT(1, AR8236_STATS_RXRUNT, "RxRunt"),
MIB_DESC_EXT(1, AR8236_STATS_RXFRAGMENT, "RxFragment"),
MIB_DESC_EXT(1, AR8236_STATS_RX64BYTE, "Rx64Byte"),
MIB_DESC_EXT(1, AR8236_STATS_RX128BYTE, "Rx128Byte"),
MIB_DESC_EXT(1, AR8236_STATS_RX256BYTE, "Rx256Byte"),
MIB_DESC_EXT(1, AR8236_STATS_RX512BYTE, "Rx512Byte"),
MIB_DESC_EXT(1, AR8236_STATS_RX1024BYTE, "Rx1024Byte"),
MIB_DESC_EXT(1, AR8236_STATS_RX1518BYTE, "Rx1518Byte"),
MIB_DESC_EXT(1, AR8236_STATS_RXMAXBYTE, "RxMaxByte"),
MIB_DESC_EXT(1, AR8236_STATS_RXTOOLONG, "RxTooLong"),
MIB_DESC_BASIC(2, AR8236_STATS_RXGOODBYTE, "RxGoodByte"),
MIB_DESC_EXT(2, AR8236_STATS_RXBADBYTE, "RxBadByte"),
MIB_DESC_EXT(1, AR8236_STATS_RXOVERFLOW, "RxOverFlow"),
MIB_DESC_EXT(1, AR8236_STATS_FILTERED, "Filtered"),
MIB_DESC_EXT(1, AR8236_STATS_TXBROAD, "TxBroad"),
MIB_DESC_EXT(1, AR8236_STATS_TXPAUSE, "TxPause"),
MIB_DESC_EXT(1, AR8236_STATS_TXMULTI, "TxMulti"),
MIB_DESC_EXT(1, AR8236_STATS_TXUNDERRUN, "TxUnderRun"),
MIB_DESC_EXT(1, AR8236_STATS_TX64BYTE, "Tx64Byte"),
MIB_DESC_EXT(1, AR8236_STATS_TX128BYTE, "Tx128Byte"),
MIB_DESC_EXT(1, AR8236_STATS_TX256BYTE, "Tx256Byte"),
MIB_DESC_EXT(1, AR8236_STATS_TX512BYTE, "Tx512Byte"),
MIB_DESC_EXT(1, AR8236_STATS_TX1024BYTE, "Tx1024Byte"),
MIB_DESC_EXT(1, AR8236_STATS_TX1518BYTE, "Tx1518Byte"),
MIB_DESC_EXT(1, AR8236_STATS_TXMAXBYTE, "TxMaxByte"),
MIB_DESC_EXT(1, AR8236_STATS_TXOVERSIZE, "TxOverSize"),
MIB_DESC_BASIC(2, AR8236_STATS_TXBYTE, "TxByte"),
MIB_DESC_EXT(1, AR8236_STATS_TXCOLLISION, "TxCollision"),
MIB_DESC_EXT(1, AR8236_STATS_TXABORTCOL, "TxAbortCol"),
MIB_DESC_EXT(1, AR8236_STATS_TXMULTICOL, "TxMultiCol"),
MIB_DESC_EXT(1, AR8236_STATS_TXSINGLECOL, "TxSingleCol"),
MIB_DESC_EXT(1, AR8236_STATS_TXEXCDEFER, "TxExcDefer"),
MIB_DESC_EXT(1, AR8236_STATS_TXDEFER, "TxDefer"),
MIB_DESC_EXT(1, AR8236_STATS_TXLATECOL, "TxLateCol"),
};
static DEFINE_MUTEX(ar8xxx_dev_list_lock);
static LIST_HEAD(ar8xxx_dev_list);
static void
ar8xxx_mib_start(struct ar8xxx_priv *priv);
static void
ar8xxx_mib_stop(struct ar8xxx_priv *priv);
/* inspired by phy_poll_reset in drivers/net/phy/phy_device.c */
static int
ar8xxx_phy_poll_reset(struct mii_bus *bus)
{
unsigned int sleep_msecs = 20;
int ret, elapsed, i;
for (elapsed = sleep_msecs; elapsed <= 600;
elapsed += sleep_msecs) {
msleep(sleep_msecs);
for (i = 0; i < AR8XXX_NUM_PHYS; i++) {
ret = mdiobus_read(bus, i, MII_BMCR);
if (ret < 0)
return ret;
if (ret & BMCR_RESET)
break;
if (i == AR8XXX_NUM_PHYS - 1) {
usleep_range(1000, 2000);
return 0;
}
}
}
return -ETIMEDOUT;
}
static int
ar8xxx_phy_check_aneg(struct phy_device *phydev)
{
int ret;
if (phydev->autoneg != AUTONEG_ENABLE)
return 0;
/*
* BMCR_ANENABLE might have been cleared
* by phy_init_hw in certain kernel versions
* therefore check for it
*/
ret = phy_read(phydev, MII_BMCR);
if (ret < 0)
return ret;
if (ret & BMCR_ANENABLE)
return 0;
dev_info(&phydev->mdio.dev, "ANEG disabled, re-enabling ...\n");
ret |= BMCR_ANENABLE | BMCR_ANRESTART;
return phy_write(phydev, MII_BMCR, ret);
}
void
ar8xxx_phy_init(struct ar8xxx_priv *priv)
{
int i;
struct mii_bus *bus;
bus = priv->sw_mii_bus ?: priv->mii_bus;
for (i = 0; i < AR8XXX_NUM_PHYS; i++) {
if (priv->chip->phy_fixup)
priv->chip->phy_fixup(priv, i);
/* initialize the port itself */
mdiobus_write(bus, i, MII_ADVERTISE,
ADVERTISE_ALL | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
if (ar8xxx_has_gige(priv))
mdiobus_write(bus, i, MII_CTRL1000, ADVERTISE_1000FULL);
mdiobus_write(bus, i, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
}
ar8xxx_phy_poll_reset(bus);
}
u32
ar8xxx_mii_read32(struct ar8xxx_priv *priv, int phy_id, int regnum)
{
struct mii_bus *bus = priv->mii_bus;
u16 lo, hi;
lo = bus->read(bus, phy_id, regnum);
hi = bus->read(bus, phy_id, regnum + 1);
return (hi << 16) | lo;
}
void
ar8xxx_mii_write32(struct ar8xxx_priv *priv, int phy_id, int regnum, u32 val)
{
struct mii_bus *bus = priv->mii_bus;
u16 lo, hi;
lo = val & 0xffff;
hi = (u16) (val >> 16);
if (priv->chip->mii_lo_first)
{
bus->write(bus, phy_id, regnum, lo);
bus->write(bus, phy_id, regnum + 1, hi);
} else {
bus->write(bus, phy_id, regnum + 1, hi);
bus->write(bus, phy_id, regnum, lo);
}
}
u32
ar8xxx_read(struct ar8xxx_priv *priv, int reg)
{
struct mii_bus *bus = priv->mii_bus;
u16 r1, r2, page;
u32 val;
split_addr((u32) reg, &r1, &r2, &page);
mutex_lock(&bus->mdio_lock);
bus->write(bus, 0x18, 0, page);
wait_for_page_switch();
val = ar8xxx_mii_read32(priv, 0x10 | r2, r1);
mutex_unlock(&bus->mdio_lock);
return val;
}
void
ar8xxx_write(struct ar8xxx_priv *priv, int reg, u32 val)
{
struct mii_bus *bus = priv->mii_bus;
u16 r1, r2, page;
split_addr((u32) reg, &r1, &r2, &page);
mutex_lock(&bus->mdio_lock);
bus->write(bus, 0x18, 0, page);
wait_for_page_switch();
ar8xxx_mii_write32(priv, 0x10 | r2, r1, val);
mutex_unlock(&bus->mdio_lock);
}
u32
ar8xxx_rmw(struct ar8xxx_priv *priv, int reg, u32 mask, u32 val)
{
struct mii_bus *bus = priv->mii_bus;
u16 r1, r2, page;
u32 ret;
split_addr((u32) reg, &r1, &r2, &page);
mutex_lock(&bus->mdio_lock);
bus->write(bus, 0x18, 0, page);
wait_for_page_switch();
ret = ar8xxx_mii_read32(priv, 0x10 | r2, r1);
ret &= ~mask;
ret |= val;
ar8xxx_mii_write32(priv, 0x10 | r2, r1, ret);
mutex_unlock(&bus->mdio_lock);
return ret;
}
void
ar8xxx_phy_dbg_read(struct ar8xxx_priv *priv, int phy_addr,
u16 dbg_addr, u16 *dbg_data)
{
struct mii_bus *bus = priv->mii_bus;
mutex_lock(&bus->mdio_lock);
bus->write(bus, phy_addr, MII_ATH_DBG_ADDR, dbg_addr);
*dbg_data = bus->read(bus, phy_addr, MII_ATH_DBG_DATA);
mutex_unlock(&bus->mdio_lock);
}
void
ar8xxx_phy_dbg_write(struct ar8xxx_priv *priv, int phy_addr,
u16 dbg_addr, u16 dbg_data)
{
struct mii_bus *bus = priv->mii_bus;
mutex_lock(&bus->mdio_lock);
bus->write(bus, phy_addr, MII_ATH_DBG_ADDR, dbg_addr);
bus->write(bus, phy_addr, MII_ATH_DBG_DATA, dbg_data);
mutex_unlock(&bus->mdio_lock);
}
static inline void
ar8xxx_phy_mmd_prep(struct mii_bus *bus, int phy_addr, u16 addr, u16 reg)
{
bus->write(bus, phy_addr, MII_ATH_MMD_ADDR, addr);
bus->write(bus, phy_addr, MII_ATH_MMD_DATA, reg);
bus->write(bus, phy_addr, MII_ATH_MMD_ADDR, addr | 0x4000);
}
void
ar8xxx_phy_mmd_write(struct ar8xxx_priv *priv, int phy_addr, u16 addr, u16 reg, u16 data)
{
struct mii_bus *bus = priv->mii_bus;
mutex_lock(&bus->mdio_lock);
ar8xxx_phy_mmd_prep(bus, phy_addr, addr, reg);
bus->write(bus, phy_addr, MII_ATH_MMD_DATA, data);
mutex_unlock(&bus->mdio_lock);
}
u16
ar8xxx_phy_mmd_read(struct ar8xxx_priv *priv, int phy_addr, u16 addr, u16 reg)
{
struct mii_bus *bus = priv->mii_bus;
u16 data;
mutex_lock(&bus->mdio_lock);
ar8xxx_phy_mmd_prep(bus, phy_addr, addr, reg);
data = bus->read(bus, phy_addr, MII_ATH_MMD_DATA);
mutex_unlock(&bus->mdio_lock);
return data;
}
static int
ar8xxx_reg_wait(struct ar8xxx_priv *priv, u32 reg, u32 mask, u32 val,
unsigned timeout)
{
int i;
for (i = 0; i < timeout; i++) {
u32 t;
t = ar8xxx_read(priv, reg);
if ((t & mask) == val)
return 0;
usleep_range(1000, 2000);
cond_resched();
}
return -ETIMEDOUT;
}
static int
ar8xxx_mib_op(struct ar8xxx_priv *priv, u32 op)
{
unsigned mib_func = priv->chip->mib_func;
int ret;
lockdep_assert_held(&priv->mib_lock);
/* Capture the hardware statistics for all ports */
ar8xxx_rmw(priv, mib_func, AR8216_MIB_FUNC, (op << AR8216_MIB_FUNC_S));
/* Wait for the capturing to complete. */
ret = ar8xxx_reg_wait(priv, mib_func, AR8216_MIB_BUSY, 0, 10);
if (ret)
goto out;
ret = 0;
out:
return ret;
}
static int
ar8xxx_mib_capture(struct ar8xxx_priv *priv)
{
return ar8xxx_mib_op(priv, AR8216_MIB_FUNC_CAPTURE);
}
static int
ar8xxx_mib_flush(struct ar8xxx_priv *priv)
{
return ar8xxx_mib_op(priv, AR8216_MIB_FUNC_FLUSH);
}
static void
ar8xxx_mib_fetch_port_stat(struct ar8xxx_priv *priv, int port, bool flush)
{
unsigned int base;
u64 *mib_stats;
int i;
WARN_ON(port >= priv->dev.ports);
lockdep_assert_held(&priv->mib_lock);
base = priv->chip->reg_port_stats_start +
priv->chip->reg_port_stats_length * port;
mib_stats = &priv->mib_stats[port * priv->chip->num_mibs];
for (i = 0; i < priv->chip->num_mibs; i++) {
const struct ar8xxx_mib_desc *mib;
u64 t;
mib = &priv->chip->mib_decs[i];
if (mib->type > priv->mib_type)
continue;
t = ar8xxx_read(priv, base + mib->offset);
if (mib->size == 2) {
u64 hi;
hi = ar8xxx_read(priv, base + mib->offset + 4);
t |= hi << 32;
}
if (flush)
mib_stats[i] = 0;
else
mib_stats[i] += t;
cond_resched();
}
}
static void
ar8216_read_port_link(struct ar8xxx_priv *priv, int port,
struct switch_port_link *link)
{
u32 status;
u32 speed;
memset(link, '\0', sizeof(*link));
status = priv->chip->read_port_status(priv, port);
link->aneg = !!(status & AR8216_PORT_STATUS_LINK_AUTO);
if (link->aneg) {
link->link = !!(status & AR8216_PORT_STATUS_LINK_UP);
} else {
link->link = true;
if (priv->get_port_link) {
int err;
err = priv->get_port_link(port);
if (err >= 0)
link->link = !!err;
}
}
if (!link->link)
return;
link->duplex = !!(status & AR8216_PORT_STATUS_DUPLEX);
link->tx_flow = !!(status & AR8216_PORT_STATUS_TXFLOW);
link->rx_flow = !!(status & AR8216_PORT_STATUS_RXFLOW);
if (link->aneg && link->duplex && priv->chip->read_port_eee_status)
link->eee = priv->chip->read_port_eee_status(priv, port);
speed = (status & AR8216_PORT_STATUS_SPEED) >>
AR8216_PORT_STATUS_SPEED_S;
switch (speed) {
case AR8216_PORT_SPEED_10M:
link->speed = SWITCH_PORT_SPEED_10;
break;
case AR8216_PORT_SPEED_100M:
link->speed = SWITCH_PORT_SPEED_100;
break;
case AR8216_PORT_SPEED_1000M:
link->speed = SWITCH_PORT_SPEED_1000;
break;
default:
link->speed = SWITCH_PORT_SPEED_UNKNOWN;
break;
}
}
static struct sk_buff *
ar8216_mangle_tx(struct net_device *dev, struct sk_buff *skb)
{
struct ar8xxx_priv *priv = dev->phy_ptr;
unsigned char *buf;
if (unlikely(!priv))
goto error;
if (!priv->vlan)
goto send;
if (unlikely(skb_headroom(skb) < 2)) {
if (pskb_expand_head(skb, 2, 0, GFP_ATOMIC) < 0)
goto error;
}
buf = skb_push(skb, 2);
buf[0] = 0x10;
buf[1] = 0x80;
send:
return skb;
error:
dev_kfree_skb_any(skb);
return NULL;
}
static void
ar8216_mangle_rx(struct net_device *dev, struct sk_buff *skb)
{
struct ar8xxx_priv *priv;
unsigned char *buf;
int port, vlan;
priv = dev->phy_ptr;
if (!priv)
return;
/* don't strip the header if vlan mode is disabled */
if (!priv->vlan)
return;
/* strip header, get vlan id */
buf = skb->data;
skb_pull(skb, 2);
/* check for vlan header presence */
if ((buf[12 + 2] != 0x81) || (buf[13 + 2] != 0x00))
return;
port = buf[0] & 0x7;
/* no need to fix up packets coming from a tagged source */
if (priv->vlan_tagged & (1 << port))
return;
/* lookup port vid from local table, the switch passes an invalid vlan id */
vlan = priv->vlan_id[priv->pvid[port]];
buf[14 + 2] &= 0xf0;
buf[14 + 2] |= vlan >> 8;
buf[15 + 2] = vlan & 0xff;
}
int
ar8216_wait_bit(struct ar8xxx_priv *priv, int reg, u32 mask, u32 val)
{
int timeout = 20;
u32 t = 0;
while (1) {
t = ar8xxx_read(priv, reg);
if ((t & mask) == val)
return 0;
if (timeout-- <= 0)
break;
udelay(10);
cond_resched();
}
pr_err("ar8216: timeout on reg %08x: %08x & %08x != %08x\n",
(unsigned int) reg, t, mask, val);
return -ETIMEDOUT;
}
static void
ar8216_vtu_op(struct ar8xxx_priv *priv, u32 op, u32 val)
{
if (ar8216_wait_bit(priv, AR8216_REG_VTU, AR8216_VTU_ACTIVE, 0))
return;
if ((op & AR8216_VTU_OP) == AR8216_VTU_OP_LOAD) {
val &= AR8216_VTUDATA_MEMBER;
val |= AR8216_VTUDATA_VALID;
ar8xxx_write(priv, AR8216_REG_VTU_DATA, val);
}
op |= AR8216_VTU_ACTIVE;
ar8xxx_write(priv, AR8216_REG_VTU, op);
}
static void
ar8216_vtu_flush(struct ar8xxx_priv *priv)
{
ar8216_vtu_op(priv, AR8216_VTU_OP_FLUSH, 0);
}
static void
ar8216_vtu_load_vlan(struct ar8xxx_priv *priv, u32 vid, u32 port_mask)
{
u32 op;
op = AR8216_VTU_OP_LOAD | (vid << AR8216_VTU_VID_S);
ar8216_vtu_op(priv, op, port_mask);
}
static int
ar8216_atu_flush(struct ar8xxx_priv *priv)
{
int ret;
ret = ar8216_wait_bit(priv, AR8216_REG_ATU_FUNC0, AR8216_ATU_ACTIVE, 0);
if (!ret)
ar8xxx_write(priv, AR8216_REG_ATU_FUNC0, AR8216_ATU_OP_FLUSH |
AR8216_ATU_ACTIVE);
return ret;
}
static int
ar8216_atu_flush_port(struct ar8xxx_priv *priv, int port)
{
u32 t;
int ret;
ret = ar8216_wait_bit(priv, AR8216_REG_ATU_FUNC0, AR8216_ATU_ACTIVE, 0);
if (!ret) {
t = (port << AR8216_ATU_PORT_NUM_S) | AR8216_ATU_OP_FLUSH_PORT;
t |= AR8216_ATU_ACTIVE;
ar8xxx_write(priv, AR8216_REG_ATU_FUNC0, t);
}
return ret;
}
static u32
ar8216_read_port_status(struct ar8xxx_priv *priv, int port)
{
return ar8xxx_read(priv, AR8216_REG_PORT_STATUS(port));
}
static void
__ar8216_setup_port(struct ar8xxx_priv *priv, int port, u32 members,
bool ath_hdr_en)
{
u32 header;
u32 egress, ingress;
u32 pvid;
if (priv->vlan) {
pvid = priv->vlan_id[priv->pvid[port]];
if (priv->vlan_tagged & (1 << port))
egress = AR8216_OUT_ADD_VLAN;
else
egress = AR8216_OUT_STRIP_VLAN;
ingress = AR8216_IN_SECURE;
} else {
pvid = port;
egress = AR8216_OUT_KEEP;
ingress = AR8216_IN_PORT_ONLY;
}
header = ath_hdr_en ? AR8216_PORT_CTRL_HEADER : 0;
ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(port),
AR8216_PORT_CTRL_LEARN | AR8216_PORT_CTRL_VLAN_MODE |
AR8216_PORT_CTRL_SINGLE_VLAN | AR8216_PORT_CTRL_STATE |
AR8216_PORT_CTRL_HEADER | AR8216_PORT_CTRL_LEARN_LOCK,
AR8216_PORT_CTRL_LEARN | header |
(egress << AR8216_PORT_CTRL_VLAN_MODE_S) |
(AR8216_PORT_STATE_FORWARD << AR8216_PORT_CTRL_STATE_S));
ar8xxx_rmw(priv, AR8216_REG_PORT_VLAN(port),
AR8216_PORT_VLAN_DEST_PORTS | AR8216_PORT_VLAN_MODE |
AR8216_PORT_VLAN_DEFAULT_ID,
(members << AR8216_PORT_VLAN_DEST_PORTS_S) |
(ingress << AR8216_PORT_VLAN_MODE_S) |
(pvid << AR8216_PORT_VLAN_DEFAULT_ID_S));
}
static void
ar8216_setup_port(struct ar8xxx_priv *priv, int port, u32 members)
{
return __ar8216_setup_port(priv, port, members,
chip_is_ar8216(priv) && priv->vlan &&
port == AR8216_PORT_CPU);
}
static int
ar8216_hw_init(struct ar8xxx_priv *priv)
{
if (priv->initialized)
return 0;
ar8xxx_write(priv, AR8216_REG_CTRL, AR8216_CTRL_RESET);
ar8xxx_reg_wait(priv, AR8216_REG_CTRL, AR8216_CTRL_RESET, 0, 1000);
ar8xxx_phy_init(priv);
priv->initialized = true;
return 0;
}
static void
ar8216_init_globals(struct ar8xxx_priv *priv)
{
/* standard atheros magic */
ar8xxx_write(priv, 0x38, 0xc000050e);
ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,
AR8216_GCTRL_MTU, 1518 + 8 + 2);
}
static void
__ar8216_init_port(struct ar8xxx_priv *priv, int port,
bool cpu_ge, bool flow_en)
{
/* Enable port learning and tx */
ar8xxx_write(priv, AR8216_REG_PORT_CTRL(port),
AR8216_PORT_CTRL_LEARN |
(4 << AR8216_PORT_CTRL_STATE_S));
ar8xxx_write(priv, AR8216_REG_PORT_VLAN(port), 0);
if (port == AR8216_PORT_CPU) {
ar8xxx_write(priv, AR8216_REG_PORT_STATUS(port),
AR8216_PORT_STATUS_LINK_UP |
(cpu_ge ? AR8216_PORT_SPEED_1000M : AR8216_PORT_SPEED_100M) |
AR8216_PORT_STATUS_TXMAC |
AR8216_PORT_STATUS_RXMAC |
(flow_en ? AR8216_PORT_STATUS_RXFLOW : 0) |
(flow_en ? AR8216_PORT_STATUS_TXFLOW : 0) |
AR8216_PORT_STATUS_DUPLEX);
} else {
ar8xxx_write(priv, AR8216_REG_PORT_STATUS(port),
AR8216_PORT_STATUS_LINK_AUTO);
}
}
static void
ar8216_init_port(struct ar8xxx_priv *priv, int port)
{
__ar8216_init_port(priv, port, ar8xxx_has_gige(priv),
chip_is_ar8316(priv));
}
static void
ar8216_wait_atu_ready(struct ar8xxx_priv *priv, u16 r2, u16 r1)
{
int timeout = 20;
while (ar8xxx_mii_read32(priv, r2, r1) & AR8216_ATU_ACTIVE && --timeout) {
udelay(10);
cond_resched();
}
if (!timeout)
pr_err("ar8216: timeout waiting for atu to become ready\n");
}
static void ar8216_get_arl_entry(struct ar8xxx_priv *priv,
struct arl_entry *a, u32 *status, enum arl_op op)
{
struct mii_bus *bus = priv->mii_bus;
u16 r2, page;
u16 r1_func0, r1_func1, r1_func2;
u32 t, val0, val1, val2;
split_addr(AR8216_REG_ATU_FUNC0, &r1_func0, &r2, &page);
r2 |= 0x10;
r1_func1 = (AR8216_REG_ATU_FUNC1 >> 1) & 0x1e;
r1_func2 = (AR8216_REG_ATU_FUNC2 >> 1) & 0x1e;
switch (op) {
case AR8XXX_ARL_INITIALIZE:
/* all ATU registers are on the same page
* therefore set page only once
*/
bus->write(bus, 0x18, 0, page);
wait_for_page_switch();
ar8216_wait_atu_ready(priv, r2, r1_func0);
ar8xxx_mii_write32(priv, r2, r1_func0, AR8216_ATU_OP_GET_NEXT);
ar8xxx_mii_write32(priv, r2, r1_func1, 0);
ar8xxx_mii_write32(priv, r2, r1_func2, 0);
break;
case AR8XXX_ARL_GET_NEXT:
t = ar8xxx_mii_read32(priv, r2, r1_func0);
t |= AR8216_ATU_ACTIVE;
ar8xxx_mii_write32(priv, r2, r1_func0, t);
ar8216_wait_atu_ready(priv, r2, r1_func0);
val0 = ar8xxx_mii_read32(priv, r2, r1_func0);
val1 = ar8xxx_mii_read32(priv, r2, r1_func1);
val2 = ar8xxx_mii_read32(priv, r2, r1_func2);
*status = (val2 & AR8216_ATU_STATUS) >> AR8216_ATU_STATUS_S;
if (!*status)
break;
a->portmap = (val2 & AR8216_ATU_PORTS) >> AR8216_ATU_PORTS_S;
a->mac[0] = (val0 & AR8216_ATU_ADDR5) >> AR8216_ATU_ADDR5_S;
a->mac[1] = (val0 & AR8216_ATU_ADDR4) >> AR8216_ATU_ADDR4_S;
a->mac[2] = (val1 & AR8216_ATU_ADDR3) >> AR8216_ATU_ADDR3_S;
a->mac[3] = (val1 & AR8216_ATU_ADDR2) >> AR8216_ATU_ADDR2_S;
a->mac[4] = (val1 & AR8216_ATU_ADDR1) >> AR8216_ATU_ADDR1_S;
a->mac[5] = (val1 & AR8216_ATU_ADDR0) >> AR8216_ATU_ADDR0_S;
break;
}
}
static int
ar8216_phy_read(struct ar8xxx_priv *priv, int addr, int regnum)
{
u32 t, val = 0xffff;
int err;
if (addr >= AR8216_NUM_PORTS)
return 0xffff;
t = (regnum << AR8216_MDIO_CTRL_REG_ADDR_S) |
(addr << AR8216_MDIO_CTRL_PHY_ADDR_S) |
AR8216_MDIO_CTRL_MASTER_EN |
AR8216_MDIO_CTRL_BUSY |
AR8216_MDIO_CTRL_CMD_READ;
ar8xxx_write(priv, AR8216_REG_MDIO_CTRL, t);
err = ar8xxx_reg_wait(priv, AR8216_REG_MDIO_CTRL,
AR8216_MDIO_CTRL_BUSY, 0, 5);
if (!err)
val = ar8xxx_read(priv, AR8216_REG_MDIO_CTRL);
return val & AR8216_MDIO_CTRL_DATA_M;
}
static int
ar8216_phy_write(struct ar8xxx_priv *priv, int addr, int regnum, u16 val)
{
u32 t;
int ret;
if (addr >= AR8216_NUM_PORTS)
return -EINVAL;
t = (addr << AR8216_MDIO_CTRL_PHY_ADDR_S) |
(regnum << AR8216_MDIO_CTRL_REG_ADDR_S) |
AR8216_MDIO_CTRL_MASTER_EN |
AR8216_MDIO_CTRL_BUSY |
AR8216_MDIO_CTRL_CMD_WRITE |
val;
ar8xxx_write(priv, AR8216_REG_MDIO_CTRL, t);
ret = ar8xxx_reg_wait(priv, AR8216_REG_MDIO_CTRL,
AR8216_MDIO_CTRL_BUSY, 0, 5);
return ret;
}
static int
ar8229_hw_init(struct ar8xxx_priv *priv)
{
int phy_if_mode;
if (priv->initialized)
return 0;
ar8xxx_write(priv, AR8216_REG_CTRL, AR8216_CTRL_RESET);
ar8xxx_reg_wait(priv, AR8216_REG_CTRL, AR8216_CTRL_RESET, 0, 1000);
phy_if_mode = of_get_phy_mode(priv->pdev->of_node);
if (phy_if_mode == PHY_INTERFACE_MODE_GMII) {
ar8xxx_write(priv, AR8229_REG_OPER_MODE0,
AR8229_OPER_MODE0_MAC_GMII_EN);
} else if (phy_if_mode == PHY_INTERFACE_MODE_MII) {
ar8xxx_write(priv, AR8229_REG_OPER_MODE0,
AR8229_OPER_MODE0_PHY_MII_EN);
} else {
pr_err("ar8229: unsupported mii mode\n");
return -EINVAL;
}
if (priv->port4_phy) {
ar8xxx_write(priv, AR8229_REG_OPER_MODE1,
AR8229_REG_OPER_MODE1_PHY4_MII_EN);
/* disable port5 to prevent mii conflict */
ar8xxx_write(priv, AR8216_REG_PORT_STATUS(5), 0);
}
ar8xxx_phy_init(priv);
priv->initialized = true;
return 0;
}
static void
ar8229_init_globals(struct ar8xxx_priv *priv)
{
/* Enable CPU port, and disable mirror port */
ar8xxx_write(priv, AR8216_REG_GLOBAL_CPUPORT,
AR8216_GLOBAL_CPUPORT_EN |
(15 << AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S));
/* Setup TAG priority mapping */
ar8xxx_write(priv, AR8216_REG_TAG_PRIORITY, 0xfa50);
/* Enable aging, MAC replacing */
ar8xxx_write(priv, AR8216_REG_ATU_CTRL,
0x2b /* 5 min age time */ |
AR8216_ATU_CTRL_AGE_EN |
AR8216_ATU_CTRL_LEARN_CHANGE);
/* Enable ARP frame acknowledge */
ar8xxx_reg_set(priv, AR8229_REG_QM_CTRL,
AR8229_QM_CTRL_ARP_EN);
/*
* Enable Broadcast/unknown multicast and unicast frames
* transmitted to the CPU port.
*/
ar8xxx_reg_set(priv, AR8216_REG_FLOOD_MASK,
AR8229_FLOOD_MASK_BC_DP(0) |
AR8229_FLOOD_MASK_MC_DP(0) |
AR8229_FLOOD_MASK_UC_DP(0));
/* setup MTU */
ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,
AR8236_GCTRL_MTU, AR8236_GCTRL_MTU);
/* Enable MIB counters */
ar8xxx_reg_set(priv, AR8216_REG_MIB_FUNC,
AR8236_MIB_EN);
/* setup Service TAG */
ar8xxx_rmw(priv, AR8216_REG_SERVICE_TAG, AR8216_SERVICE_TAG_M, 0);
}
static void
ar8229_init_port(struct ar8xxx_priv *priv, int port)
{
__ar8216_init_port(priv, port, true, true);
}
static int
ar7240sw_hw_init(struct ar8xxx_priv *priv)
{
if (priv->initialized)
return 0;
ar8xxx_write(priv, AR8216_REG_CTRL, AR8216_CTRL_RESET);
ar8xxx_reg_wait(priv, AR8216_REG_CTRL, AR8216_CTRL_RESET, 0, 1000);
priv->port4_phy = 1;
/* disable port5 to prevent mii conflict */
ar8xxx_write(priv, AR8216_REG_PORT_STATUS(5), 0);
ar8xxx_phy_init(priv);
priv->initialized = true;
return 0;
}
static void
ar7240sw_init_globals(struct ar8xxx_priv *priv)
{
/* Enable CPU port, and disable mirror port */
ar8xxx_write(priv, AR8216_REG_GLOBAL_CPUPORT,
AR8216_GLOBAL_CPUPORT_EN |
(15 << AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S));