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950-0714-vc4_hdmi_regs-Add-Intr2-register-block.patch
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950-0714-vc4_hdmi_regs-Add-Intr2-register-block.patch
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From 2aa3a92e409ed4ad416eceacef998f0027016a81 Mon Sep 17 00:00:00 2001
From: Dom Cobley <popcornmix@gmail.com>
Date: Thu, 7 May 2020 18:16:07 +0100
Subject: [PATCH] vc4_hdmi_regs: Add Intr2 register block
Signed-off-by: Dom Cobley <popcornmix@gmail.com>
---
arch/arm/boot/dts/bcm2711.dtsi | 14 ++++++++++----
drivers/gpu/drm/vc4/vc4_hdmi.c | 8 ++++++++
drivers/gpu/drm/vc4/vc4_hdmi.h | 2 ++
drivers/gpu/drm/vc4/vc4_hdmi_regs.h | 17 +++++++++++++++++
4 files changed, 37 insertions(+), 4 deletions(-)
--- a/arch/arm/boot/dts/bcm2711.dtsi
+++ b/arch/arm/boot/dts/bcm2711.dtsi
@@ -316,7 +316,8 @@
<0x7ef01f00 0x400>,
<0x7ef00200 0x80>,
<0x7ef04300 0x100>,
- <0x7ef20000 0x100>;
+ <0x7ef20000 0x100>,
+ <0x7ef00100 0x30>;
reg-names = "hdmi",
"dvp",
"phy",
@@ -325,13 +326,15 @@
"metadata",
"csc",
"cec",
- "hd";
+ "hd",
+ "intr2";
clocks = <&firmware_clocks 13>;
clock-names = "hdmi";
resets = <&dvp 0>;
ddc = <&ddc0>;
dmas = <&dma 10>;
dma-names = "audio-rx";
+ interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
@@ -353,7 +356,8 @@
<0x7ef06f00 0x400>,
<0x7ef00280 0x80>,
<0x7ef09300 0x100>,
- <0x7ef20000 0x100>;
+ <0x7ef20000 0x100>,
+ <0x7ef00100 0x30>;
reg-names = "hdmi",
"dvp",
"phy",
@@ -362,13 +366,15 @@
"metadata",
"csc",
"cec",
- "hd";
+ "hd",
+ "intr2";
ddc = <&ddc1>;
clocks = <&firmware_clocks 13>;
clock-names = "hdmi";
resets = <&dvp 1>;
dmas = <&dma 17>;
dma-names = "audio-rx";
+ interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
--- a/drivers/gpu/drm/vc4/vc4_hdmi.c
+++ b/drivers/gpu/drm/vc4/vc4_hdmi.c
@@ -1581,6 +1581,14 @@ static int vc5_hdmi_init_resources(struc
if (IS_ERR(vc4_hdmi->dvp_regs))
return PTR_ERR(vc4_hdmi->dvp_regs);
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "intr2");
+ if (!res)
+ return -ENODEV;
+
+ vc4_hdmi->intr2_regs = devm_ioremap(dev, res->start, resource_size(res));
+ if (IS_ERR(vc4_hdmi->intr2_regs))
+ return PTR_ERR(vc4_hdmi->intr2_regs);
+
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phy");
if (!res)
return -ENODEV;
--- a/drivers/gpu/drm/vc4/vc4_hdmi.h
+++ b/drivers/gpu/drm/vc4/vc4_hdmi.h
@@ -140,6 +140,8 @@ struct vc4_hdmi {
void __iomem *ram_regs;
/* VC5 Only */
void __iomem *rm_regs;
+ /* VC5 Only */
+ void __iomem *intr2_regs;
int hpd_gpio;
bool hpd_active_low;
--- a/drivers/gpu/drm/vc4/vc4_hdmi_regs.h
+++ b/drivers/gpu/drm/vc4/vc4_hdmi_regs.h
@@ -24,6 +24,7 @@ enum vc4_hdmi_regs {
VC5_PHY,
VC5_RAM,
VC5_RM,
+ VC5_INTR2,
};
enum vc4_hdmi_field {
@@ -148,6 +149,7 @@ struct vc4_hdmi_register {
#define VC5_CEC_REG(reg, offset) _VC4_REG(VC5_CEC, reg, offset)
#define VC5_CSC_REG(reg, offset) _VC4_REG(VC5_CSC, reg, offset)
#define VC5_DVP_REG(reg, offset) _VC4_REG(VC5_DVP, reg, offset)
+#define VC5_INTR2_REG(reg, offset) _VC4_REG(VC5_INTR2, reg, offset)
#define VC5_PHY_REG(reg, offset) _VC4_REG(VC5_PHY, reg, offset)
#define VC5_RAM_REG(reg, offset) _VC4_REG(VC5_RAM, reg, offset)
#define VC5_RM_REG(reg, offset) _VC4_REG(VC5_RM, reg, offset)
@@ -280,6 +282,12 @@ static const struct vc4_hdmi_register vc
VC5_CEC_REG(HDMI_CEC_RX_DATA_2, 0x03c),
VC5_CEC_REG(HDMI_CEC_RX_DATA_3, 0x040),
VC5_CEC_REG(HDMI_CEC_RX_DATA_4, 0x044),
+ VC5_INTR2_REG(HDMI_CEC_CPU_STATUS, 0x0000),
+ VC5_INTR2_REG(HDMI_CEC_CPU_SET, 0x0004),
+ VC5_INTR2_REG(HDMI_CEC_CPU_CLEAR, 0x0008),
+ VC5_INTR2_REG(HDMI_CEC_CPU_MASK_STATUS, 0x000c),
+ VC5_INTR2_REG(HDMI_CEC_CPU_MASK_SET, 0x0010),
+ VC5_INTR2_REG(HDMI_CEC_CPU_MASK_CLEAR, 0x0014),
VC5_CSC_REG(HDMI_CSC_CTL, 0x000),
VC5_CSC_REG(HDMI_CSC_12_11, 0x004),
@@ -356,6 +364,12 @@ static const struct vc4_hdmi_register vc
VC5_CEC_REG(HDMI_CEC_RX_DATA_2, 0x03c),
VC5_CEC_REG(HDMI_CEC_RX_DATA_3, 0x040),
VC5_CEC_REG(HDMI_CEC_RX_DATA_4, 0x044),
+ VC5_INTR2_REG(HDMI_CEC_CPU_STATUS, 0x0000),
+ VC5_INTR2_REG(HDMI_CEC_CPU_SET, 0x0004),
+ VC5_INTR2_REG(HDMI_CEC_CPU_CLEAR, 0x0008),
+ VC5_INTR2_REG(HDMI_CEC_CPU_MASK_STATUS, 0x000c),
+ VC5_INTR2_REG(HDMI_CEC_CPU_MASK_SET, 0x0010),
+ VC5_INTR2_REG(HDMI_CEC_CPU_MASK_CLEAR, 0x0014),
VC5_CSC_REG(HDMI_CSC_CTL, 0x000),
VC5_CSC_REG(HDMI_CSC_12_11, 0x004),
@@ -386,6 +400,9 @@ void __iomem *__vc4_hdmi_get_field_base(
case VC5_DVP:
return hdmi->dvp_regs;
+ case VC5_INTR2:
+ return hdmi->intr2_regs;
+
case VC5_PHY:
return hdmi->phy_regs;