mt7620a_dlink_dwr-961-a1.dts

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * D-Link DWR-961 A1 Board Description
 * Copyright 2022 Pawel Dembicki <paweldembicki@gmail.com>
 */
#include "mt7620a_dlink_dwr-96x.dtsi"

/ {
	compatible = "dlink,dwr-961-a1", "ralink,mt7620a-soc";
	model = "D-Link DWR-961 A1";

	leds {
		hidden-1 { /* hidden next to wlan5g led */
			label = "green:hidden-1";
			gpios = <&gpio0 13 GPIO_ACTIVE_LOW>;
		};

		hidden-2 { /* hidden next to sms led*/
			label = "green:hidden-2";
			gpios = <&gpio0 14 GPIO_ACTIVE_LOW>;
		};
	};
};

&ethernet {
	pinctrl-names = "default";
	pinctrl-0 = <&rgmii1_pins &mdio_pins>;

	port@5 {
		status = "okay";
		phy-mode = "rgmii";
		mediatek,fixed-link = <1000 1 1 1>;
	};

	mdio-bus {
		status = "okay";

		ethernet-phy@0 {
			reg = <0>;
			phy-mode = "rgmii";
			qca,ar8327-initvals = <
				0x04 0x87300000 /* PORT0 PAD MODE CTRL */
				0x0c 0x00000000 /* PORT6 PAD MODE CTRL */
				0x7c 0x0000007e /* PORT0_STATUS */
				0x80 0x00001200 /* PORT1_STATUS */
				0x84 0x00001200 /* PORT2_STATUS */
				0x88 0x00001200 /* PORT3_STATUS */
				0x8c 0x00001200 /* PORT4_STATUS */
				0x90 0x00001200 /* PORT5_STATUS */
				0x94 0x00000000 /* PORT6_STATUS */
			>;
		};
	};
};

&gsw {
	mediatek,ephy-base = /bits/ 8 <8>;
};

&wifi {
	mediatek,mtd-eeprom = <&config 0xe29e>;
};