302-dts-0030-arm64-dts-lx2160-PCS-PHY-definitions-for-10GBase-KR-.patch

From c1619d9de2da093a585426e9cef353ca1789236d Mon Sep 17 00:00:00 2001
From: Florinel Iordache <florinel.iordache@nxp.com>
Date: Mon, 5 Nov 2018 17:02:19 +0200
Subject: [PATCH] arm64: dts: lx2160: PCS PHY definitions for 10GBase-KR and
 40GBase-KR backplane modes

Signed-off-by: Florinel Iordache <florinel.iordache@nxp.com>
---
 arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts | 40 +++++++++++++++++++++++
 1 file changed, 40 insertions(+)

--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts
@@ -162,3 +162,43 @@
 &usb1 {
 	status = "okay";
 };
+
+&pcs_mdio1 {
+	pcs_phy1: ethernet-phy@0 {
+		compatible = "ethernet-phy-ieee802.3-c45";
+		backplane-mode = "40gbase-kr";
+		reg = <0x0>;
+		fsl,lane-handle = <&serdes1>;
+		fsl,lane-reg = <0xF00 0xE00 0xD00 0xC00>; /* lanes H, G, F, E */
+	};
+};
+
+&pcs_mdio2 {
+	pcs_phy2: ethernet-phy@0 {
+		compatible = "ethernet-phy-ieee802.3-c45";
+		backplane-mode = "40gbase-kr";
+		reg = <0x0>;
+		fsl,lane-handle = <&serdes1>;
+		fsl,lane-reg = <0xB00 0xA00 0x900 0x800>; /* lanes D, C, B, A */
+	};
+};
+
+&pcs_mdio3 {
+	pcs_phy3: ethernet-phy@0 {
+		compatible = "ethernet-phy-ieee802.3-c45";
+		backplane-mode = "10gbase-kr";
+		reg = <0x0>;
+		fsl,lane-handle = <&serdes1>;
+		fsl,lane-reg = <0xF00 0x100>; /* lane H */
+	};
+};
+
+&pcs_mdio4 {
+	pcs_phy4: ethernet-phy@0 {
+		compatible = "ethernet-phy-ieee802.3-c45";
+		backplane-mode = "10gbase-kr";
+		reg = <0x0>;
+		fsl,lane-handle = <&serdes1>;
+		fsl,lane-reg = <0xE00 0x100>; /* lane G */
+	};
+};