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rtl838x_eth.c
2205 lines (1878 loc) · 62.5 KB
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rtl838x_eth.c
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// SPDX-License-Identifier: GPL-2.0-only
/*
* linux/drivers/net/ethernet/rtl838x_eth.c
* Copyright (C) 2020 B. Koblitz
*/
#include <linux/dma-mapping.h>
#include <linux/etherdevice.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/platform_device.h>
#include <linux/sched.h>
#include <linux/slab.h>
#include <linux/of.h>
#include <linux/of_net.h>
#include <linux/of_mdio.h>
#include <linux/module.h>
#include <linux/phylink.h>
#include <linux/pkt_sched.h>
#include <net/dsa.h>
#include <net/switchdev.h>
#include <asm/cacheflush.h>
#include <asm/mach-rtl838x/mach-rtl83xx.h>
#include "rtl838x_eth.h"
extern struct rtl83xx_soc_info soc_info;
/*
* Maximum number of RX rings is 8 on RTL83XX and 32 on the 93XX
* The ring is assigned by switch based on packet/port priortity
* Maximum number of TX rings is 2, Ring 2 being the high priority
* ring on the RTL93xx SoCs. MAX_RING_SIZE * RING_BUFFER gives
* the memory used for the ring buffer.
*/
#define MAX_RXRINGS 32
#define MAX_RXLEN 100
#define MAX_ENTRIES (200 * 8)
#define TXRINGS 2
// BUG: TXRINGLEN can be 160
#define TXRINGLEN 16
#define NOTIFY_EVENTS 10
#define NOTIFY_BLOCKS 10
#define TX_EN 0x8
#define RX_EN 0x4
#define TX_EN_93XX 0x20
#define RX_EN_93XX 0x10
#define TX_DO 0x2
#define WRAP 0x2
#define RING_BUFFER 1600
#define RTL838X_STORM_CTRL_PORT_BC_EXCEED (0x470C)
#define RTL838X_STORM_CTRL_PORT_MC_EXCEED (0x4710)
#define RTL838X_STORM_CTRL_PORT_UC_EXCEED (0x4714)
#define RTL838X_ATK_PRVNT_STS (0x5B1C)
struct p_hdr {
uint8_t *buf;
uint16_t reserved;
uint16_t size; /* buffer size */
uint16_t offset;
uint16_t len; /* pkt len */
uint16_t cpu_tag[10];
} __packed __aligned(1);
struct n_event {
uint32_t type:2;
uint32_t fidVid:12;
uint64_t mac:48;
uint32_t slp:6;
uint32_t valid:1;
uint32_t reserved:27;
} __packed __aligned(1);
struct ring_b {
uint32_t rx_r[MAX_RXRINGS][MAX_RXLEN];
uint32_t tx_r[TXRINGS][TXRINGLEN];
struct p_hdr rx_header[MAX_RXRINGS][MAX_RXLEN];
struct p_hdr tx_header[TXRINGS][TXRINGLEN];
uint32_t c_rx[MAX_RXRINGS];
uint32_t c_tx[TXRINGS];
uint8_t tx_space[TXRINGS * TXRINGLEN * RING_BUFFER];
uint8_t *rx_space;
};
struct notify_block {
struct n_event events[NOTIFY_EVENTS];
};
struct notify_b {
struct notify_block blocks[NOTIFY_BLOCKS];
u32 reserved1[8];
u32 ring[NOTIFY_BLOCKS];
u32 reserved2[8];
};
void rtl838x_create_tx_header(struct p_hdr *h, int dest_port, int prio)
{
prio &= 0x7;
if (dest_port > 0) {
// cpu_tag[0] is reserved on the RTL83XX SoCs
h->cpu_tag[1] = 0x0400;
h->cpu_tag[2] = 0x0200;
h->cpu_tag[3] = 0x0000;
h->cpu_tag[4] = BIT(dest_port) >> 16;
h->cpu_tag[5] = BIT(dest_port) & 0xffff;
// Set internal priority and AS_PRIO
if (prio >= 0)
h->cpu_tag[2] |= (prio | 0x8) << 12;
}
}
void rtl839x_create_tx_header(struct p_hdr *h, int dest_port, int prio)
{
prio &= 0x7;
if (dest_port > 0) {
// cpu_tag[0] is reserved on the RTL83XX SoCs
h->cpu_tag[1] = 0x0100;
h->cpu_tag[2] = h->cpu_tag[3] = h->cpu_tag[4] = h->cpu_tag[5] = 0;
if (dest_port >= 32) {
dest_port -= 32;
h->cpu_tag[2] = BIT(dest_port) >> 16;
h->cpu_tag[3] = BIT(dest_port) & 0xffff;
} else {
h->cpu_tag[4] = BIT(dest_port) >> 16;
h->cpu_tag[5] = BIT(dest_port) & 0xffff;
}
h->cpu_tag[6] |= BIT(21); // Enable destination port mask use
// Set internal priority and AS_PRIO
if (prio >= 0)
h->cpu_tag[1] |= prio | BIT(3);
}
}
void rtl930x_create_tx_header(struct p_hdr *h, int dest_port, int prio)
{
h->cpu_tag[0] = 0x8000;
h->cpu_tag[1] = 0; // TODO: Fill port and prio
h->cpu_tag[2] = 0;
h->cpu_tag[3] = 0;
h->cpu_tag[4] = 0;
h->cpu_tag[5] = 0;
h->cpu_tag[6] = 0;
h->cpu_tag[7] = 0xffff;
}
void rtl931x_create_tx_header(struct p_hdr *h, int dest_port, int prio)
{
h->cpu_tag[0] = 0x8000;
h->cpu_tag[1] = 0; // TODO: Fill port and prio
h->cpu_tag[2] = 0;
h->cpu_tag[3] = 0;
h->cpu_tag[4] = 0;
h->cpu_tag[5] = 0;
h->cpu_tag[6] = 0;
h->cpu_tag[7] = 0xffff;
}
struct rtl838x_rx_q {
int id;
struct rtl838x_eth_priv *priv;
struct napi_struct napi;
};
struct rtl838x_eth_priv {
struct net_device *netdev;
struct platform_device *pdev;
void *membase;
spinlock_t lock;
struct mii_bus *mii_bus;
struct rtl838x_rx_q rx_qs[MAX_RXRINGS];
struct phylink *phylink;
struct phylink_config phylink_config;
u16 id;
u16 family_id;
const struct rtl838x_reg *r;
u8 cpu_port;
u32 lastEvent;
u16 rxrings;
u16 rxringlen;
};
extern int rtl838x_phy_init(struct rtl838x_eth_priv *priv);
extern int rtl838x_read_sds_phy(int phy_addr, int phy_reg);
extern int rtl839x_read_sds_phy(int phy_addr, int phy_reg);
extern int rtl839x_write_sds_phy(int phy_addr, int phy_reg, u16 v);
extern int rtl930x_read_sds_phy(int phy_addr, int page, int phy_reg);
extern int rtl930x_write_sds_phy(int phy_addr, int page, int phy_reg, u16 v);
extern int rtl930x_read_mmd_phy(u32 port, u32 devnum, u32 regnum, u32 *val);
extern int rtl930x_write_mmd_phy(u32 port, u32 devnum, u32 regnum, u32 val);
/*
* On the RTL93XX, the RTL93XX_DMA_IF_RX_RING_CNTR track the fill level of
* the rings. Writing x into these registers substracts x from its content.
* When the content reaches the ring size, the ASIC no longer adds
* packets to this receive queue.
*/
void rtl838x_update_cntr(int r, int released)
{
// This feature is not available on RTL838x SoCs
}
void rtl839x_update_cntr(int r, int released)
{
// This feature is not available on RTL839x SoCs
}
void rtl930x_update_cntr(int r, int released)
{
int pos = (r % 3) * 10;
u32 reg = RTL930X_DMA_IF_RX_RING_CNTR + ((r / 3) << 2);
u32 v = sw_r32(reg);
v = (v >> pos) & 0x3ff;
pr_debug("RX: Work done %d, old value: %d, pos %d, reg %04x\n", released, v, pos, reg);
sw_w32_mask(0x3ff << pos, released << pos, reg);
sw_w32(v, reg);
}
void rtl931x_update_cntr(int r, int released)
{
int pos = (r % 3) * 10;
u32 reg = RTL931X_DMA_IF_RX_RING_CNTR + ((r / 3) << 2);
sw_w32_mask(0x3ff << pos, released << pos, reg);
}
struct dsa_tag {
u8 reason;
u8 queue;
u16 port;
u8 l2_offloaded;
u8 prio;
bool crc_error;
};
bool rtl838x_decode_tag(struct p_hdr *h, struct dsa_tag *t)
{
t->reason = h->cpu_tag[3] & 0xf;
t->queue = (h->cpu_tag[0] & 0xe0) >> 5;
t->port = h->cpu_tag[1] & 0x1f;
t->crc_error = t->reason == 13;
pr_debug("Reason: %d\n", t->reason);
if (t->reason != 4) // NIC_RX_REASON_SPECIAL_TRAP
t->l2_offloaded = 1;
else
t->l2_offloaded = 0;
return t->l2_offloaded;
}
bool rtl839x_decode_tag(struct p_hdr *h, struct dsa_tag *t)
{
t->reason = h->cpu_tag[4] & 0x1f;
t->queue = (h->cpu_tag[3] & 0xe000) >> 13;
t->port = h->cpu_tag[1] & 0x3f;
t->crc_error = h->cpu_tag[3] & BIT(2);
pr_debug("Reason: %d\n", t->reason);
if ((t->reason != 7) && (t->reason != 8)) // NIC_RX_REASON_RMA_USR
t->l2_offloaded = 1;
else
t->l2_offloaded = 0;
return t->l2_offloaded;
}
bool rtl930x_decode_tag(struct p_hdr *h, struct dsa_tag *t)
{
t->reason = h->cpu_tag[7] & 0x3f;
t->queue = (h->cpu_tag[2] >> 11) & 0x1f;
t->port = (h->cpu_tag[0] >> 8) & 0x1f;
t->crc_error = h->cpu_tag[1] & BIT(6);
pr_debug("Reason %d, port %d, queue %d\n", t->reason, t->port, t->queue);
if (t->reason >= 19 && t->reason <= 27)
t->l2_offloaded = 0;
else
t->l2_offloaded = 1;
return t->l2_offloaded;
}
bool rtl931x_decode_tag(struct p_hdr *h, struct dsa_tag *t)
{
t->reason = h->cpu_tag[7] & 0x3f;
t->queue = (h->cpu_tag[2] >> 11) & 0x1f;
t->port = (h->cpu_tag[0] >> 8) & 0x3f;
t->crc_error = h->cpu_tag[1] & BIT(6);
pr_debug("Reason %d, port %d, queue %d\n", t->reason, t->port, t->queue);
if (t->reason >= 19 && t->reason <= 27)
t->l2_offloaded = 0;
else
t->l2_offloaded = 1;
return t->l2_offloaded;
}
/*
* Discard the RX ring-buffers, called as part of the net-ISR
* when the buffer runs over
* Caller needs to hold priv->lock
*/
static void rtl838x_rb_cleanup(struct rtl838x_eth_priv *priv, int status)
{
int r;
u32 *last;
struct p_hdr *h;
struct ring_b *ring = priv->membase;
for (r = 0; r < priv->rxrings; r++) {
pr_debug("In %s working on r: %d\n", __func__, r);
last = (u32 *)KSEG1ADDR(sw_r32(priv->r->dma_if_rx_cur + r * 4));
do {
if ((ring->rx_r[r][ring->c_rx[r]] & 0x1))
break;
pr_debug("Got something: %d\n", ring->c_rx[r]);
h = &ring->rx_header[r][ring->c_rx[r]];
memset(h, 0, sizeof(struct p_hdr));
h->buf = (u8 *)KSEG1ADDR(ring->rx_space
+ r * priv->rxringlen * RING_BUFFER
+ ring->c_rx[r] * RING_BUFFER);
h->size = RING_BUFFER;
/* make sure the header is visible to the ASIC */
mb();
ring->rx_r[r][ring->c_rx[r]] = KSEG1ADDR(h) | 0x1
| (ring->c_rx[r] == (priv->rxringlen - 1) ? WRAP : 0x1);
ring->c_rx[r] = (ring->c_rx[r] + 1) % priv->rxringlen;
} while (&ring->rx_r[r][ring->c_rx[r]] != last);
}
}
struct fdb_update_work {
struct work_struct work;
struct net_device *ndev;
u64 macs[NOTIFY_EVENTS + 1];
};
void rtl838x_fdb_sync(struct work_struct *work)
{
const struct fdb_update_work *uw =
container_of(work, struct fdb_update_work, work);
struct switchdev_notifier_fdb_info info;
u8 addr[ETH_ALEN];
int i = 0;
int action;
while (uw->macs[i]) {
action = (uw->macs[i] & (1ULL << 63)) ? SWITCHDEV_FDB_ADD_TO_BRIDGE
: SWITCHDEV_FDB_DEL_TO_BRIDGE;
u64_to_ether_addr(uw->macs[i] & 0xffffffffffffULL, addr);
info.addr = &addr[0];
info.vid = 0;
info.offloaded = 1;
pr_debug("FDB entry %d: %llx, action %d\n", i, uw->macs[0], action);
call_switchdev_notifiers(action, uw->ndev, &info.info, NULL);
i++;
}
kfree(work);
}
static void rtl839x_l2_notification_handler(struct rtl838x_eth_priv *priv)
{
struct notify_b *nb = priv->membase + sizeof(struct ring_b);
u32 e = priv->lastEvent;
struct n_event *event;
int i;
u64 mac;
struct fdb_update_work *w;
while (!(nb->ring[e] & 1)) {
w = kzalloc(sizeof(*w), GFP_ATOMIC);
if (!w) {
pr_err("Out of memory: %s", __func__);
return;
}
INIT_WORK(&w->work, rtl838x_fdb_sync);
for (i = 0; i < NOTIFY_EVENTS; i++) {
event = &nb->blocks[e].events[i];
if (!event->valid)
continue;
mac = event->mac;
if (event->type)
mac |= 1ULL << 63;
w->ndev = priv->netdev;
w->macs[i] = mac;
}
/* Hand the ring entry back to the switch */
nb->ring[e] = nb->ring[e] | 1;
e = (e + 1) % NOTIFY_BLOCKS;
w->macs[i] = 0ULL;
schedule_work(&w->work);
}
priv->lastEvent = e;
}
static irqreturn_t rtl83xx_net_irq(int irq, void *dev_id)
{
struct net_device *dev = dev_id;
struct rtl838x_eth_priv *priv = netdev_priv(dev);
u32 status = sw_r32(priv->r->dma_if_intr_sts);
bool triggered = false;
u32 atk = sw_r32(RTL838X_ATK_PRVNT_STS);
int i;
u32 storm_uc = sw_r32(RTL838X_STORM_CTRL_PORT_UC_EXCEED);
u32 storm_mc = sw_r32(RTL838X_STORM_CTRL_PORT_MC_EXCEED);
u32 storm_bc = sw_r32(RTL838X_STORM_CTRL_PORT_BC_EXCEED);
pr_debug("IRQ: %08x\n", status);
if (storm_uc || storm_mc || storm_bc) {
pr_warn("Storm control UC: %08x, MC: %08x, BC: %08x\n",
storm_uc, storm_mc, storm_bc);
sw_w32(storm_uc, RTL838X_STORM_CTRL_PORT_UC_EXCEED);
sw_w32(storm_mc, RTL838X_STORM_CTRL_PORT_MC_EXCEED);
sw_w32(storm_bc, RTL838X_STORM_CTRL_PORT_BC_EXCEED);
triggered = true;
}
if (atk) {
pr_debug("Attack prevention triggered: %08x\n", atk);
sw_w32(atk, RTL838X_ATK_PRVNT_STS);
}
spin_lock(&priv->lock);
/* Ignore TX interrupt */
if ((status & 0xf0000)) {
/* Clear ISR */
sw_w32(0x000f0000, priv->r->dma_if_intr_sts);
}
/* RX interrupt */
if (status & 0x0ff00) {
/* ACK and disable RX interrupt for this ring */
sw_w32_mask(0xff00 & status, 0, priv->r->dma_if_intr_msk);
sw_w32(0x0000ff00 & status, priv->r->dma_if_intr_sts);
for (i = 0; i < priv->rxrings; i++) {
if (status & BIT(i + 8)) {
pr_debug("Scheduling queue: %d\n", i);
napi_schedule(&priv->rx_qs[i].napi);
}
}
}
/* RX buffer overrun */
if (status & 0x000ff) {
pr_info("RX buffer overrun: status %x, mask: %x\n",
status, sw_r32(priv->r->dma_if_intr_msk));
sw_w32(status, priv->r->dma_if_intr_sts);
rtl838x_rb_cleanup(priv, status & 0xff);
}
if (priv->family_id == RTL8390_FAMILY_ID && status & 0x00100000) {
sw_w32(0x00100000, priv->r->dma_if_intr_sts);
rtl839x_l2_notification_handler(priv);
}
if (priv->family_id == RTL8390_FAMILY_ID && status & 0x00200000) {
sw_w32(0x00200000, priv->r->dma_if_intr_sts);
rtl839x_l2_notification_handler(priv);
}
if (priv->family_id == RTL8390_FAMILY_ID && status & 0x00400000) {
sw_w32(0x00400000, priv->r->dma_if_intr_sts);
rtl839x_l2_notification_handler(priv);
}
spin_unlock(&priv->lock);
return IRQ_HANDLED;
}
static irqreturn_t rtl93xx_net_irq(int irq, void *dev_id)
{
struct net_device *dev = dev_id;
struct rtl838x_eth_priv *priv = netdev_priv(dev);
u32 status_rx_r = sw_r32(priv->r->dma_if_intr_rx_runout_sts);
u32 status_rx = sw_r32(priv->r->dma_if_intr_rx_done_sts);
u32 status_tx = sw_r32(priv->r->dma_if_intr_tx_done_sts);
int i;
pr_debug("In %s, status_tx: %08x, status_rx: %08x, status_rx_r: %08x\n",
__func__, status_tx, status_rx, status_rx_r);
spin_lock(&priv->lock);
/* Ignore TX interrupt */
if (status_tx) {
/* Clear ISR */
pr_debug("TX done\n");
sw_w32(status_tx, priv->r->dma_if_intr_tx_done_sts);
}
/* RX interrupt */
if (status_rx) {
pr_debug("RX IRQ\n");
/* ACK and disable RX interrupt for given rings */
sw_w32(status_rx, priv->r->dma_if_intr_rx_done_sts);
sw_w32_mask(status_rx, 0, priv->r->dma_if_intr_rx_done_msk);
for (i = 0; i < priv->rxrings; i++) {
if (status_rx & BIT(i)) {
pr_debug("Scheduling queue: %d\n", i);
napi_schedule(&priv->rx_qs[i].napi);
}
}
}
/* RX buffer overrun */
if (status_rx_r) {
pr_debug("RX buffer overrun: status %x, mask: %x\n",
status_rx_r, sw_r32(priv->r->dma_if_intr_rx_runout_msk));
sw_w32(status_rx_r, priv->r->dma_if_intr_rx_runout_sts);
rtl838x_rb_cleanup(priv, status_rx_r);
}
spin_unlock(&priv->lock);
return IRQ_HANDLED;
}
static const struct rtl838x_reg rtl838x_reg = {
.net_irq = rtl83xx_net_irq,
.mac_port_ctrl = rtl838x_mac_port_ctrl,
.dma_if_intr_sts = RTL838X_DMA_IF_INTR_STS,
.dma_if_intr_msk = RTL838X_DMA_IF_INTR_MSK,
.dma_if_ctrl = RTL838X_DMA_IF_CTRL,
.mac_force_mode_ctrl = RTL838X_MAC_FORCE_MODE_CTRL,
.dma_rx_base = RTL838X_DMA_RX_BASE,
.dma_tx_base = RTL838X_DMA_TX_BASE,
.dma_if_rx_ring_size = rtl838x_dma_if_rx_ring_size,
.dma_if_rx_ring_cntr = rtl838x_dma_if_rx_ring_cntr,
.dma_if_rx_cur = RTL838X_DMA_IF_RX_CUR,
.rst_glb_ctrl = RTL838X_RST_GLB_CTRL_0,
.get_mac_link_sts = rtl838x_get_mac_link_sts,
.get_mac_link_dup_sts = rtl838x_get_mac_link_dup_sts,
.get_mac_link_spd_sts = rtl838x_get_mac_link_spd_sts,
.get_mac_rx_pause_sts = rtl838x_get_mac_rx_pause_sts,
.get_mac_tx_pause_sts = rtl838x_get_mac_tx_pause_sts,
.mac = RTL838X_MAC,
.l2_tbl_flush_ctrl = RTL838X_L2_TBL_FLUSH_CTRL,
.update_cntr = rtl838x_update_cntr,
.create_tx_header = rtl838x_create_tx_header,
.decode_tag = rtl838x_decode_tag,
};
static const struct rtl838x_reg rtl839x_reg = {
.net_irq = rtl83xx_net_irq,
.mac_port_ctrl = rtl839x_mac_port_ctrl,
.dma_if_intr_sts = RTL839X_DMA_IF_INTR_STS,
.dma_if_intr_msk = RTL839X_DMA_IF_INTR_MSK,
.dma_if_ctrl = RTL839X_DMA_IF_CTRL,
.mac_force_mode_ctrl = RTL839X_MAC_FORCE_MODE_CTRL,
.dma_rx_base = RTL839X_DMA_RX_BASE,
.dma_tx_base = RTL839X_DMA_TX_BASE,
.dma_if_rx_ring_size = rtl839x_dma_if_rx_ring_size,
.dma_if_rx_ring_cntr = rtl839x_dma_if_rx_ring_cntr,
.dma_if_rx_cur = RTL839X_DMA_IF_RX_CUR,
.rst_glb_ctrl = RTL839X_RST_GLB_CTRL,
.get_mac_link_sts = rtl839x_get_mac_link_sts,
.get_mac_link_dup_sts = rtl839x_get_mac_link_dup_sts,
.get_mac_link_spd_sts = rtl839x_get_mac_link_spd_sts,
.get_mac_rx_pause_sts = rtl839x_get_mac_rx_pause_sts,
.get_mac_tx_pause_sts = rtl839x_get_mac_tx_pause_sts,
.mac = RTL839X_MAC,
.l2_tbl_flush_ctrl = RTL839X_L2_TBL_FLUSH_CTRL,
.update_cntr = rtl839x_update_cntr,
.create_tx_header = rtl839x_create_tx_header,
.decode_tag = rtl839x_decode_tag,
};
static const struct rtl838x_reg rtl930x_reg = {
.net_irq = rtl93xx_net_irq,
.mac_port_ctrl = rtl930x_mac_port_ctrl,
.dma_if_intr_rx_runout_sts = RTL930X_DMA_IF_INTR_RX_RUNOUT_STS,
.dma_if_intr_rx_done_sts = RTL930X_DMA_IF_INTR_RX_DONE_STS,
.dma_if_intr_tx_done_sts = RTL930X_DMA_IF_INTR_TX_DONE_STS,
.dma_if_intr_rx_runout_msk = RTL930X_DMA_IF_INTR_RX_RUNOUT_MSK,
.dma_if_intr_rx_done_msk = RTL930X_DMA_IF_INTR_RX_DONE_MSK,
.dma_if_intr_tx_done_msk = RTL930X_DMA_IF_INTR_TX_DONE_MSK,
.l2_ntfy_if_intr_sts = RTL930X_L2_NTFY_IF_INTR_STS,
.l2_ntfy_if_intr_msk = RTL930X_L2_NTFY_IF_INTR_MSK,
.dma_if_ctrl = RTL930X_DMA_IF_CTRL,
.mac_force_mode_ctrl = RTL930X_MAC_FORCE_MODE_CTRL,
.dma_rx_base = RTL930X_DMA_RX_BASE,
.dma_tx_base = RTL930X_DMA_TX_BASE,
.dma_if_rx_ring_size = rtl930x_dma_if_rx_ring_size,
.dma_if_rx_ring_cntr = rtl930x_dma_if_rx_ring_cntr,
.dma_if_rx_cur = RTL930X_DMA_IF_RX_CUR,
.rst_glb_ctrl = RTL930X_RST_GLB_CTRL_0,
.get_mac_link_sts = rtl930x_get_mac_link_sts,
.get_mac_link_dup_sts = rtl930x_get_mac_link_dup_sts,
.get_mac_link_spd_sts = rtl930x_get_mac_link_spd_sts,
.get_mac_rx_pause_sts = rtl930x_get_mac_rx_pause_sts,
.get_mac_tx_pause_sts = rtl930x_get_mac_tx_pause_sts,
.mac = RTL930X_MAC_L2_ADDR_CTRL,
.l2_tbl_flush_ctrl = RTL930X_L2_TBL_FLUSH_CTRL,
.update_cntr = rtl930x_update_cntr,
.create_tx_header = rtl930x_create_tx_header,
.decode_tag = rtl930x_decode_tag,
};
static const struct rtl838x_reg rtl931x_reg = {
.net_irq = rtl93xx_net_irq,
.mac_port_ctrl = rtl931x_mac_port_ctrl,
.dma_if_intr_rx_runout_sts = RTL931X_DMA_IF_INTR_RX_RUNOUT_STS,
.dma_if_intr_rx_done_sts = RTL931X_DMA_IF_INTR_RX_DONE_STS,
.dma_if_intr_tx_done_sts = RTL931X_DMA_IF_INTR_TX_DONE_STS,
.dma_if_intr_rx_runout_msk = RTL931X_DMA_IF_INTR_RX_RUNOUT_MSK,
.dma_if_intr_rx_done_msk = RTL931X_DMA_IF_INTR_RX_DONE_MSK,
.dma_if_intr_tx_done_msk = RTL931X_DMA_IF_INTR_TX_DONE_MSK,
.l2_ntfy_if_intr_sts = RTL931X_L2_NTFY_IF_INTR_STS,
.l2_ntfy_if_intr_msk = RTL931X_L2_NTFY_IF_INTR_MSK,
.dma_if_ctrl = RTL931X_DMA_IF_CTRL,
.mac_force_mode_ctrl = RTL931X_MAC_FORCE_MODE_CTRL,
.dma_rx_base = RTL931X_DMA_RX_BASE,
.dma_tx_base = RTL931X_DMA_TX_BASE,
.dma_if_rx_ring_size = rtl931x_dma_if_rx_ring_size,
.dma_if_rx_ring_cntr = rtl931x_dma_if_rx_ring_cntr,
.dma_if_rx_cur = RTL931X_DMA_IF_RX_CUR,
.rst_glb_ctrl = RTL931X_RST_GLB_CTRL,
.get_mac_link_sts = rtl931x_get_mac_link_sts,
.get_mac_link_dup_sts = rtl931x_get_mac_link_dup_sts,
.get_mac_link_spd_sts = rtl931x_get_mac_link_spd_sts,
.get_mac_rx_pause_sts = rtl931x_get_mac_rx_pause_sts,
.get_mac_tx_pause_sts = rtl931x_get_mac_tx_pause_sts,
.mac = RTL931X_MAC_L2_ADDR_CTRL,
.l2_tbl_flush_ctrl = RTL931X_L2_TBL_FLUSH_CTRL,
.update_cntr = rtl931x_update_cntr,
.create_tx_header = rtl931x_create_tx_header,
.decode_tag = rtl931x_decode_tag,
};
static void rtl838x_hw_reset(struct rtl838x_eth_priv *priv)
{
u32 int_saved, nbuf;
int i, pos;
pr_info("RESETTING %x, CPU_PORT %d\n", priv->family_id, priv->cpu_port);
sw_w32_mask(0x3, 0, priv->r->mac_port_ctrl(priv->cpu_port));
mdelay(100);
/* Disable and clear interrupts */
if (priv->family_id == RTL9300_FAMILY_ID || priv->family_id == RTL9310_FAMILY_ID) {
sw_w32(0x00000000, priv->r->dma_if_intr_rx_runout_msk);
sw_w32(0xffffffff, priv->r->dma_if_intr_rx_runout_sts);
sw_w32(0x00000000, priv->r->dma_if_intr_rx_done_msk);
sw_w32(0xffffffff, priv->r->dma_if_intr_rx_done_sts);
sw_w32(0x00000000, priv->r->dma_if_intr_tx_done_msk);
sw_w32(0x0000000f, priv->r->dma_if_intr_tx_done_sts);
} else {
sw_w32(0x00000000, priv->r->dma_if_intr_msk);
sw_w32(0xffffffff, priv->r->dma_if_intr_sts);
}
if (priv->family_id == RTL8390_FAMILY_ID) {
/* Preserve L2 notification and NBUF settings */
int_saved = sw_r32(priv->r->dma_if_intr_msk);
nbuf = sw_r32(RTL839X_DMA_IF_NBUF_BASE_DESC_ADDR_CTRL);
/* Disable link change interrupt on RTL839x */
sw_w32(0, RTL839X_IMR_PORT_LINK_STS_CHG);
sw_w32(0, RTL839X_IMR_PORT_LINK_STS_CHG + 4);
sw_w32(0x00000000, priv->r->dma_if_intr_msk);
sw_w32(0xffffffff, priv->r->dma_if_intr_sts);
}
/* Reset NIC */
if (priv->family_id == RTL9300_FAMILY_ID || priv->family_id == RTL9310_FAMILY_ID)
sw_w32(0x4, priv->r->rst_glb_ctrl);
else
sw_w32(0x8, priv->r->rst_glb_ctrl);
do { /* Wait for reset of NIC and Queues done */
udelay(20);
} while (sw_r32(priv->r->rst_glb_ctrl) & 0xc);
mdelay(100);
/* Setup Head of Line */
if (priv->family_id == RTL8380_FAMILY_ID)
sw_w32(0, RTL838X_DMA_IF_RX_RING_SIZE); // Disabled on RTL8380
if (priv->family_id == RTL8390_FAMILY_ID)
sw_w32(0xffffffff, RTL839X_DMA_IF_RX_RING_CNTR);
if (priv->family_id == RTL9300_FAMILY_ID) {
for (i = 0; i < priv->rxrings; i++) {
pos = (i % 3) * 10;
sw_w32_mask(0x3ff << pos, 0, priv->r->dma_if_rx_ring_size(i));
sw_w32_mask(0x3ff << pos, priv->rxringlen,
priv->r->dma_if_rx_ring_cntr(i));
}
}
/* Re-enable link change interrupt */
if (priv->family_id == RTL8390_FAMILY_ID) {
sw_w32(0xffffffff, RTL839X_ISR_PORT_LINK_STS_CHG);
sw_w32(0xffffffff, RTL839X_ISR_PORT_LINK_STS_CHG + 4);
sw_w32(0xffffffff, RTL839X_IMR_PORT_LINK_STS_CHG);
sw_w32(0xffffffff, RTL839X_IMR_PORT_LINK_STS_CHG + 4);
/* Restore notification settings: on RTL838x these bits are null */
sw_w32_mask(7 << 20, int_saved & (7 << 20), priv->r->dma_if_intr_msk);
sw_w32(nbuf, RTL839X_DMA_IF_NBUF_BASE_DESC_ADDR_CTRL);
}
}
static void rtl838x_hw_ring_setup(struct rtl838x_eth_priv *priv)
{
int i;
struct ring_b *ring = priv->membase;
for (i = 0; i < priv->rxrings; i++)
sw_w32(KSEG1ADDR(&ring->rx_r[i]), priv->r->dma_rx_base + i * 4);
for (i = 0; i < TXRINGS; i++)
sw_w32(KSEG1ADDR(&ring->tx_r[i]), priv->r->dma_tx_base + i * 4);
}
static void rtl838x_hw_en_rxtx(struct rtl838x_eth_priv *priv)
{
/* Disable Head of Line features for all RX rings */
sw_w32(0xffffffff, priv->r->dma_if_rx_ring_size(0));
/* Truncate RX buffer to 0x640 (1600) bytes, pad TX */
sw_w32(0x06400020, priv->r->dma_if_ctrl);
/* Enable RX done, RX overflow and TX done interrupts */
sw_w32(0xfffff, priv->r->dma_if_intr_msk);
/* Enable DMA, engine expects empty FCS field */
sw_w32_mask(0, RX_EN | TX_EN, priv->r->dma_if_ctrl);
/* Restart TX/RX to CPU port */
sw_w32_mask(0x0, 0x3, priv->r->mac_port_ctrl(priv->cpu_port));
/* Set Speed, duplex, flow control
* FORCE_EN | LINK_EN | NWAY_EN | DUP_SEL
* | SPD_SEL = 0b10 | FORCE_FC_EN | PHY_MASTER_SLV_MANUAL_EN
* | MEDIA_SEL
*/
sw_w32(0x6192F, priv->r->mac_force_mode_ctrl + priv->cpu_port * 4);
/* Enable CRC checks on CPU-port */
sw_w32_mask(0, BIT(3), priv->r->mac_port_ctrl(priv->cpu_port));
}
static void rtl839x_hw_en_rxtx(struct rtl838x_eth_priv *priv)
{
/* Setup CPU-Port: RX Buffer */
sw_w32(0x0000c808, priv->r->dma_if_ctrl);
/* Enable Notify, RX done, RX overflow and TX done interrupts */
sw_w32(0x007fffff, priv->r->dma_if_intr_msk); // Notify IRQ!
/* Enable DMA */
sw_w32_mask(0, RX_EN | TX_EN, priv->r->dma_if_ctrl);
/* Restart TX/RX to CPU port, enable CRC checking */
sw_w32_mask(0x0, 0x3 | BIT(3), priv->r->mac_port_ctrl(priv->cpu_port));
/* CPU port joins Lookup Miss Flooding Portmask */
// TODO: The code below should also work for the RTL838x
sw_w32(0x28000, RTL839X_TBL_ACCESS_L2_CTRL);
sw_w32_mask(0, 0x80000000, RTL839X_TBL_ACCESS_L2_DATA(0));
sw_w32(0x38000, RTL839X_TBL_ACCESS_L2_CTRL);
/* Force CPU port link up */
sw_w32_mask(0, 3, priv->r->mac_force_mode_ctrl + priv->cpu_port * 4);
}
static void rtl93xx_hw_en_rxtx(struct rtl838x_eth_priv *priv)
{
int i, pos;
u32 v;
/* Setup CPU-Port: RX Buffer truncated at 1600 Bytes */
sw_w32(0x06400040, priv->r->dma_if_ctrl);
for (i = 0; i < priv->rxrings; i++) {
pos = (i % 3) * 10;
sw_w32_mask(0x3ff << pos, priv->rxringlen << pos, priv->r->dma_if_rx_ring_size(i));
// Some SoCs have issues with missing underflow protection
v = (sw_r32(priv->r->dma_if_rx_ring_cntr(i)) >> pos) & 0x3ff;
sw_w32_mask(0x3ff << pos, v, priv->r->dma_if_rx_ring_cntr(i));
}
/* Enable Notify, RX done, RX overflow and TX done interrupts */
sw_w32(0xffffffff, priv->r->dma_if_intr_rx_runout_msk);
sw_w32(0xffffffff, priv->r->dma_if_intr_rx_done_msk);
sw_w32(0x0000000f, priv->r->dma_if_intr_tx_done_msk);
/* Enable DMA */
sw_w32_mask(0, RX_EN_93XX | TX_EN_93XX, priv->r->dma_if_ctrl);
/* Restart TX/RX to CPU port, enable CRC checking */
sw_w32_mask(0x0, 0x3 | BIT(4), priv->r->mac_port_ctrl(priv->cpu_port));
sw_w32_mask(0, BIT(priv->cpu_port), RTL930X_L2_UNKN_UC_FLD_PMSK);
sw_w32(0x217, priv->r->mac_force_mode_ctrl + priv->cpu_port * 4);
}
static void rtl838x_setup_ring_buffer(struct rtl838x_eth_priv *priv, struct ring_b *ring)
{
int i, j;
struct p_hdr *h;
for (i = 0; i < priv->rxrings; i++) {
for (j = 0; j < priv->rxringlen; j++) {
h = &ring->rx_header[i][j];
memset(h, 0, sizeof(struct p_hdr));
h->buf = (u8 *)KSEG1ADDR(ring->rx_space
+ i * priv->rxringlen * RING_BUFFER
+ j * RING_BUFFER);
h->size = RING_BUFFER;
/* All rings owned by switch, last one wraps */
ring->rx_r[i][j] = KSEG1ADDR(h) | 1
| (j == (priv->rxringlen - 1) ? WRAP : 0);
}
ring->c_rx[i] = 0;
}
for (i = 0; i < TXRINGS; i++) {
for (j = 0; j < TXRINGLEN; j++) {
h = &ring->tx_header[i][j];
memset(h, 0, sizeof(struct p_hdr));
h->buf = (u8 *)KSEG1ADDR(ring->tx_space
+ i * TXRINGLEN * RING_BUFFER
+ j * RING_BUFFER);
h->size = RING_BUFFER;
ring->tx_r[i][j] = KSEG1ADDR(&ring->tx_header[i][j]);
}
/* Last header is wrapping around */
ring->tx_r[i][j-1] |= WRAP;
ring->c_tx[i] = 0;
}
}
static void rtl839x_setup_notify_ring_buffer(struct rtl838x_eth_priv *priv)
{
int i;
struct notify_b *b = priv->membase + sizeof(struct ring_b);
for (i = 0; i < NOTIFY_BLOCKS; i++)
b->ring[i] = KSEG1ADDR(&b->blocks[i]) | 1 | (i == (NOTIFY_BLOCKS - 1) ? WRAP : 0);
sw_w32((u32) b->ring, RTL839X_DMA_IF_NBUF_BASE_DESC_ADDR_CTRL);
sw_w32_mask(0x3ff << 2, 100 << 2, RTL839X_L2_NOTIFICATION_CTRL);
/* Setup notification events */
sw_w32_mask(0, 1 << 14, RTL839X_L2_CTRL_0); // RTL8390_L2_CTRL_0_FLUSH_NOTIFY_EN
sw_w32_mask(0, 1 << 12, RTL839X_L2_NOTIFICATION_CTRL); // SUSPEND_NOTIFICATION_EN
/* Enable Notification */
sw_w32_mask(0, 1 << 0, RTL839X_L2_NOTIFICATION_CTRL);
priv->lastEvent = 0;
}
static int rtl838x_eth_open(struct net_device *ndev)
{
unsigned long flags;
struct rtl838x_eth_priv *priv = netdev_priv(ndev);
struct ring_b *ring = priv->membase;
int i, err;
pr_debug("%s called: RX rings %d(length %d), TX rings %d(length %d)\n",
__func__, priv->rxrings, priv->rxringlen, TXRINGS, TXRINGLEN);
spin_lock_irqsave(&priv->lock, flags);
rtl838x_hw_reset(priv);
rtl838x_setup_ring_buffer(priv, ring);
if (priv->family_id == RTL8390_FAMILY_ID) {
rtl839x_setup_notify_ring_buffer(priv);
/* Make sure the ring structure is visible to the ASIC */
mb();
flush_cache_all();
}
rtl838x_hw_ring_setup(priv);
err = request_irq(ndev->irq, priv->r->net_irq, IRQF_SHARED, ndev->name, ndev);
if (err) {
netdev_err(ndev, "%s: could not acquire interrupt: %d\n",
__func__, err);
return err;
}
phylink_start(priv->phylink);
for (i = 0; i < priv->rxrings; i++)
napi_enable(&priv->rx_qs[i].napi);
switch (priv->family_id) {
case RTL8380_FAMILY_ID:
rtl838x_hw_en_rxtx(priv);
/* Trap IGMP/MLD traffic to CPU-Port */
sw_w32(0x3, RTL838X_SPCL_TRAP_IGMP_CTRL);
/* Flush learned FDB entries on link down of a port */
sw_w32_mask(0, BIT(7), RTL838X_L2_CTRL_0);
break;
case RTL8390_FAMILY_ID:
rtl839x_hw_en_rxtx(priv);
// Trap MLD and IGMP messages to CPU_PORT
sw_w32(0x3, RTL839X_SPCL_TRAP_IGMP_CTRL);
/* Flush learned FDB entries on link down of a port */
sw_w32_mask(0, BIT(7), RTL839X_L2_CTRL_0);
break;
case RTL9300_FAMILY_ID:
rtl93xx_hw_en_rxtx(priv);
/* Flush learned FDB entries on link down of a port */
sw_w32_mask(0, BIT(7), RTL930X_L2_CTRL);
// Trap MLD and IGMP messages to CPU_PORT
sw_w32((0x2 << 3) | 0x2, RTL930X_VLAN_APP_PKT_CTRL);
break;
case RTL9310_FAMILY_ID:
rtl93xx_hw_en_rxtx(priv);
break;
}
netif_tx_start_all_queues(ndev);
spin_unlock_irqrestore(&priv->lock, flags);
return 0;
}
static void rtl838x_hw_stop(struct rtl838x_eth_priv *priv)
{
u32 force_mac = priv->family_id == RTL8380_FAMILY_ID ? 0x6192C : 0x75;
u32 clear_irq = priv->family_id == RTL8380_FAMILY_ID ? 0x000fffff : 0x007fffff;
int i;
// Disable RX/TX from/to CPU-port
sw_w32_mask(0x3, 0, priv->r->mac_port_ctrl(priv->cpu_port));
/* Disable traffic */
if (priv->family_id == RTL9300_FAMILY_ID || priv->family_id == RTL9310_FAMILY_ID)
sw_w32_mask(RX_EN_93XX | TX_EN_93XX, 0, priv->r->dma_if_ctrl);
else
sw_w32_mask(RX_EN | TX_EN, 0, priv->r->dma_if_ctrl);
mdelay(200); // Test, whether this is needed
/* Block all ports */
if (priv->family_id == RTL8380_FAMILY_ID) {
sw_w32(0x03000000, RTL838X_TBL_ACCESS_DATA_0(0));
sw_w32(0x00000000, RTL838X_TBL_ACCESS_DATA_0(1));
sw_w32(1 << 15 | 2 << 12, RTL838X_TBL_ACCESS_CTRL_0);
}
/* Flush L2 address cache */
if (priv->family_id == RTL8380_FAMILY_ID) {
for (i = 0; i <= priv->cpu_port; i++) {
sw_w32(1 << 26 | 1 << 23 | i << 5, priv->r->l2_tbl_flush_ctrl);
do { } while (sw_r32(priv->r->l2_tbl_flush_ctrl) & (1 << 26));
}
} else if (priv->family_id == RTL8390_FAMILY_ID) {
for (i = 0; i <= priv->cpu_port; i++) {
sw_w32(1 << 28 | 1 << 25 | i << 5, priv->r->l2_tbl_flush_ctrl);
do { } while (sw_r32(priv->r->l2_tbl_flush_ctrl) & (1 << 28));
}
}
// TODO: L2 flush register is 64 bit on RTL931X and 930X
/* CPU-Port: Link down */
if (priv->family_id == RTL8380_FAMILY_ID || priv->family_id == RTL8390_FAMILY_ID)
sw_w32(force_mac, priv->r->mac_force_mode_ctrl + priv->cpu_port * 4);
else
sw_w32_mask(0x3, 0, priv->r->mac_force_mode_ctrl + priv->cpu_port *4);
mdelay(100);
/* Disable all TX/RX interrupts */
if (priv->family_id == RTL9300_FAMILY_ID || priv->family_id == RTL9310_FAMILY_ID) {
sw_w32(0x00000000, priv->r->dma_if_intr_rx_runout_msk);
sw_w32(0xffffffff, priv->r->dma_if_intr_rx_runout_sts);
sw_w32(0x00000000, priv->r->dma_if_intr_rx_done_msk);
sw_w32(0xffffffff, priv->r->dma_if_intr_rx_done_sts);
sw_w32(0x00000000, priv->r->dma_if_intr_tx_done_msk);
sw_w32(0x0000000f, priv->r->dma_if_intr_tx_done_sts);
} else {
sw_w32(0x00000000, priv->r->dma_if_intr_msk);
sw_w32(clear_irq, priv->r->dma_if_intr_sts);
}
/* Disable TX/RX DMA */
sw_w32(0x00000000, priv->r->dma_if_ctrl);
mdelay(200);
}
static int rtl838x_eth_stop(struct net_device *ndev)
{
unsigned long flags;
int i;
struct rtl838x_eth_priv *priv = netdev_priv(ndev);