hiveap-330.dts

/*
 * Aerohive HiveAP-330 Device Tree Source
 *
 * Copyright (C) 2017 Chris Blake <chrisrblake93@gmail.com>
 *
 * This program is free software; you can redistribute  it and/or modify it
 * under  the terms of  the GNU General  Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 */

/include/ "fsl/p1020si-pre.dtsi"
/ {
	model = "Aerohive HiveAP-330";
	compatible = "aerohive,hiveap-330";

	aliases {
		led-boot = &tricolor_green;
		led-failsafe = &tricolor_red;
		led-running = &tricolor_green;
		led-upgrade = &tricolor_red;
		label-mac-device = &enet0;
	};

	memory {
		device_type = "memory";
	};

	board_lbc: lbc: localbus@ffe05000 {
		reg = <0 0xffe05000 0 0x1000>;
		ranges = <0x0 0x0 0x0 0xec000000 0x4000000>;

		nor@0,0 {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "cfi-flash";
			reg = <0x0 0x0 0x4000000>;
			bank-width = <2>;
			device-width = <1>;

			partitions {
				compatible = "fixed-partitions";
				#address-cells = <1>;
				#size-cells = <1>;

				firmware@0 {
					reg = <0x0 0x3f00000>;
					label = "firmware";
					/*
					 * This unknown/invalid compatible prevents
					 * openwrt's mtdsplit_fit to go off a tangent if it
					 * finds a magic value inside the uncompressed kernel
					 * at a blocksized aligned place.
					 */
					compatible = "areohive,hiveap-330-image";
				};

				partition@0 {
					reg = <0x0 0x40000>;
					label = "dtb";
				};

				partition@40000 {
					compatible = "openwrt,uimage", "denx,uimage";
					reg = <0x40000 0x3ec0000>;
					label = "kernel";
				};

				partition@3f00000 {
					reg = <0x3f00000 0x20000>;
					label = "hw-info";
					read-only;

					compatible = "nvmem-cells";
					#address-cells = <1>;
					#size-cells = <1>;

					macaddr_hwinfo_0: macaddr@0 {
						reg = <0x0 0x6>;
					};
				};

				partition@3f20000 {
					reg = <0x3f20000 0x20000>;
					label = "boot-info";
					read-only;
				};

				partition@3f40000 {
					reg = <0x3f40000 0x20000>;
					label = "boot-info-backup";
					read-only;
				};

				partition@3f60000 {
					reg = <0x3f60000 0x20000>;
					label = "u-boot-env";
				};

				partition@3f80000 {
					reg = <0x3f80000 0x80000>;
					label = "u-boot";
					read-only;
				};
			};
		};
	};

	board_soc: soc: soc@ffe00000 {
		ranges = <0x0 0x0 0xffe00000 0x100000>;

		i2c@3100 {
			tpm@29 {
				compatible = "atmel,at97sc3204t";
				reg = <0x29>;
			};

			lp5521@32 {
				compatible = "national,lp5521";
				reg = <0x32>;
				clock-mode = /bits/ 8 <2>;
				tricolor_red: chan0 {
					chan-name = "hiveap-330:red:tricolor0";
					led-cur = /bits/ 8 <0x2f>;
					max-cur = /bits/ 8 <0x5f>;
				};
				tricolor_green:chan1 {
					chan-name = "hiveap-330:green:tricolor0";
					led-cur = /bits/ 8 <0x2f>;
					max-cur = /bits/ 8 <0x5f>;
				};
				chan2 {
					chan-name = "hiveap-330:blue:tricolor0";
					led-cur = /bits/ 8 <0x2f>;
					max-cur = /bits/ 8 <0x5f>;
				};
			};

			/* Most likely SoC boot config */
			eeprom@51 {
				compatible = "eeprom";
				reg = <0x51>;
			};
		};

		mdio@24000 {
			phy0: ethernet-phy@0 {
				interrupts = <3 1 0 0>;
				reg = <0x1>;
			};

			phy1: ethernet-phy@1 {
				interrupts = <2 1 0 0>;
				reg = <0x2>;
			};
		};

		mdio@25000 {
			status = "disabled";
		};

		mdio@26000 {
			status = "disabled";
		};

		enet0: ethernet@b0000 {
			status = "okay";
			phy-handle = <&phy0>;
			phy-connection-type = "rgmii-id";
			nvmem-cells = <&macaddr_hwinfo_0>;
			nvmem-cell-names = "mac-address";
		};

		enet1: ethernet@b1000 {
			status = "disabled";
		};

		enet2: ethernet@b2000 {
			status = "okay";
			phy-handle = <&phy1>;
			phy-connection-type = "rgmii-id";
			nvmem-cells = <&macaddr_hwinfo_0>;
			nvmem-cell-names = "mac-address";
			mac-address-increment = <1>;
		};

		gpio0: gpio-controller@fc00 {
		};

		usb@22000 {
			phy_type = "ulpi";
			dr_mode = "host";
		};

		usb@23000 {
			status = "disabled";
		};
	};

	pci0: pcie@ffe09000 {
		reg = <0x0 0xffe09000 0x0 0x1000>;
		ranges = <0x2000000 0x0 0xa0000000 0x0 0xa0000000 0x0 0x20000000
			0x1000000 0x0 0x00000000 0x0 0xffc30000 0x0 0x10000>;
		pcie@0 {
			ranges = <0x2000000 0x0 0xa0000000
				  0x2000000 0x0 0xa0000000
				  0x0 0x20000000

				  0x1000000 0x0 0x0
				  0x1000000 0x0 0x0
				  0x0 0x100000>;
		};
	};

	pci1: pcie@ffe0a000 {
		reg = <0x0 0xffe0a000 0x0 0x1000>;
		ranges = <0x2000000 0x0 0xc0000000 0x0 0xc0000000 0x0 0x20000000
		      0x1000000 0x0 0x00000000 0x0 0xffc20000 0x0 0x10000>;
		pcie@0 {
			ranges = <0x2000000 0x0 0xc0000000
			      0x2000000 0x0 0xc0000000
				  0x0 0x20000000

				  0x1000000 0x0 0x0
				  0x1000000 0x0 0x0
				  0x0 0x100000>;
		};
	};

	buttons {
		compatible = "gpio-keys";

		reset {
			label = "Reset button";
			gpios = <&gpio0 8 1>; /* active low */
			linux,code = <0x198>; /* KEY_RESTART */
		};
	};
};
/include/ "fsl/p1020si-post.dtsi"