Document RISC-V a bit more

README.md

@@ -10,11 +10,13 @@ Target side implementation of the RTT (Real-Time Transfer) I/O protocol. RTT imp
 
 While this crate is platform agnostic, some platform-specific code is needed for locking if you want to use the global `rprintln!` macro.
 
-If using Cortex-M, there is built-in support with a feature flag:
+If using Cortex-M or RISC-V, there is built-in support with a feature flag:
 
 ```toml
 # Cargo.toml
 rtt-target = { version = "x.y.z", features = ["cortex-m"] }
+# or
+rtt-target = { version = "x.y.z", features = ["riscv"] }
 ```
 
 Otherwise, check the documentation for the `set_print_channel_cs` function.

rtt-target/src/lib.rs

@@ -9,8 +9,8 @@
 //!
 //! This crate is platform agnostic and can be used on any chip that supports background memory
 //! access via its debug interface. The printing macros require a critical section which is
-//! platform-dependent. ARM Cortex-M has built-in support, which can be enabled with the "cortex-m"
-//! feature flag.
+//! platform-dependent. Built-in ARM Cortex-M support can be enabled with the "cortex-m" feature,
+//! and RISC-V support can be enabled with the "riscv" feature.
 //!
 //! To interface with RTT from the host computer, a debug probe such as an ST-Link or J-Link is
 //! required. The normal debug protocol (e.g. SWD) is used to access RTT, so no extra connections

rtt-target/src/print.rs

@@ -218,6 +218,8 @@ macro_rules! rtt_init_print {
             "- Enable a platform support feature:\r\n",
             "    # Cargo.toml\r\n",
             "    rtt-target = { version = \"x.y.z\", features = [\"cortex-m\"] }\r\n",
+            "    # or",
+            "    rtt-target = { version = \"x.y.z\", features = [\"riscv\"] }\r\n",
             "- OR use set_print_channel_cs() instead if you want to provide your own locking.\r\n"
         ))
     };