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msm_serial_hs.c
3489 lines (3020 loc) · 94.2 KB
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msm_serial_hs.c
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/* drivers/serial/msm_serial_hs.c
*
* MSM 7k High speed uart driver
*
* Copyright (c) 2008 Google Inc.
* Copyright (c) 2007-2013, The Linux Foundation. All rights reserved.
* Modified: Nick Pelly <npelly@google.com>
*
* All source code in this file is licensed under the following license
* except where indicated.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
* See the GNU General Public License for more details.
*
* Has optional support for uart power management independent of linux
* suspend/resume:
*
* RX wakeup.
* UART wakeup can be triggered by RX activity (using a wakeup GPIO on the
* UART RX pin). This should only be used if there is not a wakeup
* GPIO on the UART CTS, and the first RX byte is known (for example, with the
* Bluetooth Texas Instruments HCILL protocol), since the first RX byte will
* always be lost. RTS will be asserted even while the UART is off in this mode
* of operation. See msm_serial_hs_platform_data.rx_wakeup_irq.
*/
#include <linux/module.h>
#include <linux/serial.h>
#include <linux/serial_core.h>
#include <linux/slab.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/io.h>
#include <linux/ioport.h>
#include <linux/atomic.h>
#include <linux/kernel.h>
#include <linux/timer.h>
#include <linux/clk.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/dma-mapping.h>
#include <linux/dmapool.h>
#include <linux/tty_flip.h>
#include <linux/wait.h>
#include <linux/sysfs.h>
#include <linux/stat.h>
#include <linux/device.h>
#include <linux/wakelock.h>
#include <linux/debugfs.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/of_gpio.h>
#include <linux/gpio.h>
#include <asm/atomic.h>
#include <asm/irq.h>
#include <mach/hardware.h>
#include <mach/dma.h>
#include <mach/sps.h>
#include <mach/msm_serial_hs.h>
#include <mach/msm_bus.h>
#include "msm_serial_hs_hwreg.h"
#define UART_SPS_CONS_PERIPHERAL 0
#define UART_SPS_PROD_PERIPHERAL 1
static int hs_serial_debug_mask = 1;
module_param_named(debug_mask, hs_serial_debug_mask,
int, S_IRUGO | S_IWUSR | S_IWGRP);
/*
* There are 3 different kind of UART Core available on MSM.
* High Speed UART (i.e. Legacy HSUART), GSBI based HSUART
* and BSLP based HSUART.
*/
enum uart_core_type {
LEGACY_HSUART,
GSBI_HSUART,
BLSP_HSUART,
};
enum flush_reason {
FLUSH_NONE,
FLUSH_DATA_READY,
FLUSH_DATA_INVALID, /* values after this indicate invalid data */
FLUSH_IGNORE = FLUSH_DATA_INVALID,
FLUSH_STOP,
FLUSH_SHUTDOWN,
};
enum msm_hs_clk_states_e {
MSM_HS_CLK_PORT_OFF, /* port not in use */
MSM_HS_CLK_OFF, /* clock disabled */
MSM_HS_CLK_REQUEST_OFF, /* disable after TX and RX flushed */
MSM_HS_CLK_ON, /* clock enabled */
};
/* Track the forced RXSTALE flush during clock off sequence.
* These states are only valid during MSM_HS_CLK_REQUEST_OFF */
enum msm_hs_clk_req_off_state_e {
CLK_REQ_OFF_START,
CLK_REQ_OFF_RXSTALE_ISSUED,
CLK_REQ_OFF_FLUSH_ISSUED,
CLK_REQ_OFF_RXSTALE_FLUSHED,
};
/* SPS data structures to support HSUART with BAM
* @sps_pipe - This struct defines BAM pipe descriptor
* @sps_connect - This struct defines a connection's end point
* @sps_register - This struct defines a event registration parameters
*/
struct msm_hs_sps_ep_conn_data {
struct sps_pipe *pipe_handle;
struct sps_connect config;
struct sps_register_event event;
};
struct msm_hs_tx {
unsigned int tx_ready_int_en; /* ok to dma more tx */
unsigned int dma_in_flight; /* tx dma in progress */
enum flush_reason flush;
wait_queue_head_t wait;
struct msm_dmov_cmd xfer;
dmov_box *command_ptr;
u32 *command_ptr_ptr;
dma_addr_t mapped_cmd_ptr;
dma_addr_t mapped_cmd_ptr_ptr;
int tx_count;
dma_addr_t dma_base;
struct tasklet_struct tlet;
struct msm_hs_sps_ep_conn_data cons;
};
struct msm_hs_rx {
enum flush_reason flush;
struct msm_dmov_cmd xfer;
dma_addr_t cmdptr_dmaaddr;
dmov_box *command_ptr;
u32 *command_ptr_ptr;
dma_addr_t mapped_cmd_ptr;
wait_queue_head_t wait;
dma_addr_t rbuffer;
unsigned char *buffer;
unsigned int buffer_pending;
struct dma_pool *pool;
struct wake_lock wake_lock;
struct delayed_work flip_insert_work;
struct tasklet_struct tlet;
struct msm_hs_sps_ep_conn_data prod;
};
enum buffer_states {
NONE_PENDING = 0x0,
FIFO_OVERRUN = 0x1,
PARITY_ERROR = 0x2,
CHARS_NORMAL = 0x4,
};
/* optional low power wakeup, typically on a GPIO RX irq */
struct msm_hs_wakeup {
int irq; /* < 0 indicates low power wakeup disabled */
unsigned char ignore; /* bool */
/* bool: inject char into rx tty on wakeup */
unsigned char inject_rx;
char rx_to_inject;
};
struct msm_hs_port {
struct uart_port uport;
unsigned long imr_reg; /* shadow value of UARTDM_IMR */
struct clk *clk;
struct clk *pclk;
struct msm_hs_tx tx;
struct msm_hs_rx rx;
/* gsbi uarts have to do additional writes to gsbi memory */
/* block and top control status block. The following pointers */
/* keep a handle to these blocks. */
unsigned char __iomem *mapped_gsbi;
int dma_tx_channel;
int dma_rx_channel;
int dma_tx_crci;
int dma_rx_crci;
struct hrtimer clk_off_timer; /* to poll TXEMT before clock off */
ktime_t clk_off_delay;
enum msm_hs_clk_states_e clk_state;
enum msm_hs_clk_req_off_state_e clk_req_off_state;
atomic_t clk_count;
struct msm_hs_wakeup wakeup;
struct wake_lock dma_wake_lock; /* held while any DMA active */
struct dentry *loopback_dir;
struct work_struct clock_off_w; /* work for actual clock off */
struct workqueue_struct *hsuart_wq; /* hsuart workqueue */
struct mutex clk_mutex; /* mutex to guard against clock off/clock on */
struct work_struct disconnect_rx_endpoint; /* disconnect rx_endpoint */
bool tty_flush_receive;
enum uart_core_type uart_type;
u32 bam_handle;
resource_size_t bam_mem;
int bam_irq;
unsigned char __iomem *bam_base;
unsigned int bam_tx_ep_pipe_index;
unsigned int bam_rx_ep_pipe_index;
/* struct sps_event_notify is an argument passed when triggering a
* callback event object registered for an SPS connection end point.
*/
struct sps_event_notify notify;
/* bus client handler */
u32 bus_perf_client;
/* BLSP UART required BUS Scaling data */
struct msm_bus_scale_pdata *bus_scale_table;
bool rx_discard_flush_issued;
int rx_count_callback;
bool rx_bam_inprogress;
bool obs;
};
#define MSM_UARTDM_BURST_SIZE 16 /* DM burst size (in bytes) */
#define UARTDM_TX_BUF_SIZE UART_XMIT_SIZE
#define UARTDM_RX_BUF_SIZE 512
#define RETRY_TIMEOUT 5
#define UARTDM_NR 256
#define BAM_PIPE_MIN 0
#define BAM_PIPE_MAX 11
#define BUS_SCALING 1
#define BUS_RESET 0
#define RX_FLUSH_COMPLETE_TIMEOUT 300 /* In jiffies */
#define BLSP_UART_CLK_FMAX 63160000
static struct dentry *debug_base;
static struct msm_hs_port q_uart_port[UARTDM_NR];
static struct platform_driver msm_serial_hs_platform_driver;
static struct uart_driver msm_hs_driver;
static struct uart_ops msm_hs_ops;
static void msm_hs_start_rx_locked(struct uart_port *uport);
static void msm_serial_hs_rx_tlet(unsigned long tlet_ptr);
static void flip_insert_work(struct work_struct *work);
static void msm_hs_bus_voting(struct msm_hs_port *msm_uport, unsigned int vote);
#define UARTDM_TO_MSM(uart_port) \
container_of((uart_port), struct msm_hs_port, uport)
static int msm_hs_ioctl(struct uart_port *uport, unsigned int cmd,
unsigned long arg)
{
int ret = 0, state = 1;
enum msm_hs_clk_states_e clk_state;
unsigned long flags;
struct msm_hs_port *msm_uport = UARTDM_TO_MSM(uport);
switch (cmd) {
case MSM_ENABLE_UART_CLOCK: {
pr_debug("%s():ENABLE UART CLOCK: cmd=%d\n", __func__, cmd);
msm_hs_request_clock_on(&msm_uport->uport);
break;
}
case MSM_DISABLE_UART_CLOCK: {
pr_debug("%s():DISABLE UART CLOCK: cmd=%d\n", __func__, cmd);
msm_hs_request_clock_off(&msm_uport->uport);
break;
}
case MSM_GET_UART_CLOCK_STATUS: {
/* Return value 0 - UART CLOCK is OFF
* Return value 1 - UART CLOCK is ON */
pr_debug("%s():GET UART CLOCK STATUS: cmd=%d\n", __func__, cmd);
spin_lock_irqsave(&msm_uport->uport.lock, flags);
clk_state = msm_uport->clk_state;
spin_unlock_irqrestore(&msm_uport->uport.lock, flags);
if (clk_state <= MSM_HS_CLK_OFF)
state = 0;
ret = state;
break;
}
default: {
pr_debug("%s():Unknown cmd specified: cmd=%d\n", __func__, cmd);
ret = -ENOIOCTLCMD;
break;
}
}
return ret;
}
static int msm_hs_clock_vote(struct msm_hs_port *msm_uport)
{
int rc = 0;
if (1 == atomic_inc_return(&msm_uport->clk_count)) {
msm_hs_bus_voting(msm_uport, BUS_SCALING);
/* Turn on core clk and iface clk */
rc = clk_prepare_enable(msm_uport->clk);
if (rc) {
atomic_dec(&msm_uport->clk_count);
dev_err(msm_uport->uport.dev,
"%s: Could not turn on core clk [%d]\n",
__func__, rc);
return rc;
}
if (msm_uport->pclk) {
rc = clk_prepare_enable(msm_uport->pclk);
if (rc) {
clk_disable_unprepare(msm_uport->clk);
atomic_dec(&msm_uport->clk_count);
dev_err(msm_uport->uport.dev,
"%s: Could not turn on pclk [%d]\n",
__func__, rc);
return rc;
}
}
msm_uport->clk_state = MSM_HS_CLK_ON;
}
return rc;
}
static void msm_hs_clock_unvote(struct msm_hs_port *msm_uport)
{
if (1 == __atomic_add_unless(&msm_uport->clk_count, -1, 0)) {
msm_hs_bus_voting(msm_uport, BUS_RESET);
/* Turn off the core clk and iface clk*/
clk_disable_unprepare(msm_uport->clk);
if (msm_uport->pclk)
clk_disable_unprepare(msm_uport->pclk);
msm_uport->clk_state = MSM_HS_CLK_OFF;
}
}
static ssize_t show_clock(struct device *dev, struct device_attribute *attr,
char *buf)
{
int state = 1;
enum msm_hs_clk_states_e clk_state;
unsigned long flags;
struct platform_device *pdev = container_of(dev, struct
platform_device, dev);
struct msm_hs_port *msm_uport = &q_uart_port[pdev->id];
spin_lock_irqsave(&msm_uport->uport.lock, flags);
clk_state = msm_uport->clk_state;
spin_unlock_irqrestore(&msm_uport->uport.lock, flags);
if (clk_state <= MSM_HS_CLK_OFF)
state = 0;
return snprintf(buf, PAGE_SIZE, "%d\n", state);
}
static ssize_t set_clock(struct device *dev, struct device_attribute *attr,
const char *buf, size_t count)
{
int state;
struct platform_device *pdev = container_of(dev, struct
platform_device, dev);
struct msm_hs_port *msm_uport = &q_uart_port[pdev->id];
state = buf[0] - '0';
switch (state) {
case 0: {
msm_hs_request_clock_off(&msm_uport->uport);
break;
}
case 1: {
msm_hs_request_clock_on(&msm_uport->uport);
break;
}
default: {
return -EINVAL;
}
}
return count;
}
static DEVICE_ATTR(clock, S_IWUSR | S_IRUGO, show_clock, set_clock);
static inline unsigned int use_low_power_wakeup(struct msm_hs_port *msm_uport)
{
return (msm_uport->wakeup.irq > 0);
}
static inline int is_gsbi_uart(struct msm_hs_port *msm_uport)
{
/* assume gsbi uart if gsbi resource found in pdata */
return ((msm_uport->mapped_gsbi != NULL));
}
static unsigned int is_blsp_uart(struct msm_hs_port *msm_uport)
{
return (msm_uport->uart_type == BLSP_HSUART);
}
static void msm_hs_bus_voting(struct msm_hs_port *msm_uport, unsigned int vote)
{
int ret;
if (is_blsp_uart(msm_uport) && msm_uport->bus_perf_client) {
pr_debug("Bus voting:%d\n", vote);
ret = msm_bus_scale_client_update_request(
msm_uport->bus_perf_client, vote);
if (ret)
pr_err("%s(): Failed for Bus voting: %d\n",
__func__, vote);
}
}
static inline unsigned int msm_hs_read(struct uart_port *uport,
unsigned int offset)
{
return readl_relaxed(uport->membase + offset);
}
static inline void msm_hs_write(struct uart_port *uport, unsigned int offset,
unsigned int value)
{
writel_relaxed(value, uport->membase + offset);
}
static void msm_hs_release_port(struct uart_port *port)
{
struct msm_hs_port *msm_uport = UARTDM_TO_MSM(port);
struct platform_device *pdev = to_platform_device(port->dev);
struct resource *gsbi_resource;
resource_size_t size;
if (is_gsbi_uart(msm_uport)) {
iowrite32(GSBI_PROTOCOL_IDLE, msm_uport->mapped_gsbi +
GSBI_CONTROL_ADDR);
gsbi_resource = platform_get_resource_byname(pdev,
IORESOURCE_MEM,
"gsbi_resource");
if (unlikely(!gsbi_resource))
return;
size = resource_size(gsbi_resource);
release_mem_region(gsbi_resource->start, size);
iounmap(msm_uport->mapped_gsbi);
msm_uport->mapped_gsbi = NULL;
}
}
static int msm_hs_request_port(struct uart_port *port)
{
struct msm_hs_port *msm_uport = UARTDM_TO_MSM(port);
struct platform_device *pdev = to_platform_device(port->dev);
struct resource *gsbi_resource;
resource_size_t size;
gsbi_resource = platform_get_resource_byname(pdev,
IORESOURCE_MEM,
"gsbi_resource");
if (gsbi_resource) {
size = resource_size(gsbi_resource);
if (unlikely(!request_mem_region(gsbi_resource->start, size,
"msm_serial_hs")))
return -EBUSY;
msm_uport->mapped_gsbi = ioremap(gsbi_resource->start,
size);
if (!msm_uport->mapped_gsbi) {
release_mem_region(gsbi_resource->start, size);
return -EBUSY;
}
}
/* no gsbi uart */
return 0;
}
static int msm_serial_loopback_enable_set(void *data, u64 val)
{
struct msm_hs_port *msm_uport = data;
struct uart_port *uport = &(msm_uport->uport);
unsigned long flags;
int ret = 0;
ret = msm_hs_clock_vote(msm_uport);
if (ret) {
printk(KERN_ERR "%s: Error could not turn on UART clk\n",
__func__);
return ret;
}
if (val) {
spin_lock_irqsave(&uport->lock, flags);
ret = msm_hs_read(uport, UARTDM_MR2_ADDR);
if (is_blsp_uart(msm_uport))
ret |= (UARTDM_MR2_LOOP_MODE_BMSK |
UARTDM_MR2_RFR_CTS_LOOP_MODE_BMSK);
else
ret |= UARTDM_MR2_LOOP_MODE_BMSK;
msm_hs_write(uport, UARTDM_MR2_ADDR, ret);
spin_unlock_irqrestore(&uport->lock, flags);
} else {
spin_lock_irqsave(&uport->lock, flags);
ret = msm_hs_read(uport, UARTDM_MR2_ADDR);
if (is_blsp_uart(msm_uport))
ret &= ~(UARTDM_MR2_LOOP_MODE_BMSK |
UARTDM_MR2_RFR_CTS_LOOP_MODE_BMSK);
else
ret &= ~UARTDM_MR2_LOOP_MODE_BMSK;
msm_hs_write(uport, UARTDM_MR2_ADDR, ret);
spin_unlock_irqrestore(&uport->lock, flags);
}
/* Calling CLOCK API. Hence mb() requires here. */
mb();
msm_hs_clock_unvote(msm_uport);
return 0;
}
static int msm_serial_loopback_enable_get(void *data, u64 *val)
{
struct msm_hs_port *msm_uport = data;
struct uart_port *uport = &(msm_uport->uport);
unsigned long flags;
int ret = 0;
ret = msm_hs_clock_vote(msm_uport);
if (ret) {
printk(KERN_ERR "%s: Error could not turn on UART clk\n",
__func__);
return ret;
}
spin_lock_irqsave(&uport->lock, flags);
ret = msm_hs_read(&msm_uport->uport, UARTDM_MR2_ADDR);
spin_unlock_irqrestore(&uport->lock, flags);
msm_hs_clock_unvote(msm_uport);
*val = (ret & UARTDM_MR2_LOOP_MODE_BMSK) ? 1 : 0;
return 0;
}
DEFINE_SIMPLE_ATTRIBUTE(loopback_enable_fops, msm_serial_loopback_enable_get,
msm_serial_loopback_enable_set, "%llu\n");
/*
* msm_serial_hs debugfs node: <debugfs_root>/msm_serial_hs/loopback.<id>
* writing 1 turns on internal loopback mode in HW. Useful for automation
* test scripts.
* writing 0 disables the internal loopback mode. Default is disabled.
*/
static void __devinit msm_serial_debugfs_init(struct msm_hs_port *msm_uport,
int id)
{
char node_name[15];
snprintf(node_name, sizeof(node_name), "loopback.%d", id);
msm_uport->loopback_dir = debugfs_create_file(node_name,
S_IRUGO | S_IWUSR,
debug_base,
msm_uport,
&loopback_enable_fops);
if (IS_ERR_OR_NULL(msm_uport->loopback_dir))
pr_err("%s(): Cannot create loopback.%d debug entry",
__func__, id);
}
static int __devexit msm_hs_remove(struct platform_device *pdev)
{
struct msm_hs_port *msm_uport;
struct device *dev;
if (pdev->id < 0 || pdev->id >= UARTDM_NR) {
printk(KERN_ERR "Invalid plaform device ID = %d\n", pdev->id);
return -EINVAL;
}
msm_uport = &q_uart_port[pdev->id];
dev = msm_uport->uport.dev;
sysfs_remove_file(&pdev->dev.kobj, &dev_attr_clock.attr);
debugfs_remove(msm_uport->loopback_dir);
dma_unmap_single(dev, msm_uport->rx.mapped_cmd_ptr, sizeof(dmov_box),
DMA_TO_DEVICE);
dma_pool_free(msm_uport->rx.pool, msm_uport->rx.buffer,
msm_uport->rx.rbuffer);
dma_pool_destroy(msm_uport->rx.pool);
dma_unmap_single(dev, msm_uport->rx.cmdptr_dmaaddr, sizeof(u32),
DMA_TO_DEVICE);
dma_unmap_single(dev, msm_uport->tx.mapped_cmd_ptr_ptr, sizeof(u32),
DMA_TO_DEVICE);
dma_unmap_single(dev, msm_uport->tx.mapped_cmd_ptr, sizeof(dmov_box),
DMA_TO_DEVICE);
wake_lock_destroy(&msm_uport->rx.wake_lock);
wake_lock_destroy(&msm_uport->dma_wake_lock);
destroy_workqueue(msm_uport->hsuart_wq);
mutex_destroy(&msm_uport->clk_mutex);
uart_remove_one_port(&msm_hs_driver, &msm_uport->uport);
clk_put(msm_uport->clk);
if (msm_uport->pclk)
clk_put(msm_uport->pclk);
/* Free the tx resources */
kfree(msm_uport->tx.command_ptr);
kfree(msm_uport->tx.command_ptr_ptr);
/* Free the rx resources */
kfree(msm_uport->rx.command_ptr);
kfree(msm_uport->rx.command_ptr_ptr);
iounmap(msm_uport->uport.membase);
return 0;
}
static int msm_hs_init_clk(struct uart_port *uport)
{
int ret;
struct msm_hs_port *msm_uport = UARTDM_TO_MSM(uport);
/* Set up the MREG/NREG/DREG/MNDREG */
ret = clk_set_rate(msm_uport->clk, uport->uartclk);
if (ret) {
printk(KERN_WARNING "Error setting clock rate on UART\n");
return ret;
}
ret = msm_hs_clock_vote(msm_uport);
if (ret) {
printk(KERN_ERR "%s: Error could not turn on UART clk\n",
__func__);
return ret;
}
return 0;
}
/* Connect a UART peripheral's SPS endpoint(consumer endpoint)
*
* Also registers a SPS callback function for the consumer
* process with the SPS driver
*
* @uport - Pointer to uart uport structure
*
* @return - 0 if successful else negative value.
*
*/
static int msm_hs_spsconnect_tx(struct uart_port *uport)
{
int ret;
struct msm_hs_port *msm_uport = UARTDM_TO_MSM(uport);
struct msm_hs_tx *tx = &msm_uport->tx;
struct sps_pipe *sps_pipe_handle = tx->cons.pipe_handle;
struct sps_connect *sps_config = &tx->cons.config;
struct sps_register_event *sps_event = &tx->cons.event;
/* Establish connection between peripheral and memory endpoint */
ret = sps_connect(sps_pipe_handle, sps_config);
if (ret) {
pr_err("msm_serial_hs: sps_connect() failed for tx!!\n"
"pipe_handle=0x%x ret=%d", (u32)sps_pipe_handle, ret);
return ret;
}
/* Register callback event for EOT (End of transfer) event. */
ret = sps_register_event(sps_pipe_handle, sps_event);
if (ret) {
pr_err("msm_serial_hs: sps_connect() failed for tx!!\n"
"pipe_handle=0x%x ret=%d", (u32)sps_pipe_handle, ret);
goto reg_event_err;
}
return 0;
reg_event_err:
sps_disconnect(sps_pipe_handle);
return ret;
}
/* Connect a UART peripheral's SPS endpoint(producer endpoint)
*
* Also registers a SPS callback function for the producer
* process with the SPS driver
*
* @uport - Pointer to uart uport structure
*
* @return - 0 if successful else negative value.
*
*/
static int msm_hs_spsconnect_rx(struct uart_port *uport)
{
int ret;
struct msm_hs_port *msm_uport = UARTDM_TO_MSM(uport);
struct msm_hs_rx *rx = &msm_uport->rx;
struct sps_pipe *sps_pipe_handle = rx->prod.pipe_handle;
struct sps_connect *sps_config = &rx->prod.config;
struct sps_register_event *sps_event = &rx->prod.event;
/* Establish connection between peripheral and memory endpoint */
ret = sps_connect(sps_pipe_handle, sps_config);
if (ret) {
pr_err("msm_serial_hs: sps_connect() failed for rx!!\n"
"pipe_handle=0x%x ret=%d", (u32)sps_pipe_handle, ret);
return ret;
}
/* Register callback event for DESC_DONE event. */
ret = sps_register_event(sps_pipe_handle, sps_event);
if (ret) {
pr_err("msm_serial_hs: sps_connect() failed for rx!!\n"
"pipe_handle=0x%x ret=%d", (u32)sps_pipe_handle, ret);
goto reg_event_err;
}
return 0;
reg_event_err:
sps_disconnect(sps_pipe_handle);
return ret;
}
/*
* programs the UARTDM_CSR register with correct bit rates
*
* Interrupts should be disabled before we are called, as
* we modify Set Baud rate
* Set receive stale interrupt level, dependant on Bit Rate
* Goal is to have around 8 ms before indicate stale.
* roundup (((Bit Rate * .008) / 10) + 1
*/
static void msm_hs_set_bps_locked(struct uart_port *uport,
unsigned int bps)
{
unsigned long rxstale;
unsigned long data;
struct msm_hs_port *msm_uport = UARTDM_TO_MSM(uport);
switch (bps) {
case 300:
msm_hs_write(uport, UARTDM_CSR_ADDR, 0x00);
rxstale = 1;
break;
case 600:
msm_hs_write(uport, UARTDM_CSR_ADDR, 0x11);
rxstale = 1;
break;
case 1200:
msm_hs_write(uport, UARTDM_CSR_ADDR, 0x22);
rxstale = 1;
break;
case 2400:
msm_hs_write(uport, UARTDM_CSR_ADDR, 0x33);
rxstale = 1;
break;
case 4800:
msm_hs_write(uport, UARTDM_CSR_ADDR, 0x44);
rxstale = 1;
break;
case 9600:
msm_hs_write(uport, UARTDM_CSR_ADDR, 0x55);
rxstale = 2;
break;
case 14400:
msm_hs_write(uport, UARTDM_CSR_ADDR, 0x66);
rxstale = 3;
break;
case 19200:
msm_hs_write(uport, UARTDM_CSR_ADDR, 0x77);
rxstale = 4;
break;
case 28800:
msm_hs_write(uport, UARTDM_CSR_ADDR, 0x88);
rxstale = 6;
break;
case 38400:
msm_hs_write(uport, UARTDM_CSR_ADDR, 0x99);
rxstale = 8;
break;
case 57600:
msm_hs_write(uport, UARTDM_CSR_ADDR, 0xaa);
rxstale = 16;
break;
case 76800:
msm_hs_write(uport, UARTDM_CSR_ADDR, 0xbb);
rxstale = 16;
break;
case 115200:
msm_hs_write(uport, UARTDM_CSR_ADDR, 0xcc);
rxstale = 31;
break;
case 230400:
msm_hs_write(uport, UARTDM_CSR_ADDR, 0xee);
rxstale = 31;
break;
case 460800:
msm_hs_write(uport, UARTDM_CSR_ADDR, 0xff);
rxstale = 31;
break;
case 4000000:
case 3686400:
case 3200000:
case 3500000:
case 3000000:
case 2500000:
case 1500000:
case 1152000:
case 1000000:
case 921600:
msm_hs_write(uport, UARTDM_CSR_ADDR, 0xff);
rxstale = 31;
break;
default:
msm_hs_write(uport, UARTDM_CSR_ADDR, 0xff);
/* default to 9600 */
bps = 9600;
rxstale = 2;
break;
}
/*
* uart baud rate depends on CSR and MND Values
* we are updating CSR before and then calling
* clk_set_rate which updates MND Values. Hence
* dsb requires here.
*/
mb();
if (bps > 460800) {
uport->uartclk = bps * 16;
if (is_blsp_uart(msm_uport)) {
/* BLSP based UART supports maximum clock frequency
* of 63.16 Mhz. With this (63.16 Mhz) clock frequency
* UART can support baud rate of 3.94 Mbps which is
* equivalent to 4 Mbps.
* UART hardware is robust enough to handle this
* deviation to achieve baud rate ~4 Mbps.
*/
if (bps == 4000000)
uport->uartclk = BLSP_UART_CLK_FMAX;
}
} else {
uport->uartclk = 7372800;
}
if (clk_set_rate(msm_uport->clk, uport->uartclk)) {
printk(KERN_WARNING "Error setting clock rate on UART\n");
WARN_ON(1);
}
data = rxstale & UARTDM_IPR_STALE_LSB_BMSK;
data |= UARTDM_IPR_STALE_TIMEOUT_MSB_BMSK & (rxstale << 2);
msm_hs_write(uport, UARTDM_IPR_ADDR, data);
/*
* It is suggested to do reset of transmitter and receiver after
* changing any protocol configuration. Here Baud rate and stale
* timeout are getting updated. Hence reset transmitter and receiver.
*/
msm_hs_write(uport, UARTDM_CR_ADDR, RESET_TX);
msm_hs_write(uport, UARTDM_CR_ADDR, RESET_RX);
}
static void msm_hs_set_std_bps_locked(struct uart_port *uport,
unsigned int bps)
{
unsigned long rxstale;
unsigned long data;
switch (bps) {
case 9600:
msm_hs_write(uport, UARTDM_CSR_ADDR, 0x99);
rxstale = 2;
break;
case 14400:
msm_hs_write(uport, UARTDM_CSR_ADDR, 0xaa);
rxstale = 3;
break;
case 19200:
msm_hs_write(uport, UARTDM_CSR_ADDR, 0xbb);
rxstale = 4;
break;
case 28800:
msm_hs_write(uport, UARTDM_CSR_ADDR, 0xcc);
rxstale = 6;
break;
case 38400:
msm_hs_write(uport, UARTDM_CSR_ADDR, 0xdd);
rxstale = 8;
break;
case 57600:
msm_hs_write(uport, UARTDM_CSR_ADDR, 0xee);
rxstale = 16;
break;
case 115200:
msm_hs_write(uport, UARTDM_CSR_ADDR, 0xff);
rxstale = 31;
break;
default:
msm_hs_write(uport, UARTDM_CSR_ADDR, 0x99);
/* default to 9600 */
bps = 9600;
rxstale = 2;
break;
}
data = rxstale & UARTDM_IPR_STALE_LSB_BMSK;
data |= UARTDM_IPR_STALE_TIMEOUT_MSB_BMSK & (rxstale << 2);
msm_hs_write(uport, UARTDM_IPR_ADDR, data);
}
/*
* termios : new ktermios
* oldtermios: old ktermios previous setting
*
* Configure the serial port
*/
static void msm_hs_set_termios(struct uart_port *uport,
struct ktermios *termios,
struct ktermios *oldtermios)
{
unsigned int bps;
unsigned long data;
int ret;
unsigned int c_cflag = termios->c_cflag;
struct msm_hs_port *msm_uport = UARTDM_TO_MSM(uport);
struct msm_hs_rx *rx = &msm_uport->rx;
struct sps_pipe *sps_pipe_handle = rx->prod.pipe_handle;
ret = msm_hs_clock_vote(msm_uport);
if (ret) {
printk(KERN_ERR "%s: Error could not turn on UART clk\n",
__func__);
return;
}
mutex_lock(&msm_uport->clk_mutex);
msm_hs_write(uport, UARTDM_IMR_ADDR, 0);
/*
* Disable Rx channel of UARTDM
* DMA Rx Stall happens if enqueue and flush of Rx command happens
* concurrently. Hence before changing the baud rate/protocol
* configuration and sending flush command to ADM, disable the Rx
* channel of UARTDM.
* Note: should not reset the receiver here immediately as it is not
* suggested to do disable/reset or reset/disable at the same time.
*/
data = msm_hs_read(uport, UARTDM_DMEN_ADDR);
if (is_blsp_uart(msm_uport)) {
/* Disable UARTDM RX BAM Interface */
data &= ~UARTDM_RX_BAM_ENABLE_BMSK;
} else {
data &= ~UARTDM_RX_DM_EN_BMSK;
}
msm_hs_write(uport, UARTDM_DMEN_ADDR, data);
/* 300 is the minimum baud support by the driver */
bps = uart_get_baud_rate(uport, termios, oldtermios, 200, 4000000);
/* Temporary remapping 200 BAUD to 3.2 mbps */
if (bps == 200)
bps = 3200000;
uport->uartclk = clk_get_rate(msm_uport->clk);
if (!uport->uartclk)
msm_hs_set_std_bps_locked(uport, bps);
else
msm_hs_set_bps_locked(uport, bps);
data = msm_hs_read(uport, UARTDM_MR2_ADDR);
data &= ~UARTDM_MR2_PARITY_MODE_BMSK;
/* set parity */
if (PARENB == (c_cflag & PARENB)) {
if (PARODD == (c_cflag & PARODD)) {
data |= ODD_PARITY;
} else if (CMSPAR == (c_cflag & CMSPAR)) {
data |= SPACE_PARITY;
} else {
data |= EVEN_PARITY;
}
}
/* Set bits per char */
data &= ~UARTDM_MR2_BITS_PER_CHAR_BMSK;
switch (c_cflag & CSIZE) {
case CS5:
data |= FIVE_BPC;
break;
case CS6:
data |= SIX_BPC;
break;
case CS7:
data |= SEVEN_BPC;