Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Jump to bottom

メモリのAXI接続 #29

Closed
pineapplehunter opened this issue Jun 12, 2022 · 2 comments
Closed

メモリのAXI接続 #29

pineapplehunter opened this issue Jun 12, 2022 · 2 comments
Labels
a: hardware FPGA実装に影響 d: intermediate 実装の難易度：中 feature 機能追加など
Projects
動作改善
Milestone
動作改善

Comments

@pineapplehunter
Copy link
Collaborator

What

メモリ接続をAXIに対応させると、Vivado上でBRAMを作って接続ができるようになるので実機でのテストがよりかんたんになる。

How

AXIの仕様を読み込んでインターフェイスを実装する。

Problems

AXIはかなり複雑な規格なので、まずはAXI Liteに対応させることから始めると良いかもしれない。
@pineapplehunter pineapplehunter added the feature 機能追加など label Jun 12, 2022
@pineapplehunter pineapplehunter added this to the 動作改善 milestone Jun 12, 2022
@pineapplehunter pineapplehunter added this to To do in 動作改善 Jul 5, 2022
@pineapplehunter pineapplehunter added the a: hardware FPGA実装に影響 label Nov 20, 2022
@pineapplehunter
Copy link
Collaborator Author

AXIの実装に対応したが、まだ原因不明のバグが多いので要デバッグ

@pineapplehunter pineapplehunter added the d: intermediate 実装の難易度：中 label Nov 20, 2022
@pineapplehunter
Copy link
Collaborator Author

ほとんど実装完了．
現在動作に問題はないが，loadが64bit単位でしか行えていない．

Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Assignees
No one assigned
Labels
a: hardware FPGA実装に影響 d: intermediate 実装の難易度：中 feature 機能追加など
Projects
動作改善
To do
Milestone
動作改善
Development

No branches or pull requests
1 participant
@pineapplehunter