insns-aarch64.go

package main

var (
	Insn_AArch64         map[string]string
	SIMDInsn_AArch64     map[string]string
	Cond_AArch64         map[string]string
	CondSetInsn_AArch64  []string
	CondSIMDInsn_AArch64 []string
)

func init() {
	Insn_AArch64 = map[string]string{
		"adc":     "Add with Carry",
		"add":     "Add",
		"adr":     "Address: PC-relative",
		"adrp":    "Address of 4KB Page: PC-relative",
		"and":     "Bitwise AND",
		"asr":     "Arithmetic Shift Right",
		"asrv":    "Arithmetic Shift Right Variable",
		"at":      "Address Translate",
		"b":       "Branch",
		"bfi":     "Bit Field Insert",
		"bfm":     "Bit Field Move",
		"bfxil":   "Bit Field Extract and Insert at Low end",
		"bic":     "Bit Clear",
		"bl":      "Branch with Link",
		"blr":     "Branch with Link to Register",
		"br":      "Branch to Register",
		"brk":     "Debug Breakpoint",
		"cbnz":    "Compare and Branch if Not Zero",
		"cbz":     "Compare and Branch if Zero",
		"ccmn":    "Conditional Compare Negative, Set condition flags",
		"ccmp":    "Conditional Compare, Set condition flags",
		"cinc":    "Conditional Increment",
		"cinv":    "Conditional Invert",
		"clrex":   "Clear Exclusive tag",
		"cls":     "Count Leading Sign bits",
		"clz":     "Count Leading Zero bits",
		"cmn":     "Compare Negative, Set condition flags",
		"cmp":     "Compare, Set condition flags",
		"cneg":    "Condition Negate",
		"crc32b":  "CRC32 checksum from Byte",
		"crc32h":  "CRC32 checksum from Half-word",
		"crc32w":  "CRC32 checksum from Word",
		"crc32x":  "CRC32 checksum from Double-word",
		"crc32cb": "CRC32C checksum from Byte",
		"crc32ch": "CRC32C checksum from Half-word",
		"crc32cw": "CRC32C checksum from Word",
		"crc32cx": "CRC32C checksum from Double-word",
		"csel":    "Condition Select",
		"cset":    "Condition Set",
		"csetm":   "Condition Set Mask",
		"csinc":   "Condition Select Increment",
		"csinv":   "Condition Select Inversion",
		"csneg":   "Condition Select Negation",
		"dc":      "Data Cache operation",
		"dcps1":   "Debug Switch to exception Level 1",
		"dcps2":   "Debug Switch to exception Level 2",
		"dcps3":   "Debug Switch to exception Level 3",
		"dmb":     "Data Memory Barrier",
		"drps":    "Debug Restore Processor State",
		"dsb":     "Data Synchronization Barrier",
		"eon":     "Exclusive OR NOT",
		"eor":     "Exclusive OR",
		"eret":    "Exception Return",
		"extr":    "Extract Register",
		"hint":    "Hint",
		"hlt":     "Halt: debug-mode breakpoint",
		"hvc":     "Hyper-Visor Call",
		"ic":      "Instruction Cache operation",
		"isb":     "Instruction Synchronization Barrier",
		"ldar":    "Load-Acquire Register",
		"ldarb":   "Load-Acquire Register Byte",
		"ldarh":   "Load-Acquire Register Half-word",
		"ldaxp":   "Load-Acquire Exclusive Pair of Registers",
		"ldaxr":   "Load-Acquire Exclusive Register",
		"ldaxrb":  "Load-Acquire Exclusive Register Byte",
		"ldaxrh":  "Load-Acquire Exclusive Register Half-word",
		"ldnp":    "Load Pair of Registers with Non-temporal hint",
		"ldp":     "Load Pair of Registers",
		"ldpsw":   "Load Pair of Registers Signed Word",
		"ldr":     "Load Register",
		"ldrb":    "Load Register Byte",
		"ldrh":    "Load Register Half-word",
		"ldrsb":   "Load Register Signed Byte",
		"ldrsh":   "Load Register Signed Half-word",
		"ldrsw":   "Load Register Signed Word",
		"ldtr":    "Load Register: Unprivileged",
		"ldtrb":   "Load Register Byte: Unprivileged",
		"ldtrh":   "Load Register Half-word: Unprivileged",
		"ldtrsb":  "Load Register Signed Byte: Unprivileged",
		"ldtrsh":  "Load Register Signed Half-word: Unprivileged",
		"ldtrsw":  "Load Register Signed Word: Unprivileged",
		"ldur":    "Load Register: Unscaled offset",
		"ldurb":   "Load Register Byte: Unscaled offset",
		"ldurh":   "Load Register Half-word: Unscaled offset",
		"ldursb":  "Load Register Signed Byte: Unscaled offset",
		"ldursh":  "Load Register Signed Half-word: Unscaled offset",
		"ldursw":  "Load Register Signed Word: Unscaled offset",
		"ldxp":    "Load Exclusive Pair of Registers",
		"ldxr":    "Load Exclusive Register",
		"ldxrb":   "Load Exclusive Register Byte",
		"ldxrh":   "Load Exclusive Register Half-word",
		"lsl":     "Logical Shift Left",
		"lslv":    "Logical Shift Left Variable",
		"lsr":     "Logical Shift Right",
		"lsrv":    "Logical Shift Right Variable",
		"madd":    "Multiply-Add",
		"mneg":    "Multiply-Negate",
		"mov":     "Move Register or constant",
		"movk":    "Move 16-bit immediate to Register",
		"movn":    "Move inverse of shifted 16-bit immediate to Register",
		"movz":    "Move shifted 16-bit immediate to Register",
		"mrc":     "Move Coprocessor Register to CPU",
		"mrs":     "Move from System Register",
		"msr":     "Move to System Register",
		"msub":    "Multiply-Subtract",
		"mul":     "Multiply",
		"mvn":     "Move Register with NOT",
		"neg":     "Negate",
		"ngc":     "Negate with Carry",
		"nop":     "No Operation",
		"orn":     "Bitwise OR with NOT",
		"orr":     "Bitwise OR",
		"prfm":    "Pre-Fetch Memory",
		"prfum":   "Pre-Fetch Memory: Unscaled offset",
		"rbit":    "Reverse Bit order",
		"ret":     "Return from subroutine",
		"rev":     "Reverse Bytes",
		"rev16":   "Reverse Bytes in 16-bit Half-words",
		"rev32":   "Reverse Bytes in 32-bit Words",
		"ror":     "Rotate Right",
		"rorv":    "Rotate Right Variable",
		"sbc":     "Subtract with Carry",
		"sbfiz":   "Signed Bit Field Insert in Zero",
		"sbfm":    "Signed Bit Field Move",
		"sbfx":    "Signed Bit Field Extract",
		"sdiv":    "Signed Divide",
		"sev":     "Send Event",
		"sevl":    "Send Event Locally",
		"smc":     "Secure Monitor Call",
		"smaddl":  "Signed Multiply-Add Long",
		"smnegl":  "Signed Multiply-Negate Long",
		"smsubl":  "Signed Multiply-Subtract Long",
		"smulh":   "Signed Multiply High",
		"smull":   "Signed Multiply Long",
		"stlr":    "Store-Release Register",
		"stlrb":   "Store-Release Register Byte",
		"stlrh":   "Store-Release Register Half-word",
		"stlxp":   "Store-Release Exclusive Pair of Registers",
		"stlxr":   "Store-Release Exclusive Register",
		"stlxrb":  "Store-Release Exclusive Register Byte",
		"stlxrh":  "Store-Release Exclusive Register Half-word",
		"stnp":    "Store Pair of Registers with Non-temporal hint",
		"stp":     "Store Pair of Registers",
		"str":     "Store Register",
		"strb":    "Store Register Byte",
		"strh":    "Store Register Half-word",
		"sttr":    "Store Register: Unprivileged",
		"sttrb":   "Store Register Byte: Unprivileged",
		"sttrh":   "Store Register Half-word: Unprivileged",
		"stur":    "Store Register: Unscaled offset",
		"sturb":   "Store Register Byte: Unscaled offset",
		"sturh":   "Store Register Half-word: Unscaled offset",
		"stxp":    "Store Exclusive Pair of Registers",
		"stxr":    "Store Exclusive Register",
		"stxrb":   "Store Exclusive Register Byte",
		"stxrh":   "Store Exclusive Register Half-word",
		"sub":     "Subtract",
		"svc":     "Super-Visor Call",
		"sxtb":    "Signed-Extend Byte",
		"sxth":    "Signed-Extend Half-word",
		"sxtw":    "Signed-Extend Word",
		"sys":     "System Instruction",
		"sysl":    "System Instruction with Result",
		"tbnz":    "Test Bit and Branch if Non-Zero",
		"tbz":     "Test Bit and Branch if Zero",
		"tlbi":    "TLB Invalidate",
		"tst":     "Test, Set condition flags",
		"ubfiz":   "Unsigned Bit Field Insert in Zero",
		"ubfm":    "Unsigned Bit Field Move",
		"ubfx":    "Unsigned Bit Field Extract",
		"udiv":    "Unsigned Divide",
		"umaddl":  "Unsigned Multiply-Add Long",
		"umnegl":  "Unsigned Multiply-Negate Long",
		"umsubl":  "Unsigned Multiply-Subtract Long",
		"umulh":   "Unsigned Multiply High",
		"umull":   "Unsigned Multiply Long",
		"uxtb":    "Unsigned-Extend Byte",
		"uxth":    "Unsigned-Extend Half-word",
		"wfe":     "Wait For Event",
		"wfi":     "Wait For Interrupt",
		"yield":   "Yield hint",
	}

	SIMDInsn_AArch64 = map[string]string{
		"abs":       "Absolute value of Vector",
		"add":       "Add Vector",
		"addhn":     "Add returning High Narrow",
		"addhn2":    "Add returning High Narrow",
		"addp":      "Add Pair",
		"addv":      "Add Vector",
		"aesd":      "AES Decryption",
		"aese":      "AES Encryption",
		"aesimc":    "AES Inverse Mix Columns",
		"aesmc":     "AES Mix Columns",
		"and":       "And Vector",
		"bic":       "Clear Bit in vector",
		"bif":       "Bitwise Insert if False",
		"bit":       "Bitwise Insert if True",
		"bsl":       "Bitwise Select",
		"cls":       "Count Leading Sign bits in vector",
		"clz":       "Count Leading Zero bits in vector",
		"cm":        "Compare Vector",
		"cmtst":     "Compare Vector Test Non-zero",
		"cnt":       "Population Count per byte",
		"dup":       "Duplicate Vector",
		"eor":       "Exclusive OR in Vector",
		"ext":       "Extract Vector",
		"fabd":      "Floating-point Absolute Difference",
		"fabs":      "Floating-point Absolute value",
		"fac":       "Floating-point Absolute Compare",
		"fadd":      "Floating-point Add",
		"faddp":     "Floating-point Add Pair",
		"fccmp":     "Floating-point Conditional Quiet Compare, Set condition flags",
		"fccmpe":    "Floating-point Conditional Signaling Compare, Set condition flags",
		"fcm":       "Floating-point Compare",
		"fcmp":      "Floating-point Quiet Compare",
		"fcmpe":     "Floating-point Signaling Compare",
		"fcsel":     "Floating-point Conditional Select",
		"fcvt":      "Floating-point Convert Precision",
		"fcvtas":    "Floating-point Convert to Signed Int, round to Nearest, ties Away",
		"fcvtau":    "Floating-point Convert to Unsigned Int, round to Nearest, ties Away",
		"fcvtl":     "Floating-point Convert to Higher Precision Long",
		"fcvtl2":    "Floating-point Convert to Higher Precision Long",
		"fcvtms":    "Floating-point Convert to Signed Int, round to Minus Inf.",
		"fcvtmu":    "Floating-point Convert to Unsigned Int, round to Minus Inf.",
		"fcvtn":     "Floating-point Convert to Lower Precision Long",
		"fcvtn2":    "Floating-point Convert to Lower Precision Long",
		"fcvtns":    "Floating-point Convert to Signed Int, round to Nearest",
		"fcvtnu":    "Floating-point Convert to Unsigned Int, round to Nearest",
		"fcvtps":    "Floating-point Convert to Signed Int, round to Positive Inf.",
		"fcvtpu":    "Floating-point Convert to Unsigned Int, round to Positive Inf",
		"fcvtxn":    "Floating-point Convert to Lower Precision Narrow, round to Odd",
		"fcvtxn2":   "Floating-point Convert to Lower Precision Narrow, round to Oodd",
		"fcvtzs":    "Floating-point Convert to Signed Int or Fixed-point, round to Zero",
		"fcvtzu":    "Floating-point Convert to Unsigned Int or Fixed-point, round to Zero",
		"fdiv":      "Floating-point Divide",
		"fmadd":     "Floating-point Multiply-Add",
		"fmax":      "Floating-point Maximum",
		"fmaxp":     "Floating-point Maximum Pair",
		"fmaxv":     "Floating-point Maximum across Vector",
		"fmaxnm":    "Floating-point Maximum Number",
		"fmaxnmp":   "Floating-point Maximum Number Pair",
		"fmaxnmv":   "Floating-point Maximum Number across Vector",
		"fmin":      "Floating-point Minimum",
		"fminp":     "Floating-point Minimum Pair",
		"fminv":     "Floating-point Minimum across Vector",
		"fminnm":    "Floating-point Minimum Number",
		"fminnmp":   "Floating-point Minimum Number Pair",
		"fminnmv":   "Floating-point Minimum Number across Vector",
		"fmla":      "Floating-point Multiply-Add to Accumulator",
		"fmls":      "Floating-point Multiply-Subtract to Accumulator",
		"fmov":      "Floating-point Move Register (w/o conversion) or Constant",
		"fmsub":     "Floating-point Multiply-Subtract",
		"fmul":      "Floating-point Multiply",
		"fmulx":     "Floating-point Multiply Extended",
		"fneg":      "Floating-point Negate",
		"fnmadd":    "Floating-point Negate Multiply-Add",
		"fnmsub":    "Floating-point Negate Multiply-Subtract",
		"fnmul":     "Floating-point Multiply-Negate",
		"frecpe":    "Floating-point Reciprocal Estimate",
		"frecps":    "Floating-point Reciprocal Step",
		"frecpx":    "Floating-point Reciprocal Exponent",
		"frinta":    "Floating-point Round to Integral Nearest (Ties Away)",
		"frinti":    "Floating-point Round to Integral",
		"frintm":    "Floating-point Round to Integral toward Minus Inf.",
		"frintn":    "Floating-point Round to Integral Nearest (Ties Even)",
		"frintp":    "Floating-point Round to Integral toward Positive Inf.",
		"frintx":    "Floating-point Round to Integral Exact",
		"frintz":    "Floating-point Round to Integral toward Zero",
		"frsqrte":   "Floating-point Reciprocal Square Root Estimate",
		"frsqrts":   "Floating-point Reciprocal Square Root Step",
		"fsqrt":     "Floating-point Square Root",
		"fsub":      "Floating-point Subtract",
		"ins":       "Insert vector",
		"ld1":       "Load 1-element structure",
		"ld1r":      "Load 1-element structure and Replicate",
		"ld2":       "Load 2-element structure",
		"ld2r":      "Load 2-element structure and Replicate",
		"ld3":       "Load 3-element structure",
		"ld3r":      "Load 3-element structure and Replicate",
		"ld4":       "Load 3-element structure",
		"ld4r":      "Load 3-element structure and Replicate",
		"ldnp":      "Load Pair with Non-temporal hint",
		"ldp":       "Load Pair",
		"ldr":       "Load Register",
		"ldur":      "Load Register: Unscaled offset",
		"mla":       "Multiply-Add to Accumulator",
		"mls":       "Multiply-Subtract to Accumulator",
		"mov":       "Move Vector",
		"movi":      "Move Immediate to Vector",
		"mul":       "Multiply Vector",
		"mvn":       "Bitwise NOT in Vector",
		"mvni":      "Move Inverted Immediate to Vector",
		"neg":       "Negate Vector",
		"not":       "Bitwise Not in Vector",
		"orn":       "Bitwise OR Not in Vector",
		"orr":       "Bitwise OR in Vector",
		"pmul":      "Polynomial Multiply",
		"pmull":     "Polynomial Multiply Long",
		"pmull2":    "Polynomial Multiply Long",
		"raddhn":    "Rounding Add returning High Narrow",
		"raddhn2":   "Rounding Add returning High Narrow",
		"rbit":      "Reverse Bit order in Vector",
		"rev16":     "Reverse Bytes in 16-bit Half-words in Vector",
		"rev32":     "Reverse Bytes in 32-bit Words in Vector",
		"rev64":     "Reverse Bytes in 64-bit Double-words in Vector",
		"rshrn":     "Rounding Shift Right Narrow",
		"rshrn2":    "Rounding Shift Right Narrow",
		"rsubhn":    "Rounding Subtract returing High Narrow",
		"rsubhn2":   "Rounding Subtract returing High Narrow",
		"saba":      "Signed Absolute Difference and Accumulate",
		"sabal":     "Signed Absolute Difference and Accumulate Long",
		"sabal2":    "Signed Absolute Difference and Accumulate Long",
		"sabd":      "Signed Absolute Difference",
		"sabdl":     "Signed Absolute Difference Long",
		"sabdl2":    "Signed Absolute Difference Long",
		"sadalp":    "Signed Add and Accumulate Long Pair",
		"saddl":     "Signed Add Long",
		"saddl2":    "Signed Add Long",
		"saddw":     "Signed Add Wide",
		"saddw2":    "Signed Add Wide",
		"scvtf":     "Signed Convert to Floating-point",
		"sha1c":     "SHA1 hash Update",
		"sha1h":     "SHA1 fixed Rotate",
		"sha1m":     "SHA1 hash Update (Majority)",
		"sha1p":     "SHA1 hash Update (Parity)",
		"sha1su0":   "SHA1 Schedule Update 0",
		"sha1su1":   "SHA1 Schedule Update 1",
		"sha256h":   "SHA256 hash Update (part 1)",
		"sha256h2":  "SHA256 hash Update (part 2)",
		"sha256su0": "SHA256 Schedule Update 0",
		"sha256su1": "SHA256 Schedule Update 1",
		"shadd":     "Signed Halving Add",
		"shl":       "Shift Left",
		"shll":      "Shift Left Long",
		"shll2":     "Shift Left Long",
		"shrn":      "Shift Right Narrow",
		"shrn2":     "Shift Right Narrow",
		"shsub":     "Signed Halving Subtract",
		"sli":       "Shift Left and Insert",
		"smax":      "Signed Maximum",
		"smaxp":     "Signed Maximum Pair",
		"smaxv":     "Signed Maximum across Vector",
		"smin":      "Signed Minimum",
		"sminp":     "Signed Minimum Pair",
		"sminv":     "Signed Minimum across Vector",
		"smlal":     "Signed Multiply-Add Long",
		"smlal2":    "Signed Multiply-Add Long",
		"smlsl":     "Signed Multiply-Subtract Long",
		"smlsl2":    "Signed Multiply-Subtract Long",
		"smov":      "Signed Move Vector",
		"smull":     "Signed Multiply Long",
		"smull2":    "Signed Multiply Long",
		"sqabs":     "Signed Saturating Absolute value",
		"sqadd":     "Signed Saturating Add",
		"sqdmlal":   "Signed Saturating Doubling Multiply-Add Long",
		"sqdmlal2":  "Signed Saturating Doubling Multiply-Add Long",
		"sqdmlsl":   "Signed Saturating Doubling Multiply-Subtract Long",
		"sqdmlsl2":  "Signed Saturating Doubling Multiply-Subtract Long",
		"sqdmulh":   "Signed Saturating Doubling Multiply returning High-half",
		"sqdmull":   "Signed Saturating Doubling Multiply Long",
		"sqdmull2":  "Signed Saturating Doubling Multiply Long",
		"sqneg":     "Signed Saturating Negate",
		"sqrdmulh":  "Signed Saturating Rounding Doubling Multiply returning High-half",
		"sqrshl":    "Signed Saturating Rounding Shift Left",
		"sqrshrn":   "Signed Saturating Rounding Shift Right Narrow",
		"sqrshrn2":  "Signed Saturating Rounding Shift Right Narrow",
		"sqrshrun":  "Signed Saturating Rounding Shift Right Unsigned Narrow",
		"sqrshrun2": "Signed Saturating Rounding Shift Right Unsigned Narrow",
		"sqshl":     "Signed Saturating Shift Left",
		"sqshlu":    "Signed Saturating Shift Left Unsigned",
		"sqshrn":    "Signed Saturating Shift Right Narrow",
		"sqshrn2":   "Signed Saturating Shift Right Narrow",
		"sqshrun":   "Signed Saturating Shift Right Unsigned Narrow",
		"sqshrun2":  "Signed Saturating Shift Right Unsigned Narrow",
		"sqsub":     "Signed Saturating Subtract",
		"sqxtn":     "Signed Saturating Extract Narrow",
		"sqxtn2":    "Signed Saturating Extract Narrow",
		"sqxtun":    "Signed Saturating Extract Unsigned Narrow",
		"sqxtun2":   "Signed Saturating Extract Unsigned Narrow",
		"srhadd":    "Signed Rounding Halving Add",
		"sri":       "Shift Right and Insert",
		"srshl":     "Signed Rounding Shift Left",
		"srshr":     "Signed Rounding Shift Right",
		"srsra":     "Signed Rounding Shift Right and Accumulate",
		"sshl":      "Signed Shift Left",
		"sshll":     "Signed Shift Left Long",
		"sshll2":    "Signed Shift Left Long",
		"sshr":      "Signed Shift Right",
		"ssra":      "Signed Shift Right and Accumulate",
		"ssubl":     "Signed Subtract Long",
		"ssubl2":    "Signed Subtract Long",
		"ssubw":     "Signed Subtract Wide",
		"ssubw2":    "Signed Subtract Wide",
		"st1":       "Store 1-element structure",
		"st2":       "Store 2-element structure",
		"st3":       "Store 3-element structure",
		"st4":       "Store 4-element structure",
		"stnp":      "Store Pair with Non-temporal hint",
		"stp":       "Store Pair",
		"str":       "Store Register",
		"stur":      "Store Register: Unscaled offset",
		"sub":       "Subtract Vector",
		"subhn":     "Subtract returning High Narrow",
		"subhn2":    "Subtract returning High Narrow",
		"suqadd":    "Signed Saturating Accumulate of Unsigned value",
		"sxtl":      "Signed Extend Long",
		"tbl":       "Table Vector Lookup",
		"tbx":       "Table Vector Lookup Extension",
		"trn1":      "Transpose Vectors: Primary",
		"trn2":      "Transpose Vectors: Secondary",
		"uaba":      "Unsigned Absolute Difference and Accumulate",
		"uabal":     "Unsigned Absolute Difference and Accumulate Long",
		"uabal2":    "Unsigned Absolute Difference and Accumulate Long",
		"uabd":      "Unsigned Absolute Difference",
		"uabdl":     "Unsigned Absolute Difference Long",
		"uabdl2":    "Unsigned Absolute Difference Long",
		"uabdlp":    "Unsigned Absolute Difference Long Pair",
		"uaddl":     "Unsigned Add Long",
		"uaddl2":    "Unsigned Add Long",
		"uaddlp":    "Unsigned Add Long Pair",
		"uaddlv":    "Unsigned Add Long across Vector",
		"uaddw":     "Unsigned Add Wide",
		"uaddw2":    "Unsigned Add Wide",
		"ucvtf":     "Unsigned Convert to Floating-point",
		"uhadd":     "Unsigned Halving Add",
		"uhsub":     "Unsigned Halving Subtract",
		"umax":      "Unsigned Maximum",
		"umaxp":     "Unsigned Maximum Pair",
		"umaxv":     "Unsigned Maximum across Vector",
		"umin":      "Unsigned Minimum",
		"uminp":     "Unsigned Minimum Pair",
		"uminv":     "Unsigned Minimum across Vector",
		"umlal":     "Unsigned Multiply-Add Long",
		"umlal2":    "Unsigned Multiply-Add Long",
		"umlsl":     "Unsigned Multiply-Subtract Long",
		"umlsl2":    "Unsigned Multiply-Subtract Long",
		"umov":      "Unsigned Move Vector",
		"umull":     "Unsigned Multiply Long",
		"umull2":    "Unsigned Multiply Long",
		"uqadd":     "Unsigned Saturating Add",
		"uqrshl":    "Unsigned Saturating Rounding Shift Left",
		"uqrshrn":   "Unsigned Saturating Rounding Shift Right Narrow",
		"uqrshrn2":  "Unsigned Saturating Rounding Shift Right Narrow",
		"uqshl":     "Unsigned Saturating Shift Left",
		"uqsub":     "Unsigned Saturating Subtract",
		"uqxtn":     "Unsigned Saturating Extract Narrow",
		"uqxtn2":    "Unsigned Saturating Extract Narrow",
		"urecpe":    "Unsigned Reciprocal Estimate",
		"urhadd":    "Unsigned Rounding Halving Add",
		"urshl":     "Unsigned Rounding Shift Left",
		"urshr":     "Unsigned Rounding Shift Right",
		"ursqrte":   "Unsigned Reciprocal Square Root Estimate",
		"ursra":     "Unsigned Rounding Shift Right and Accumulate",
		"ushl":      "Unsigned Shift Left",
		"ushll":     "Unsigned Shift Left Long",
		"ushll2":    "Unsigned Shift Left Long",
		"ushr":      "Unsigned Shift Right",
		"usqadd":    "Unsigned Saturating Accumulate of Signed value",
		"usra":      "Unsigned Shift Right and Accumulate",
		"usubl":     "Unsigned Subtract Long",
		"usubl2":    "Unsigned Subtract Long",
		"usubw":     "Unsigned Subtract Wide",
		"usubw2":    "Unsigned Subtract Wide",
		"uxtl":      "Unsigned Extend Long",
		"uzp1":      "Unzip vectors: Primary",
		"uzp2":      "Unzip vectors: Secondary",
		"xtn":       "Extract Narrow",
		"xtn2":      "Extract Narrow",
		"zip1":      "Zip vectors: Primary",
		"zip2":      "Zip vectors: Secondary",
	}

	Cond_AArch64 = map[string]string{
		"eq": "Equal",
		"ne": "Not Equal",
		"cs": "Higher or Same",
		"cc": "Lower",
		"mi": "Minus",
		"pl": "Plus",
		"vs": "Overflow",
		"vc": "No Overflow",
		"hi": "Higher",
		"hs": "Higher or Same",
		"lo": "Lower",
		"ls": "Lower or Same",
		"ae": "Above or Equal",
		"ge": "Greater Than or Equal",
		"gt": "Greater Than",
		"lt": "Less Than",
		"le": "Less Than or Equal",
		"al": "Always",
	}

	// instructions have 's' suffix
	CondSetInsn_AArch64 = []string{"add", "adc", "and", "neg", "ngc", "sbc", "sub"}

	// instructions have condition suffixes (like 'gt')
	CondSIMDInsn_AArch64 = []string{"cm", "fac", "fcm"}
}