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6502_func_test.lst
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6502_func_test.lst
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AS65 Assembler for R6502 [1.42]. Page 1
-------------------------- 6502_functional_test.asm --------------------------
6010 lines read, no errors in pass 1.
;
; 6 5 0 2 F U N C T I O N A L T E S T
;
; Copyright (C) 2012-2015 Klaus Dormann
;
; This program is free software: you can redistribute
; it under the terms of the GNU General Public License
; the Free Software Foundation, either version 3 of th
; (at your option) any later version.
;
; This program is distributed in the hope that it will
; but WITHOUT ANY WARRANTY; without even the implied w
; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
; GNU General Public License for more details.
;
; You should have received a copy of the GNU General P
; along with this program. If not, see <http://www.gn
; This program is designed to test all opcodes of a 65
; addressing modes with focus on propper setting of th
; register bits.
;
; version 21-oct-2015
; contact info at http://2m5.de or email K@2m5.de
;
; assembled with AS65 from http://www.kingswood-consul
; command line switches: -l -m -s2 -w -h0
; | | | | no page headers
; | | | wide listing (133
; | | write intel hex file i
; | expand macros in listing
; generate pass2 listing
;
; No IO - should be run from a monitor with access to
; To run load intel hex image with a load command, tha
; (code_segment) and enter a go command.
; Loop on program counter determines error or successf
; Check listing for relevant traps (jump/branch *).
; Please note that in early tests some instructions wi
; they are actually tested!
;
; RESET, NMI or IRQ should not occur and will be trapp
; Tests documented behavior of the original NMOS 6502
; opcodes. Additional opcodes of newer versions of the
; not be tested. Decimal ops will only be tested with
; N V Z flags will be ignored.
;
; Debugging hints:
; Most of the code is written sequentially. if you
; immediately preceeding code for the instruction to
; tested first, flags are checked second by pushing
; pulling them to the accumulator after the result w
; flags are no longer valid for the tested instructi
; If the tested instruction was indexed, the relev
; also be checked. Opposed to the flags, X and Y reg
;
; versions:
; 28-jul-2012 1st version distributed for testing
; 29-jul-2012 fixed references to location 0, now #
; added license - GPLv3
; 30-jul-2012 added configuration options
; 01-aug-2012 added trap macro to allow user to cha
; 01-dec-2012 fixed trap in branch field must be a
; 02-mar-2013 fixed PLA flags not tested
; 19-jul-2013 allowed ROM vectors to be loaded when
; added test sequence check to detect i
; 23-jul-2013 added RAM integrity check option
; 16-aug-2013 added error report to standard output
; 13-dec-2014 added binary/decimal opcode table swi
; 14-dec-2014 improved relative address test
; 23-aug-2015 added option to disable self modifyin
; 24-aug-2015 all self modifying immediate opcodes
; added small branch offset pretest
; 21-oct-2015 added option to disable decimal mode
; C O N F I G U R A T I O N
;ROM_vectors writable (0=no, 1=yes)
;if ROM vectors can not be used interrupts will not be
;as a consequence BRK can not be tested but will be em
0001 = ROM_vectors = 1
;load_data_direct (0=move from code segment, 1=load di
;loading directly is preferred but may not be supporte
;0 produces only consecutive object code, 1 is not sui
0001 = load_data_direct = 1
;I_flag behavior (0=force enabled, 1=force disabled, 2
;change) 2 requires extra code and is not recommended.
;tested if you allow changing the interrupt status (I_
0003 = I_flag = 3
;configure memory - try to stay away from memory used
;zero_page memory start address, $50 (80) consecutive
; add 2 if I_flag = 2
000a = zero_page = $a
;data_segment memory start address, $6A (106) consecut
0200 = data_segment = $200
if (data_segment & $ff) != 0
ERROR ERROR ERROR low byte of data_segment MUS
endif
;code_segment memory start address, 13kB of consecutiv
; add 2.5 kB if I_fl
0400 = code_segment = $400
;self modifying code may be disabled to allow running
;0=part of the code is self modifying and must reside
;1=tests disabled: branch range
0000 = disable_selfmod = 0
;report errors through I/O channel (0=use standard sel
;report.i65 as I/O channel, add 3.5 kB)
0000 = report = 0
;RAM integrity test option. Checks for undesired RAM w
;set lowest non RAM or RAM mirror address page (-1=dis
;leave disabled if a monitor, OS or background interru
ffff = ram_top = -1
;disable test decimal mode ADC & SBC, 0=enable, 1=disa
;2=disable including decimal flag in processor status
0000 = disable_decimal = 0
noopt ;do not take shortcuts
;macros for error & success traps to allow user modifi
;example:
;trap macro
; jsr my_error_handler
; endm
;trap_eq macro
; bne skip\?
; trap ;failed equal (zero)
;skip\?
; endm
;
; my_error_handler should pop the calling address from
; putting larger portions of code (more than 3 bytes)
; may lead to branch range problems for some tests.
if report = 0
trap macro
jmp * ;failed anyway
endm
trap_eq macro
beq * ;failed equal (zero)
endm
trap_ne macro
bne * ;failed not equal (non zero)
endm
trap_cs macro
bcs * ;failed carry set
endm
trap_cc macro
bcc * ;failed carry clear
endm
trap_mi macro
bmi * ;failed minus (bit 7 set)
endm
trap_pl macro
bpl * ;failed plus (bit 7 clear)
endm
trap_vs macro
bvs * ;failed overflow set
endm
trap_vc macro
bvc * ;failed overflow clear
endm
; please observe that during the test the stack gets i
; therefore a RTS inside the success macro is not poss
success macro
jmp * ;test passed, no errors
endm
endif
if report = 1
trap macro
jsr report_error
endm
trap_eq macro
bne skip\?
trap ;failed equal (zero)
skip\?
endm
trap_ne macro
beq skip\?
trap ;failed not equal (non zero)
skip\?
endm
trap_cs macro
bcc skip\?
trap ;failed carry set
skip\?
endm
trap_cc macro
bcs skip\?
trap ;failed carry clear
skip\?
endm
trap_mi macro
bpl skip\?
trap ;failed minus (bit 7 set)
skip\?
endm
trap_pl macro
bmi skip\?
trap ;failed plus (bit 7 clear)
skip\?
endm
trap_vs macro
bvc skip\?
trap ;failed overflow set
skip\?
endm
trap_vc macro
bvs skip\?
trap ;failed overflow clear
skip\?
endm
; please observe that during the test the stack gets i
; therefore a RTS inside the success macro is not poss
success macro
jsr report_success
endm
endif
0001 = carry equ %00000001 ;flag bits in status
0002 = zero equ %00000010
0004 = intdis equ %00000100
0008 = decmode equ %00001000
0010 = break equ %00010000
0020 = reserv equ %00100000
0040 = overfl equ %01000000
0080 = minus equ %10000000
0001 = fc equ carry
0002 = fz equ zero
0003 = fzc equ carry+zero
0040 = fv equ overfl
0042 = fvz equ overfl+zero
0080 = fn equ minus
0081 = fnc equ minus+carry
0082 = fnz equ minus+zero
0083 = fnzc equ minus+zero+carry
00c0 = fnv equ minus+overfl
0030 = fao equ break+reserv ;bits always on after PHP,
0034 = fai equ fao+intdis ;+ forced interrupt disabl
0038 = faod equ fao+decmode ;+ ignore decimal
003c = faid equ fai+decmode ;+ ignore decimal
00ff = m8 equ $ff ;8 bit mask
00fb = m8i equ $ff&~intdis ;8 bit mask - interrupt di
;macros to allow masking of status bits.
;masking test of decimal bit
;masking of interrupt enable/disable on load and compa
;masking of always on bits after PHP or BRK (unused &
if disable_decimal < 2
if I_flag = 0
load_flag macro
lda #\1&m8i ;force enable interrup
endm
cmp_flag macro
cmp #(\1|fao)&m8i ;I_flag is always enab
endm
eor_flag macro
eor #(\1&m8i|fao) ;mask I, invert expect
endm
endif
if I_flag = 1
load_flag macro
lda #\1|intdis ;force disable interru
endm
cmp_flag macro
cmp #(\1|fai)&m8 ;I_flag is always disa
endm
eor_flag macro
eor #(\1|fai) ;invert expected flags
endm
endif
if I_flag = 2
load_flag macro
lda #\1
ora flag_I_on ;restore I-flag
and flag_I_off
endm
cmp_flag macro
eor flag_I_on ;I_flag is never chang
cmp #(\1|fao)&m8i ;expected flags + alwa
endm
eor_flag macro
eor flag_I_on ;I_flag is never chang
eor #(\1&m8i|fao) ;mask I, invert expect
endm
endif
if I_flag = 3
load_flag macro
lda #\1 ;allow test to change
endm
cmp_flag macro
cmp #(\1|fao)&m8 ;expected flags + alwa
endm
eor_flag macro
eor #\1|fao ;invert expected flags
endm
endif
else
if I_flag = 0
load_flag macro
lda #\1&m8i ;force enable interrup
endm
cmp_flag macro
ora #decmode ;ignore decimal mode b
cmp #(\1|faod)&m8i ;I_flag is always enab
endm
eor_flag macro
ora #decmode ;ignore decimal mode b
eor #(\1&m8i|faod) ;mask I, invert expect
endm
endif
if I_flag = 1
load_flag macro
lda #\1|intdis ;force disable interru
endm
cmp_flag macro
ora #decmode ;ignore decimal mode b
cmp #(\1|faid)&m8 ;I_flag is always disa
endm
eor_flag macro
ora #decmode ;ignore decimal mode b
eor #(\1|faid) ;invert expected flags
endm
endif
if I_flag = 2
load_flag macro
lda #\1
ora flag_I_on ;restore I-flag
and flag_I_off
endm
cmp_flag macro
eor flag_I_on ;I_flag is never chang
ora #decmode ;ignore decimal mode b
cmp #(\1|faod)&m8i ;expected flags + alwa
endm
eor_flag macro
eor flag_I_on ;I_flag is never chang
ora #decmode ;ignore decimal mode b
eor #(\1&m8i|faod) ;mask I, invert expect
endm
endif
if I_flag = 3
load_flag macro
lda #\1 ;allow test to change
endm
cmp_flag macro
ora #decmode ;ignore decimal mode b
cmp #(\1|faod)&m8 ;expected flags + alwa
endm
eor_flag macro
ora #decmode ;ignore decimal mode b
eor #\1|faod ;invert expected flags
endm
endif
endif
;macros to set (register|memory|zeropage) & status
set_stat macro ;setting flags in the processo
load_flag \1
pha ;use stack to load status
plp
endm
set_a macro ;precharging accu & status
load_flag \2
pha ;use stack to load status
lda #\1 ;precharge accu
plp
endm
set_x macro ;precharging index & status
load_flag \2
pha ;use stack to load status
ldx #\1 ;precharge index x
plp
endm
set_y macro ;precharging index & status
load_flag \2
pha ;use stack to load status
ldy #\1 ;precharge index y
plp
endm
set_ax macro ;precharging indexed accu & im
load_flag \2
pha ;use stack to load status
lda \1,x ;precharge accu
plp
endm
set_ay macro ;precharging indexed accu & im
load_flag \2
pha ;use stack to load status
lda \1,y ;precharge accu
plp
endm
set_z macro ;precharging indexed zp & imme
load_flag \2
pha ;use stack to load status
lda \1,x ;load to zeropage
sta zpt
plp
endm
set_zx macro ;precharging zp,x & immediate
load_flag \2
pha ;use stack to load status
lda \1,x ;load to indexed zeropage
sta zpt,x
plp
endm
set_abs macro ;precharging indexed memory &
load_flag \2
pha ;use stack to load status
lda \1,x ;load to memory
sta abst
plp
endm
set_absx macro ;precharging abs,x & immediate
load_flag \2
pha ;use stack to load status
lda \1,x ;load to indexed memory
sta abst,x
plp
endm
;macros to test (register|memory|zeropage) & status &
tst_stat macro ;testing flags in the processo
php ;save status
pla ;use stack to retrieve status
pha
cmp_flag \1
trap_ne
plp ;restore status
endm
tst_a macro ;testing result in accu & flag
php ;save flags
cmp #\1 ;test result
trap_ne
pla ;load status
pha
cmp_flag \2
trap_ne
plp ;restore status
endm
tst_x macro ;testing result in x index & f
php ;save flags
cpx #\1 ;test result
trap_ne
pla ;load status
pha
cmp_flag \2
trap_ne
plp ;restore status
endm
tst_y macro ;testing result in y index & f
php ;save flags
cpy #\1 ;test result
trap_ne
pla ;load status
pha
cmp_flag \2
trap_ne
plp ;restore status
endm
tst_ax macro ;indexed testing result in acc
php ;save flags
cmp \1,x ;test result
trap_ne
pla ;load status
eor_flag \3
cmp \2,x ;test flags
trap_ne ;
endm
tst_ay macro ;indexed testing result in acc
php ;save flags
cmp \1,y ;test result
trap_ne ;
pla ;load status
eor_flag \3
cmp \2,y ;test flags
trap_ne
endm
tst_z macro ;indexed testing result in zp
php ;save flags
lda zpt
cmp \1,x ;test result
trap_ne
pla ;load status
eor_flag \3
cmp \2,x ;test flags
trap_ne
endm
tst_zx macro ;testing result in zp,x & flag
php ;save flags
lda zpt,x
cmp \1,x ;test result
trap_ne
pla ;load status
eor_flag \3
cmp \2,x ;test flags
trap_ne
endm
tst_abs macro ;indexed testing result in mem
php ;save flags
lda abst
cmp \1,x ;test result
trap_ne
pla ;load status
eor_flag \3
cmp \2,x ;test flags
trap_ne
endm
tst_absx macro ;testing result in abs,x & fla
php ;save flags
lda abst,x
cmp \1,x ;test result
trap_ne
pla ;load status
eor_flag \3
cmp \2,x ;test flags
trap_ne
endm
; RAM integrity test
; verifies that none of the previous tests has alter
; designated write areas.
; uses zpt word as indirect pointer, zpt+2 word as c
if ram_top > -1
check_ram macro
cld
lda #0
sta zpt ;set low byte of indirect
sta zpt+3 ;checksum high byte
if disable_selfmod = 0
sta range_adr ;reset self modifying code
endif
clc
ldx #zp_bss-zero_page ;zeropage - write te
ccs3\? adc zero_page,x
bcc ccs2\?
inc zpt+3 ;carry to high byte
clc
ccs2\? inx
bne ccs3\?
ldx #hi(abs1) ;set high byte of indirect
stx zpt+1
ldy #lo(abs1) ;data after write & execut
ccs5\? adc (zpt),y
bcc ccs4\?
inc zpt+3 ;carry to high byte
clc
ccs4\? iny
bne ccs5\?
inx ;advance RAM high address
stx zpt+1
cpx #ram_top
bne ccs5\?
sta zpt+2 ;checksum low is
cmp ram_chksm ;checksum low expected
trap_ne ;checksum mismatch
lda zpt+3 ;checksum high is
cmp ram_chksm+1 ;checksum high expected
trap_ne ;checksum mismatch
endm
else
check_ram macro
;RAM check disabled - RAM size not set
endm
endif
next_test macro ;make sure, tests don't ju
lda test_case ;previous test
cmp #test_num
trap_ne ;test is out of sequence
test_num = test_num + 1
lda #test_num ;*** next tests' number
sta test_case
;check_ram ;uncomment to find altere
endm
if load_data_direct = 1
data
else
bss ;uninitialized segment, co
endif
0000 = org 0 ;edited to load from 0x0000 (w
0000 : 00000000000000.. ds zero_page ;see above (this line added)
;break test interrupt save
000a : 00 irq_a ds 1 ;a register
000b : 00 irq_x ds 1 ;x register
if I_flag = 2
;masking for I bit in status
flag_I_on ds 1 ;or mask to load flags
flag_I_off ds 1 ;and mask to load flags
endif
000c : zpt ;5 bytes store/modify test
;add/subtract operand generation and result/flag predi
000c : 00 adfc ds 1 ;carry flag before op
000d : 00 ad1 ds 1 ;operand 1 - accumulator
000e : 00 ad2 ds 1 ;operand 2 - memory / imme
000f : 00 adrl ds 1 ;expected result bits 0-7
0010 : 00 adrh ds 1 ;expected result bit 8 (ca
0011 : 00 adrf ds 1 ;expected flags NV0000ZC (
0012 : 00 sb2 ds 1 ;operand 2 complemented fo
0013 : zp_bss
0013 : c3824100 zp1 db $c3,$82,$41,0 ;test patterns for LDx BIT
0017 : 7f zp7f db $7f ;test pattern for compare
;logical zeropage operands
0018 : 001f7180 zpOR db 0,$1f,$71,$80 ;test pattern for OR
001c : 0fff7f80 zpAN db $0f,$ff,$7f,$80 ;test pattern for AND
0020 : ff0f8f8f zpEO db $ff,$0f,$8f,$8f ;test pattern for EOR
;indirect addressing pointers
0024 : 1702 ind1 dw abs1 ;indirect pointer to patte
0026 : 1802 dw abs1+1
0028 : 1902 dw abs1+2
002a : 1a02 dw abs1+3
002c : 1b02 dw abs7f
002e : 1f01 inw1 dw abs1-$f8 ;indirect pointer for wrap
0030 : 0302 indt dw abst ;indirect pointer to store
0032 : 0402 dw abst+1
0034 : 0502 dw abst+2
0036 : 0602 dw abst+3
0038 : 0b01 inwt dw abst-$f8 ;indirect pointer for wrap
003a : 4e02 indAN dw absAN ;indirect pointer to AND p
003c : 4f02 dw absAN+1
003e : 5002 dw absAN+2
0040 : 5102 dw absAN+3
0042 : 5202 indEO dw absEO ;indirect pointer to EOR p
0044 : 5302 dw absEO+1
0046 : 5402 dw absEO+2
0048 : 5502 dw absEO+3
004a : 4a02 indOR dw absOR ;indirect pointer to OR pa
004c : 4b02 dw absOR+1
004e : 4c02 dw absOR+2
0050 : 4d02 dw absOR+3
;add/subtract indirect pointers
0052 : 0302 adi2 dw ada2 ;indirect pointer to opera
0054 : 0402 sbi2 dw sba2 ;indirect pointer to compl
0056 : 0401 adiy2 dw ada2-$ff ;with offset for indirect
0058 : 0501 sbiy2 dw sba2-$ff
005a : zp_bss_end
0200 = org data_segment
0200 : 00 test_case ds 1 ;current test number
0201 : 0000 ram_chksm ds 2 ;checksum for RAM integrit
;add/subtract operand copy - abs tests write area
0203 : abst ;5 bytes store/modify test
0203 : 00 ada2 ds 1 ;operand 2
0204 : 00 sba2 ds 1 ;operand 2 complemented fo
0205 : 000000 ds 3 ;fill remaining bytes
0208 : data_bss
if load_data_direct = 1
0208 : 2900 ex_andi and #0 ;execute immediate opcodes
020a : 60 rts
020b : 4900 ex_eori eor #0 ;execute immediate opcodes
020d : 60 rts
020e : 0900 ex_orai ora #0 ;execute immediate opcodes
0210 : 60 rts
0211 : 6900 ex_adci adc #0 ;execute immediate opcodes
0213 : 60 rts
0214 : e900 ex_sbci sbc #0 ;execute immediate opcodes
0216 : 60 rts
else
ex_andi ds 3
ex_eori ds 3
ex_orai ds 3
ex_adci ds 3
ex_sbci ds 3
endif
0217 : c3824100 abs1 db $c3,$82,$41,0 ;test patterns for LDx BIT
021b : 7f abs7f db $7f ;test pattern for compare
;loads
021c : 80800002 fLDx db fn,fn,0,fz ;expected flags for load
;shifts
0220 : rASL ;expected result ASL & ROL
0220 : 86048200 rROL db $86,$04,$82,0 ; "
0224 : 87058301 rROLc db $87,$05,$83,1 ;expected result ROL +carr
0228 : rLSR ;expected result LSR & ROR
0228 : 61412000 rROR db $61,$41,$20,0 ; "
022c : e1c1a080 rRORc db $e1,$c1,$a0,$80 ;expected result ROR +carr
0230 : fASL ;expected flags for shifts
0230 : 81018002 fROL db fnc,fc,fn,fz ;no carry in
0234 : 81018000 fROLc db fnc,fc,fn,0 ;carry in
0238 : fLSR
0238 : 01000102 fROR db fc,0,fc,fz ;no carry in
023c : 81808180 fRORc db fnc,fn,fnc,fn ;carry in
;increments (decrements)
0240 : 7f80ff0001 rINC db $7f,$80,$ff,0,1 ;expected result for INC/D
0245 : 0080800200 fINC db 0,fn,fn,fz,0 ;expected flags for INC/DE
;logical memory operand
024a : 001f7180 absOR db 0,$1f,$71,$80 ;test pattern for OR
024e : 0fff7f80 absAN db $0f,$ff,$7f,$80 ;test pattern for AND
0252 : ff0f8f8f absEO db $ff,$0f,$8f,$8f ;test pattern for EOR
;logical accu operand
0256 : 00f11f00 absORa db 0,$f1,$1f,0 ;test pattern for OR
025a : f0ffffff absANa db $f0,$ff,$ff,$ff ;test pattern for AND
025e : fff0f00f absEOa db $ff,$f0,$f0,$0f ;test pattern for EOR
;logical results
0262 : 00ff7f80 absrlo db 0,$ff,$7f,$80
0266 : 02800080 absflo db fz,fn,0,fn
026a : data_bss_end
code
0400 = org code_segment
0400 : d8 start cld
0401 : a2ff ldx #$ff
0403 : 9a txs
0404 : a900 lda #0 ;*** test 0 = initialize
0406 : 8d0002 sta test_case
0000 = test_num = 0
;stop interrupts before initializing BSS
if I_flag = 1
sei
endif
;initialize I/O for report channel
if report = 1
jsr report_init
endif
;pretest small branch offset
0409 : a205 ldx #5
040b : 4c3304 jmp psb_test
040e : psb_bwok
040e : a005 ldy #5
0410 : d008 bne psb_forw
trap ;branch should be taken
0412 : 4c1204 > jmp * ;failed anyway
0415 : 88 dey ;forward landing zone
0416 : 88 dey
0417 : 88 dey
0418 : 88 dey
0419 : 88 dey
041a : psb_forw
041a : 88 dey
041b : 88 dey
041c : 88 dey
041d : 88 dey
041e : 88 dey
041f : f017 beq psb_fwok
trap ;forward offset
0421 : 4c2104 > jmp * ;failed anyway
0424 : ca dex ;backward landing zone
0425 : ca dex
0426 : ca dex
0427 : ca dex
0428 : ca dex
0429 : psb_back
0429 : ca dex
042a : ca dex
042b : ca dex
042c : ca dex
042d : ca dex
042e : f0de beq psb_bwok
trap ;backward offset
0430 : 4c3004 > jmp * ;failed anyway
0433 : psb_test
0433 : d0f4 bne psb_back
trap ;branch should be taken
0435 : 4c3504 > jmp * ;failed anyway
0438 : psb_fwok
;initialize BSS segment
if load_data_direct != 1
ldx #zp_end-zp_init-1
ld_zp lda zp_init,x
sta zp_bss,x
dex
bpl ld_zp
ldx #data_end-data_init-1
ld_data lda data_init,x
sta data_bss,x
dex
bpl ld_data
if ROM_vectors = 1
ldx #5
ld_vect lda vec_init,x
sta vec_bss,x
dex
bpl ld_vect
endif
endif
;retain status of interrupt flag
if I_flag = 2
php
pla
and #4 ;isolate flag
sta flag_I_on ;or mask
eor #lo(~4) ;reverse
sta flag_I_off ;and mask
endif
;generate checksum for RAM integrity test
if ram_top > -1
lda #0
sta zpt ;set low byte of indirect poin
sta ram_chksm+1 ;checksum high byte
if disable_selfmod = 0
sta range_adr ;reset self modifying code
endif
clc
ldx #zp_bss-zero_page ;zeropage - write test a
gcs3 adc zero_page,x
bcc gcs2
inc ram_chksm+1 ;carry to high byte
clc
gcs2 inx
bne gcs3
ldx #hi(abs1) ;set high byte of indirect poi
stx zpt+1
ldy #lo(abs1) ;data after write & execute te
gcs5 adc (zpt),y
bcc gcs4
inc ram_chksm+1 ;carry to high byte
clc
gcs4 iny
bne gcs5
inx ;advance RAM high address
stx zpt+1
cpx #ram_top
bne gcs5
sta ram_chksm ;checksum complete
endif
next_test
0438 : ad0002 > lda test_case ;previous test
043b : c900 > cmp #test_num
> trap_ne ;test is out of sequence
043d : d0fe > bne * ;failed not equal (non zero)
>
0001 = >test_num = test_num + 1
043f : a901 > lda #test_num ;*** next tests' number
0441 : 8d0002 > sta test_case
> ;check_ram ;uncomment to find altere
if disable_selfmod = 0
;testing relative addressing with BEQ
0444 : a0fe ldy #$fe ;testing maximum range, not -1
0446 : range_loop
0446 : 88 dey ;next relative address
0447 : 98 tya
0448 : aa tax ;precharge count to end of loo
0449 : 1008 bpl range_fw ;calculate relative address
044b : 18 clc ;avoid branch self or to relat
044c : 6902 adc #2
044e : ea nop ;offset landing zone - tolerat
044f : ea nop
0450 : ea nop
0451 : ea nop
0452 : ea nop
0453 : range_fw
0453 : ea nop
0454 : ea nop
0455 : ea nop
0456 : ea nop
0457 : ea nop
0458 : 497f eor #$7f ;complement except sign
045a : 8de604 sta range_adr ;load into test target
045d : a900 lda #0 ;should set zero flag in statu
045f : 4ce504 jmp range_op
0462 : ca dex ; offset landing zone - backwa
0463 : ca dex
0464 : ca dex
0465 : ca dex
0466 : ca dex
;relative address target field with branch und
0467 : ca dex ;-128 - max backward
0468 : ca dex
0469 : ca dex
046a : ca dex
046b : ca dex
046c : ca dex
046d : ca dex
046e : ca dex
046f : ca dex ;-120
0470 : ca dex
0471 : ca dex
0472 : ca dex
0473 : ca dex
0474 : ca dex
0475 : ca dex
0476 : ca dex
0477 : ca dex
0478 : ca dex
0479 : ca dex ;-110
047a : ca dex
047b : ca dex
047c : ca dex
047d : ca dex
047e : ca dex
047f : ca dex
0480 : ca dex
0481 : ca dex
0482 : ca dex
0483 : ca dex ;-100
0484 : ca dex
0485 : ca dex
0486 : ca dex
0487 : ca dex
0488 : ca dex
0489 : ca dex
048a : ca dex
048b : ca dex
048c : ca dex
048d : ca dex ;-90
048e : ca dex
048f : ca dex
0490 : ca dex
0491 : ca dex
0492 : ca dex
0493 : ca dex
0494 : ca dex
0495 : ca dex
0496 : ca dex
0497 : ca dex ;-80
0498 : ca dex
0499 : ca dex
049a : ca dex
049b : ca dex
049c : ca dex
049d : ca dex
049e : ca dex
049f : ca dex
04a0 : ca dex
04a1 : ca dex ;-70
04a2 : ca dex
04a3 : ca dex
04a4 : ca dex
04a5 : ca dex
04a6 : ca dex
04a7 : ca dex
04a8 : ca dex
04a9 : ca dex
04aa : ca dex
04ab : ca dex ;-60
04ac : ca dex
04ad : ca dex
04ae : ca dex
04af : ca dex
04b0 : ca dex
04b1 : ca dex
04b2 : ca dex
04b3 : ca dex
04b4 : ca dex
04b5 : ca dex ;-50
04b6 : ca dex
04b7 : ca dex
04b8 : ca dex
04b9 : ca dex
04ba : ca dex
04bb : ca dex
04bc : ca dex
04bd : ca dex
04be : ca dex
04bf : ca dex ;-40
04c0 : ca dex
04c1 : ca dex
04c2 : ca dex
04c3 : ca dex
04c4 : ca dex
04c5 : ca dex