forked from xen-project/xen
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time.c
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time.c
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/******************************************************************************
* arch/x86/time.c
*
* Per-CPU time calibration and management.
*
* Copyright (c) 2002-2005, K A Fraser
*
* Portions from Linux are:
* Copyright (c) 1991, 1992, 1995 Linus Torvalds
*/
#include <xen/errno.h>
#include <xen/event.h>
#include <xen/sched.h>
#include <xen/lib.h>
#include <xen/init.h>
#include <xen/param.h>
#include <xen/time.h>
#include <xen/timer.h>
#include <xen/smp.h>
#include <xen/irq.h>
#include <xen/pci_ids.h>
#include <xen/softirq.h>
#include <xen/efi.h>
#include <xen/cpuidle.h>
#include <xen/symbols.h>
#include <xen/keyhandler.h>
#include <xen/guest_access.h>
#include <asm/apic.h>
#include <asm/io.h>
#include <asm/iocap.h>
#include <asm/msr.h>
#include <asm/mpspec.h>
#include <asm/processor.h>
#include <asm/fixmap.h>
#include <asm/guest.h>
#include <asm/mc146818rtc.h>
#include <asm/mwait.h>
#include <asm/div64.h>
#include <asm/acpi.h>
#include <asm/hpet.h>
#include <io_ports.h>
#include <asm/setup.h> /* for early_time_init */
#include <public/arch-x86/cpuid.h>
/* opt_clocksource: Force clocksource to one of: pit, hpet, acpi. */
static char __initdata opt_clocksource[10];
string_param("clocksource", opt_clocksource);
unsigned long __read_mostly cpu_khz; /* CPU clock frequency in kHz. */
DEFINE_SPINLOCK(rtc_lock);
unsigned long pit0_ticks;
struct cpu_time_stamp {
u64 local_tsc;
s_time_t local_stime;
/* Next field unconditionally valid only when !CONSTANT_TSC. */
s_time_t master_stime;
};
struct cpu_time {
struct cpu_time_stamp stamp;
struct time_scale tsc_scale;
};
struct platform_timesource {
char *id;
char *name;
u64 frequency;
/* Post-init this hook may only be invoked via the read_counter() wrapper! */
u64 (*read_counter)(void);
s64 (*init)(struct platform_timesource *);
void (*resume)(struct platform_timesource *);
int counter_bits;
};
static DEFINE_PER_CPU(struct cpu_time, cpu_time);
/* Calibrate all CPUs to platform timer every EPOCH. */
#define EPOCH MILLISECS(1000)
static struct timer calibration_timer;
/*
* We simulate a 32-bit platform timer from the 16-bit PIT ch2 counter.
* Otherwise overflow happens too quickly (~50ms) for us to guarantee that
* softirq handling will happen in time.
*
* The pit_lock protects the 16- and 32-bit stamp fields as well as the
*/
static DEFINE_SPINLOCK(pit_lock);
static u16 pit_stamp16;
static u32 pit_stamp32;
static bool __read_mostly using_pit;
/* Boot timestamp, filled in head.S */
u64 __initdata boot_tsc_stamp;
/* Per-socket TSC_ADJUST values, for secondary cores/threads to sync to. */
static uint64_t *__read_mostly tsc_adjust;
/*
* 32-bit division of integer dividend and integer divisor yielding
* 32-bit fractional quotient.
*/
static inline u32 div_frac(u32 dividend, u32 divisor)
{
u32 quotient, remainder;
ASSERT(dividend < divisor);
asm (
"divl %4"
: "=a" (quotient), "=d" (remainder)
: "0" (0), "1" (dividend), "r" (divisor) );
return quotient;
}
/*
* 32-bit multiplication of multiplicand and fractional multiplier
* yielding 32-bit product (radix point at same position as in multiplicand).
*/
static inline u32 mul_frac(u32 multiplicand, u32 multiplier)
{
u32 product_int, product_frac;
asm (
"mul %3"
: "=a" (product_frac), "=d" (product_int)
: "0" (multiplicand), "r" (multiplier) );
return product_int;
}
/*
* Scale a 64-bit delta by scaling and multiplying by a 32-bit fraction,
* yielding a 64-bit result.
*/
u64 scale_delta(u64 delta, const struct time_scale *scale)
{
u64 product;
if ( scale->shift < 0 )
delta >>= -scale->shift;
else
delta <<= scale->shift;
asm (
"mulq %2 ; shrd $32,%1,%0"
: "=a" (product), "=d" (delta)
: "rm" (delta), "0" ((u64)scale->mul_frac) );
return product;
}
#define _TS_MUL_FRAC_IDENTITY 0x80000000UL
/* Compute the reciprocal of the given time_scale. */
static inline struct time_scale scale_reciprocal(struct time_scale scale)
{
struct time_scale reciprocal;
u32 dividend;
ASSERT(scale.mul_frac != 0);
dividend = _TS_MUL_FRAC_IDENTITY;
reciprocal.shift = 1 - scale.shift;
while ( unlikely(dividend >= scale.mul_frac) )
{
dividend >>= 1;
reciprocal.shift++;
}
asm (
"divl %4"
: "=a" (reciprocal.mul_frac), "=d" (dividend)
: "0" (0), "1" (dividend), "r" (scale.mul_frac) );
return reciprocal;
}
/*
* cpu_mask that denotes the CPUs that needs timer interrupt coming in as
* IPIs in place of local APIC timers
*/
static cpumask_t pit_broadcast_mask;
static void smp_send_timer_broadcast_ipi(void)
{
int cpu = smp_processor_id();
cpumask_t mask;
cpumask_and(&mask, &cpu_online_map, &pit_broadcast_mask);
if ( cpumask_test_cpu(cpu, &mask) )
{
__cpumask_clear_cpu(cpu, &mask);
raise_softirq(TIMER_SOFTIRQ);
}
if ( !cpumask_empty(&mask) )
{
cpumask_raise_softirq(&mask, TIMER_SOFTIRQ);
}
}
static void cf_check timer_interrupt(
int irq, void *dev_id, struct cpu_user_regs *regs)
{
ASSERT(local_irq_is_enabled());
if ( hpet_legacy_irq_tick() )
return;
/* Only for start-of-day interruopt tests in io_apic.c. */
pit0_ticks++;
/* Rough hack to allow accurate timers to sort-of-work with no APIC. */
if ( !cpu_has_apic )
raise_softirq(TIMER_SOFTIRQ);
if ( xen_cpuidle )
smp_send_timer_broadcast_ipi();
/* Emulate a 32-bit PIT counter. */
if ( using_pit )
{
u16 count;
spin_lock_irq(&pit_lock);
outb(0x80, PIT_MODE);
count = inb(PIT_CH2);
count |= inb(PIT_CH2) << 8;
pit_stamp32 += (u16)(pit_stamp16 - count);
pit_stamp16 = count;
spin_unlock_irq(&pit_lock);
}
}
static struct irqaction __read_mostly irq0 = {
timer_interrupt, "timer", NULL
};
#define CLOCK_TICK_RATE 1193182 /* system crystal frequency (Hz) */
#define CALIBRATE_FRAC 20 /* calibrate over 50ms */
#define CALIBRATE_VALUE(freq) (((freq) + CALIBRATE_FRAC / 2) / CALIBRATE_FRAC)
static void preinit_pit(void)
{
/* Set PIT channel 0 to HZ Hz. */
#define LATCH (((CLOCK_TICK_RATE)+(HZ/2))/HZ)
outb_p(0x34, PIT_MODE); /* binary, mode 2, LSB/MSB, ch 0 */
outb_p(LATCH & 0xff, PIT_CH0); /* LSB */
outb(LATCH >> 8, PIT_CH0); /* MSB */
#undef LATCH
}
void set_time_scale(struct time_scale *ts, u64 ticks_per_sec)
{
u64 tps64 = ticks_per_sec;
u32 tps32;
int shift = 0;
ASSERT(tps64 != 0);
while ( tps64 > (MILLISECS(1000)*2) )
{
tps64 >>= 1;
shift--;
}
tps32 = (u32)tps64;
while ( tps32 <= (u32)MILLISECS(1000) )
{
tps32 <<= 1;
shift++;
}
ts->mul_frac = div_frac(MILLISECS(1000), tps32);
ts->shift = shift;
printk("SET_TIME_SCALE: ts->mul_frac: %u ; ts->shift: %u ; ticks_per_sec: %lu \n", ts->mul_frac, ts->shift, ticks_per_sec);
}
static char *freq_string(u64 freq)
{
static char s[20];
uint64_t x, y;
if ( do_div(freq, 1000) > 500 )
++freq;
y = (uint64_t)do_div(freq, 1000);
x = (uint64_t)freq;
snprintf(s, sizeof(s), "%lu.%03luMHz", x, y);
return s;
}
static uint32_t __init read_pt_and_tsc(uint64_t *tsc,
const struct platform_timesource *pts)
{
uint64_t tsc_prev = *tsc = rdtsc_ordered(), tsc_min = ~0;
uint32_t best = best;
unsigned int i;
for ( i = 0; ; ++i )
{
uint32_t pt = pts->read_counter();
uint64_t tsc_cur = rdtsc_ordered();
uint64_t tsc_delta = tsc_cur - tsc_prev;
if ( tsc_delta < tsc_min )
{
tsc_min = tsc_delta;
*tsc = tsc_cur;
best = pt;
}
else if ( i > 2 )
break;
tsc_prev = tsc_cur;
}
return best;
}
static uint64_t __init calibrate_tsc(const struct platform_timesource *pts)
{
uint64_t start, end, elapsed;
uint64_t count = read_pt_and_tsc(&start, pts);
uint64_t target = CALIBRATE_VALUE(pts->frequency), actual;
uint64_t mask = (uint64_t)~0 >> (64 - pts->counter_bits);
while ( ((pts->read_counter() - count) & mask) < target )
continue;
actual = (read_pt_and_tsc(&end, pts) - count) & mask;
elapsed = end - start;
if ( likely(actual > target) )
{
/*
* A (perhaps significant) delay before the last timer read (e.g. due
* to a SMI or NMI) can lead to (perhaps severe) inaccuracy if not
* accounting for the time elapsed beyond the originally calculated
* duration of the calibration interval.
*/
elapsed = muldiv64(elapsed, target, actual);
}
return elapsed * CALIBRATE_FRAC;
}
/************************************************************
* PLATFORM TIMER 1: PROGRAMMABLE INTERVAL TIMER (LEGACY PIT)
*/
static u64 cf_check read_pit_count(void)
{
u16 count16;
u32 count32;
unsigned long flags;
spin_lock_irqsave(&pit_lock, flags);
outb(0x80, PIT_MODE);
count16 = inb(PIT_CH2);
count16 |= inb(PIT_CH2) << 8;
count32 = pit_stamp32 + (u16)(pit_stamp16 - count16);
spin_unlock_irqrestore(&pit_lock, flags);
return count32;
}
static s64 __init cf_check init_pit(struct platform_timesource *pts)
{
u8 portb = inb(0x61);
u64 start, end;
unsigned long count;
/* Set the Gate high, disable speaker. */
outb((portb & ~0x02) | 0x01, 0x61);
/*
* Now let's take care of CTC channel 2: mode 0, (interrupt on
* terminal count mode), binary count, load CALIBRATE_LATCH count,
* (LSB and MSB) to begin countdown.
*/
#define CALIBRATE_LATCH CALIBRATE_VALUE(CLOCK_TICK_RATE)
BUILD_BUG_ON(CALIBRATE_LATCH >> 16);
outb(0xb0, PIT_MODE); /* binary, mode 0, LSB/MSB, Ch 2 */
outb(CALIBRATE_LATCH & 0xff, PIT_CH2); /* LSB of count */
outb(CALIBRATE_LATCH >> 8, PIT_CH2); /* MSB of count */
#undef CALIBRATE_LATCH
start = rdtsc_ordered();
for ( count = 0; !(inb(0x61) & 0x20); ++count )
continue;
end = rdtsc_ordered();
/* Set the Gate low, disable speaker. */
outb(portb & ~0x03, 0x61);
/* Error if the CTC doesn't behave itself. */
if ( count == 0 )
return 0;
using_pit = true;
return (end - start) * CALIBRATE_FRAC;
}
static void cf_check resume_pit(struct platform_timesource *pts)
{
/* Set CTC channel 2 to mode 0 again; initial value does not matter. */
outb(0xb0, PIT_MODE); /* binary, mode 0, LSB/MSB, Ch 2 */
outb(0, PIT_CH2); /* LSB of count */
outb(0, PIT_CH2); /* MSB of count */
}
static struct platform_timesource __initdata_cf_clobber plt_pit =
{
.id = "pit",
.name = "PIT",
.frequency = CLOCK_TICK_RATE,
.read_counter = read_pit_count,
.counter_bits = 32,
.init = init_pit,
.resume = resume_pit,
};
/************************************************************
* PLATFORM TIMER 2: HIGH PRECISION EVENT TIMER (HPET)
*/
static u64 cf_check read_hpet_count(void)
{
return hpet_read32(HPET_COUNTER);
}
static int64_t __init cf_check init_hpet(struct platform_timesource *pts)
{
uint64_t hpet_rate;
/*
* Allow HPET to be setup, but report a frequency of 0 so it's not selected
* as a timer source. This is required so it can be used in legacy
* replacement mode in check_timer.
*/
bool disable_hpet = false;
if ( hpet_address && strcmp(opt_clocksource, pts->id) &&
cpuidle_using_deep_cstate() )
{
if ( pci_conf_read16(PCI_SBDF(0, 0, 0x1f, 0),
PCI_VENDOR_ID) == PCI_VENDOR_ID_INTEL )
switch ( pci_conf_read16(PCI_SBDF(0, 0, 0x1f, 0), PCI_DEVICE_ID) )
{
/* HPET on Bay Trail platforms will halt in deep C states. */
case 0x0f1c:
/* HPET on Cherry Trail platforms will halt in deep C states. */
case 0x229c:
disable_hpet = true;
break;
}
/*
* Some Coffee Lake and later platforms have a skewed HPET timer once
* they entered PC10.
*
* Check whether the system supports PC10. If so force disable HPET as
* that stops counting in PC10. This check is overbroad as it does not
* take any of the following into account:
*
* - ACPI tables
* - Enablement of mwait-idle
* - Command line arguments which limit mwait-idle C-state support
*
* That's perfectly fine. HPET is a piece of hardware designed by
* committee and the only reasons why it is still in use on modern
* systems is the fact that it is impossible to reliably query TSC and
* CPU frequency via CPUID or firmware.
*
* If HPET is functional it is useful for calibrating TSC, but this can
* be done via PMTIMER as well which seems to be the last remaining
* timer on X86/INTEL platforms that has not been completely wreckaged
* by feature creep.
*
* In theory HPET support should be removed altogether, but there are
* older systems out there which depend on it because TSC and APIC timer
* are dysfunctional in deeper C-states.
*/
if ( mwait_pc10_supported() )
{
uint64_t pcfg;
rdmsrl(MSR_PKG_CST_CONFIG_CONTROL, pcfg);
if ( (pcfg & 0xf) < 8 )
/* nothing */;
else if ( !strcmp(opt_clocksource, pts->id) )
printk("HPET use requested via command line, but dysfunctional in PC10\n");
else
disable_hpet = true;
}
if ( disable_hpet )
printk("Disabling HPET for being unreliable\n");
}
if ( (hpet_rate = hpet_setup()) == 0 || disable_hpet )
return 0;
pts->frequency = hpet_rate;
return calibrate_tsc(pts);
}
static void cf_check resume_hpet(struct platform_timesource *pts)
{
hpet_resume(NULL);
}
static struct platform_timesource __initdata_cf_clobber plt_hpet =
{
.id = "hpet",
.name = "HPET",
.read_counter = read_hpet_count,
.counter_bits = 32,
.init = init_hpet,
.resume = resume_hpet
};
/************************************************************
* PLATFORM TIMER 3: ACPI PM TIMER
*/
u32 __read_mostly pmtmr_ioport;
unsigned int __initdata pmtmr_width;
/* ACPI PM timer ticks at 3.579545 MHz. */
#define ACPI_PM_FREQUENCY 3579545
static u64 cf_check read_pmtimer_count(void)
{
return inl(pmtmr_ioport);
}
static s64 __init cf_check init_pmtimer(struct platform_timesource *pts)
{
if ( !pmtmr_ioport || (pmtmr_width != 24 && pmtmr_width != 32) )
return 0;
pts->counter_bits = pmtmr_width;
return calibrate_tsc(pts);
}
static struct platform_timesource __initdata_cf_clobber plt_pmtimer =
{
.id = "acpi",
.name = "ACPI PM Timer",
.frequency = ACPI_PM_FREQUENCY,
.read_counter = read_pmtimer_count,
.init = init_pmtimer
};
static struct time_scale __read_mostly pmt_scale;
static __init int cf_check init_pmtmr_scale(void)
{
set_time_scale(&pmt_scale, ACPI_PM_FREQUENCY);
return 0;
}
__initcall(init_pmtmr_scale);
uint64_t cf_check acpi_pm_tick_to_ns(uint64_t ticks)
{
return scale_delta(ticks, &pmt_scale);
}
/************************************************************
* PLATFORM TIMER 4: TSC
*/
static unsigned int __initdata tsc_flags;
/* TSC is reliable across sockets */
#define TSC_RELIABLE_SOCKET (1 << 0)
/*
* Called in verify_tsc_reliability() under reliable TSC conditions
* thus reusing all the checks already performed there.
*/
static s64 __init cf_check init_tsc(struct platform_timesource *pts)
{
u64 ret = pts->frequency;
if ( nr_cpu_ids != num_present_cpus() )
{
printk(XENLOG_WARNING "TSC: CPU Hotplug intended\n");
ret = 0;
}
if ( nr_sockets > 1 && !(tsc_flags & TSC_RELIABLE_SOCKET) )
{
printk(XENLOG_WARNING "TSC: Not invariant across sockets\n");
ret = 0;
}
if ( !ret )
printk(XENLOG_DEBUG "TSC: Not setting it as clocksource\n");
return ret;
}
/*
* plt_tsc's read_counter hook is not (and should not be) invoked via the
* struct field. To avoid carrying an unused, indirectly reachable function,
* poison the field with an easily identifiable non-canonical pointer.
*/
#define READ_TSC_POISON ((uint64_t(*)(void))0x75C75C75C75C75C0ul)
static struct platform_timesource __initdata_cf_clobber plt_tsc =
{
.id = "tsc",
.name = "TSC",
.read_counter = READ_TSC_POISON,
/*
* Calculations for platform timer overflow assume u64 boundary.
* Hence we set to less than 64, such that the TSC wraparound is
* correctly checked and handled.
*/
.counter_bits = 63,
.init = init_tsc,
};
#ifdef CONFIG_XEN_GUEST
/************************************************************
* PLATFORM TIMER 5: XEN PV CLOCK SOURCE
*
* Xen clock source is a variant of TSC source.
*/
static uint64_t xen_timer_last;
static uint64_t xen_timer_cpu_frequency(void)
{
struct vcpu_time_info *info = &this_cpu(vcpu_info)->time;
uint64_t freq;
freq = (1000000000ULL << 32) / info->tsc_to_system_mul;
if ( info->tsc_shift < 0 )
freq <<= -info->tsc_shift;
else
freq >>= info->tsc_shift;
return freq;
}
static int64_t __init cf_check init_xen_timer(struct platform_timesource *pts)
{
if ( !xen_guest )
return 0;
return xen_timer_cpu_frequency();
}
static always_inline uint64_t read_cycle(const struct vcpu_time_info *info,
uint64_t tsc)
{
uint64_t delta = tsc - info->tsc_timestamp;
struct time_scale ts = {
.shift = info->tsc_shift,
.mul_frac = info->tsc_to_system_mul,
};
uint64_t offset = scale_delta(delta, &ts);
return info->system_time + offset;
}
static uint64_t cf_check read_xen_timer(void)
{
struct vcpu_time_info *info = &this_cpu(vcpu_info)->time;
uint32_t version;
uint64_t ret;
uint64_t last;
do {
version = info->version & ~1;
/* Make sure version is read before the data */
smp_rmb();
ret = read_cycle(info, rdtsc_ordered());
/* Ignore fancy flags for now */
/* Make sure version is reread after the data */
smp_rmb();
} while ( unlikely(version != info->version) );
/* Maintain a monotonic global value */
do {
last = read_atomic(&xen_timer_last);
if ( ret < last )
return last;
} while ( unlikely(cmpxchg(&xen_timer_last, last, ret) != last) );
return ret;
}
static void cf_check resume_xen_timer(struct platform_timesource *pts)
{
write_atomic(&xen_timer_last, 0);
}
static struct platform_timesource __initdata_cf_clobber plt_xen_timer =
{
.id = "xen",
.name = "XEN PV CLOCK",
.frequency = 1000000000ULL,
.read_counter = read_xen_timer,
.init = init_xen_timer,
.resume = resume_xen_timer,
.counter_bits = 63,
};
#endif
#ifdef CONFIG_HYPERV_GUEST
/************************************************************
* HYPER-V REFERENCE TSC
*/
#include <asm/guest/hyperv-tlfs.h>
static struct ms_hyperv_tsc_page *hyperv_tsc;
static struct page_info *hyperv_tsc_page;
static int64_t __init cf_check init_hyperv_timer(
struct platform_timesource *pts)
{
paddr_t maddr;
uint64_t tsc_msr, freq;
if ( !(ms_hyperv.features & HV_MSR_REFERENCE_TSC_AVAILABLE) ||
!(ms_hyperv.features & HV_X64_ACCESS_FREQUENCY_MSRS) )
return 0;
hyperv_tsc_page = alloc_domheap_page(NULL, 0);
if ( !hyperv_tsc_page )
return 0;
hyperv_tsc = __map_domain_page_global(hyperv_tsc_page);
if ( !hyperv_tsc )
{
free_domheap_page(hyperv_tsc_page);
hyperv_tsc_page = NULL;
return 0;
}
maddr = page_to_maddr(hyperv_tsc_page);
/*
* Per Hyper-V TLFS:
* 1. Read existing MSR value
* 2. Preserve bits [11:1]
* 3. Set bits [63:12] to be guest physical address of tsc page
* 4. Set enabled bit (0)
* 5. Write back new MSR value
*/
rdmsrl(HV_X64_MSR_REFERENCE_TSC, tsc_msr);
tsc_msr &= 0xffe;
tsc_msr |= maddr | 1 /* enabled */;
wrmsrl(HV_X64_MSR_REFERENCE_TSC, tsc_msr);
/* Get TSC frequency from Hyper-V */
rdmsrl(HV_X64_MSR_TSC_FREQUENCY, freq);
pts->frequency = freq;
return freq;
}
static uint64_t cf_check read_hyperv_timer(void)
{
uint64_t scale, ret, tsc;
int64_t offset;
uint32_t seq;
const struct ms_hyperv_tsc_page *tsc_page = hyperv_tsc;
do {
seq = tsc_page->tsc_sequence;
/* Seq 0 is special. It means the TSC enlightenment is not
* available at the moment. The reference time can only be
* obtained from the Reference Counter MSR.
*/
if ( seq == 0 )
{
rdmsrl(HV_X64_MSR_TIME_REF_COUNT, ret);
return ret;
}
/* rdtsc_ordered already contains a load fence */
tsc = rdtsc_ordered();
scale = tsc_page->tsc_scale;
offset = tsc_page->tsc_offset;
smp_rmb();
} while ( tsc_page->tsc_sequence != seq );
return hv_scale_tsc(tsc, scale, offset);
}
static struct platform_timesource __initdata_cf_clobber plt_hyperv_timer =
{
.id = "hyperv",
.name = "HYPER-V REFERENCE TSC",
.read_counter = read_hyperv_timer,
.init = init_hyperv_timer,
/* See TSC time source for why counter_bits is set to 63 */
.counter_bits = 63,
};
#endif
/************************************************************
* GENERIC PLATFORM TIMER INFRASTRUCTURE
*/
/* details of chosen timesource */
static struct platform_timesource __read_mostly plt_src;
/* hardware-width mask */
static u64 __read_mostly plt_mask;
/* ns between calls to plt_overflow() */
static u64 __read_mostly plt_overflow_period;
/* scale: platform counter -> nanosecs */
static struct time_scale __read_mostly plt_scale;
/* Protected by platform_timer_lock. */
static DEFINE_SPINLOCK(platform_timer_lock);
static s_time_t stime_platform_stamp; /* System time at below platform time */
static u64 platform_timer_stamp; /* Platform time at above system time */
static u64 plt_stamp64; /* 64-bit platform counter stamp */
static u64 plt_stamp; /* hardware-width platform counter stamp */
static struct timer plt_overflow_timer;
static s_time_t __read_platform_stime(u64 platform_time)
{
u64 diff = platform_time - platform_timer_stamp;
ASSERT(spin_is_locked(&platform_timer_lock));
return (stime_platform_stamp + scale_delta(diff, &plt_scale));
}
static uint64_t read_counter(void)
{
/*
* plt_tsc is put in use only after alternatives patching has occurred,
* hence we can't invoke read_tsc() that way. Special case it here, open-
* coding the function call at the same time.
*/
return plt_src.read_counter != READ_TSC_POISON
? alternative_call(plt_src.read_counter)
: rdtsc_ordered();
}
static void cf_check plt_overflow(void *unused)
{
int i;
u64 count;
s_time_t now, plt_now, plt_wrap;
spin_lock_irq(&platform_timer_lock);
count = read_counter();
plt_stamp64 += (count - plt_stamp) & plt_mask;
plt_stamp = count;
now = NOW();
plt_wrap = __read_platform_stime(plt_stamp64);
for ( i = 0; i < 10; i++ )
{
plt_now = plt_wrap;
plt_wrap = __read_platform_stime(plt_stamp64 + plt_mask + 1);
if ( ABS(plt_wrap - now) > ABS(plt_now - now) )
break;
plt_stamp64 += plt_mask + 1;
}
if ( i != 0 )
{
static bool warned_once;
if ( !test_and_set_bool(warned_once) )
printk("Platform timer appears to have unexpectedly wrapped "
"%u%s times.\n", i, (i == 10) ? " or more" : "");
}
spin_unlock_irq(&platform_timer_lock);
set_timer(&plt_overflow_timer, NOW() + plt_overflow_period);
}
static s_time_t read_platform_stime(u64 *stamp)
{
u64 plt_counter, count;
s_time_t stime;
ASSERT(!local_irq_is_enabled());
spin_lock(&platform_timer_lock);
plt_counter = read_counter();
count = plt_stamp64 + ((plt_counter - plt_stamp) & plt_mask);
stime = __read_platform_stime(count);
spin_unlock(&platform_timer_lock);
if ( unlikely(stamp) )
*stamp = plt_counter;
return stime;
}
static void platform_time_calibration(void)
{
u64 count;
s_time_t stamp;
unsigned long flags;
spin_lock_irqsave(&platform_timer_lock, flags);
count = plt_stamp64 + ((read_counter() - plt_stamp) & plt_mask);
stamp = __read_platform_stime(count);
stime_platform_stamp = stamp;
platform_timer_stamp = count;
spin_unlock_irqrestore(&platform_timer_lock, flags);
}
static void resume_platform_timer(void)
{
/* Timer source can be reset when backing from S3 to S0 */
if ( plt_src.resume )
alternative_vcall(plt_src.resume, &plt_src);
plt_stamp64 = platform_timer_stamp;
plt_stamp = read_counter();
}
static void __init reset_platform_timer(void)
{
kill_timer(&plt_overflow_timer);
/* Reset counters and stamps */
spin_lock_irq(&platform_timer_lock);
plt_stamp = 0;
plt_stamp64 = 0;
platform_timer_stamp = 0;
stime_platform_stamp = 0;
spin_unlock_irq(&platform_timer_lock);
}
static s64 __init try_platform_timer(struct platform_timesource *pts)
{
s64 rc = pts->init(pts);
if ( rc <= 0 )
return rc;
/* We have a platform timesource already so reset it */
if ( plt_src.counter_bits != 0 )
reset_platform_timer();
plt_mask = (u64)~0ull >> (64 - pts->counter_bits);
set_time_scale(&plt_scale, pts->frequency);
plt_overflow_period = scale_delta(
1ull << (pts->counter_bits - 1), &plt_scale);
plt_src = *pts;
return rc;
}
static u64 __init init_platform_timer(void)
{
static struct platform_timesource * __initdata plt_timers[] = {
#ifdef CONFIG_XEN_GUEST
&plt_xen_timer,
#endif
#ifdef CONFIG_HYPERV_GUEST
&plt_hyperv_timer,
#endif
&plt_hpet, &plt_pmtimer, &plt_pit
};
struct platform_timesource *pts = NULL;
unsigned int i;
s64 rc = -1;
/* clocksource=tsc is initialized via __initcalls (when CPUs are up). */
if ( (opt_clocksource[0] != '\0') && strcmp(opt_clocksource, "tsc") )
{
for ( i = 0; i < ARRAY_SIZE(plt_timers); i++ )
{
pts = plt_timers[i];
if ( !strcmp(opt_clocksource, pts->id) )
{
rc = try_platform_timer(pts);
break;
}
}
if ( rc <= 0 )