/
fpu.c
1881 lines (1753 loc) · 61.5 KB
/
fpu.c
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
// x87 FPU operations built on top of the Bochs/SoftFloat floating point emulator.
// Quick note:
// | ST0 | ST1 | | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 |
// fld A | A | - | | | | | | | | | A | ftop: 7
// fld B | B | A | | | | | | | | B | A | ftop: 6
// fadd C | B+A | A | | | | | | | |B+A| A | ftop: 6
// List of instructions that do NOT check for exceptions:
// - FNSTENV, FNINIT, FNCLEX, FNSAVE, FNSTSW, FNSTSW, FNSTCW
// List of instructions that do not update FPU eip and friends:
// - FNCLEX, FLDCW, FNSTCW, FNSTSW, FNSTENV, FLDENV, and FWAIT
// FLD mem order of operations:
// 1. Read source memory, but don't do anything with it yet
// 2. Save FPU CS:IP and data pointers
// 3. Convert source memory to 80-bit FP register
// 4. Check destination
// For basic arithmetic instructions, these are the possible operands:
/*
FADD:
ST(0) = ST(0) + float32 <D8>
ST(0) = ST(0) + int32 <DA>
ST(0) = ST(0) + float64 <DC>
ST(0) = ST(0) + int16 <DE>
ST(0) = ST(0) + ST(i) <D8 mod=3>
ST(i) = ST(i) + ST(0) <DC mod=3>
ST(i) = ST(i) + ST(0) & pop <DE mod=3>
*/
// There are no read-modify-write operations, thank god.
#define FPU_DEBUG
#ifdef FPU_DEBUG
#include <math.h>
#endif
#include "cpu/cpu.h"
#include "cpu/instrument.h"
#include "devices.h"
#define EXCEPTION_HANDLER return 1
#define FLOATX80
#include "softfloat/softfloat.h"
#include "softfloat/softfloatx80.h"
#define NEED_STRUCT
#include "cpu/fpu.h"
#undef NEED_STRUCT
#if 0
// For savestate generator
// <<< BEGIN STRUCT "struct" >>>
int ftop;
uint16_t control_word, status_word, tag_word;
uint32_t fpu_eip, fpu_data_ptr;
uint16_t fpu_cs, fpu_opcode, fpu_data_seg;
// <<< END STRUCT "struct" >>>
#endif
enum {
FPU_TAG_VALID = 0,
FPU_TAG_ZERO = 1,
FPU_TAG_SPECIAL = 2,
FPU_TAG_EMPTY = 3
};
#define FPU_ROUND_SHIFT 10
#define FPU_PRECISION_SHIFT 8
enum {
FPU_ROUND_NEAREST = 0,
FPU_ROUND_DOWN = 1,
FPU_ROUND_UP = 2,
FPU_ROUND_TRUNCATE = 3
};
enum {
FPU_PRECISION_24 = 0, // 32-bit float
FPU_PRECISION_53 = 2, // 64-bit double
FPU_PRECISION_64 = 3 // 80-bit st80
};
#define FPU_EXCEPTION_STACK_FAULT (1 << 6)
#define FPU_EXCEPTION_PRECISION (1 << 5)
#define FPU_EXCEPTION_UNDERFLOW (1 << 4)
#define FPU_EXCEPTION_OVERFLOW (1 << 3)
#define FPU_EXCEPTION_ZERO_DIVIDE (1 << 2)
#define FPU_EXCEPTION_DENORMALIZED (1 << 1)
#define FPU_EXCEPTION_INVALID_OPERATION (1 << 0)
// Status word
#define GET_C0 (fpu.status_word & (1 << 8)) != 0
#define GET_C1 (fpu.status_word & (1 << 9)) != 0
#define GET_C2 (fpu.status_word & (1 << 10)) != 0
#define GET_C3 (fpu.status_word & (1 << 14)) != 0
#define FPU_FTOP_SHIFT 11
#define SET_C0(n) fpu.status_word = (fpu.status_word & ~(1 << 8)) | (n) << 8
#define SET_C1(n) fpu.status_word = (fpu.status_word & ~(1 << 9)) | (n) << 9
#define SET_C2(n) fpu.status_word = (fpu.status_word & ~(1 << 10)) | (n) << 10
#define SET_C3(n) fpu.status_word = (fpu.status_word & ~(1 << 14)) | (n) << 14
#define MASKED(a) (fpu.control_word & a)
static const floatx80 Zero = BUILD_FLOAT(0, 0);
static const floatx80 IndefiniteNaN = BUILD_FLOAT(0xFFFF, 0xC000000000000000);
//static const floatx80 PositiveInfinity = BUILD_FLOAT(0x7FFF, 0x8000000000000000);
//static const extFloat80_t NegativeInfinity = BUILD_FLOAT(0xFFFF, 0x8000000000000000);
static const floatx80 Constant_1 = BUILD_FLOAT(0x3fff, 0x8000000000000000);
static const floatx80 Constant_L2T = BUILD_FLOAT(0x4000, 0xd49a784bcd1b8afe);
static const floatx80 Constant_L2E = BUILD_FLOAT(0x3fff, 0xb8aa3b295c17f0bc);
static const floatx80 Constant_PI = BUILD_FLOAT(0x4000, 0xc90fdaa22168c235);
static const floatx80 Constant_LG2 = BUILD_FLOAT(0x3ffd, 0x9a209a84fbcff799);
static const floatx80 Constant_LN2 = BUILD_FLOAT(0x3ffe, 0xb17217f7d1cf79ac);
static const floatx80* Constants[8] = {
// Technically, there are only 7 constants according to the x87 spec, but to make this array nice and round, I'm going to assume that were there to be an eighth value, it would be an indefinite NaN.
&Constant_1, &Constant_L2T, &Constant_L2E, &Constant_PI, &Constant_LG2, &Constant_LN2, &Zero, &IndefiniteNaN
};
struct fpu fpu;
// FLDCW
static void fpu_set_control_word(uint16_t control_word)
{
control_word |= 0x40; // Experiments with real hardware indicate that bit 6 is always set.
fpu.control_word = control_word;
int rounding = fpu.control_word >> FPU_ROUND_SHIFT & 3;
switch (rounding) {
case FPU_ROUND_NEAREST: // aka round to even
fpu.status.float_rounding_mode = float_round_nearest_even;
break;
case FPU_ROUND_DOWN:
fpu.status.float_rounding_mode = float_round_down;
break;
case FPU_ROUND_UP:
fpu.status.float_rounding_mode = float_round_up;
break;
case FPU_ROUND_TRUNCATE: // aka towards zero
fpu.status.float_rounding_mode = float_round_to_zero;
break;
}
int precision = fpu.control_word >> FPU_PRECISION_SHIFT & 3;
switch (precision) {
case FPU_PRECISION_24: // aka float
fpu.status.float_rounding_precision = 32;
break;
case FPU_PRECISION_53: // aka double
fpu.status.float_rounding_precision = 64;
break;
case FPU_PRECISION_64: // This is the default
fpu.status.float_rounding_precision = 80;
break;
}
// Are these right?
fpu.status.float_exception_flags = 0; // clear exceptions before execution
fpu.status.float_nan_handling_mode = float_first_operand_nan;
fpu.status.flush_underflow_to_zero = 0;
fpu.status.float_suppress_exception = 0;
fpu.status.float_exception_masks = control_word & 0x3F;
fpu.status.denormals_are_zeros = 0;
}
static void fpu_state(void)
{
#ifndef LIBCPU
// <<< BEGIN AUTOGENERATE "state" >>>
struct bjson_object* obj = state_obj("fpu", 9 + 16);
state_field(obj, 4, "fpu.ftop", &fpu.ftop);
state_field(obj, 2, "fpu.control_word", &fpu.control_word);
state_field(obj, 2, "fpu.status_word", &fpu.status_word);
state_field(obj, 2, "fpu.tag_word", &fpu.tag_word);
state_field(obj, 4, "fpu.fpu_eip", &fpu.fpu_eip);
state_field(obj, 4, "fpu.fpu_data_ptr", &fpu.fpu_data_ptr);
state_field(obj, 2, "fpu.fpu_cs", &fpu.fpu_cs);
state_field(obj, 2, "fpu.fpu_opcode", &fpu.fpu_opcode);
state_field(obj, 2, "fpu.fpu_data_seg", &fpu.fpu_data_seg);
// <<< END AUTOGENERATE "state" >>>
char name[32];
for (int i = 0; i < 8; i++) {
sprintf(name, "fpu.st[%d].mantissa", i);
state_field(obj, 8, name, &fpu.st[i].fraction);
sprintf(name, "fpu.st[%d].exponent", i);
state_field(obj, 2, name, &fpu.st[i].exp);
}
if (state_is_reading())
fpu_set_control_word(fpu.control_word);
#endif
}
static uint16_t fpu_get_status_word(void)
{
return fpu.status_word | (fpu.ftop << 11);
}
// Helper functions to determine type of floating point number.
static int is_denormal(uint16_t exponent, uint64_t mantissa)
{
return !(exponent & 0x7FFF) && mantissa;
}
static int is_pseudo_denormal(uint16_t exponent, uint64_t mantissa)
{
return is_denormal(exponent, mantissa) && !(mantissa & 0x8000000000000000ULL);
}
static int is_zero(uint16_t exponent, uint64_t mantissa)
{
return ((exponent & 0x7FFF) | mantissa) == 0;
}
// Check if a floating point number is a zero of any sign.
// Returns 1 if it's a positive zero
// Returns -1 if it's a negative zero
// Returns 0 if it's neither.
static int is_zero_any_sign(uint16_t exponent, uint64_t mantissa)
{
if (is_zero(exponent, mantissa)) {
if (exponent & 0x8000)
return -1;
else
return 1;
} else
return 0;
}
int is_negative(uint16_t exponent, uint64_t mantissa)
{
return !is_zero_any_sign(exponent, mantissa) && (exponent & 0x8000) != 0;
}
static int is_invalid(uint16_t exponent, uint64_t mantissa)
{
// Check for pseudo NaN, pseudo Infinity, or Unnormal
uint16_t exponent_without_sign = exponent & 0x7FFF;
if (exponent_without_sign != 0)
return (mantissa & 0x8000000000000000ULL) == 0; // Pseudo-NaN, Pseudo-Infinity, or Unnormal
return 0;
}
// Returns:
// -1 for -Infinity
// 1 for Infinity
// 0 for non-infinity
static int is_infinity(uint16_t exponent, uint64_t mantissa)
{
if (((exponent & 0x7FFF) == 0x7FFF) && (mantissa == 0x8000000000000000ULL))
return mantissa >> 15 ? -1 : 1;
return 0;
}
// Returns 1 if quiet, 2 if signalling, 0 if neither
static int is_nan(uint16_t exponent, uint64_t mantissa)
{
if (((exponent & 0x7FFF) == 0x7FFF) && (mantissa != 0x8000000000000000ULL))
return 1 + ((mantissa & 0x4000000000000000ULL) != 0);
return 0;
}
static int fpu_get_tag_from_value(floatx80* f)
{
uint16_t exponent;
uint64_t mantissa;
floatx80_unpack(f, exponent, mantissa);
if ((exponent | mantissa) == 0) // Both exponent and mantissa are zero
return FPU_TAG_ZERO;
int x = 0;
x |= is_infinity(exponent, mantissa);
x |= is_denormal(exponent, mantissa);
x |= is_pseudo_denormal(exponent, mantissa);
x |= is_invalid(exponent, mantissa);
x |= is_nan(exponent, mantissa);
if (x)
return FPU_TAG_SPECIAL;
return FPU_TAG_VALID;
}
static int fpu_get_tag(int st)
{
return fpu.tag_word >> (((st + fpu.ftop) & 7) << 1) & 3;
}
static void fpu_set_tag(int st, int v)
{
int shift = ((st + fpu.ftop) & 7) << 1;
fpu.tag_word &= ~(3 << shift);
fpu.tag_word |= v << shift;
}
static int fpu_exception_raised(int flags)
{
return (fpu.status.float_exception_flags & ~fpu.status.float_exception_masks) & flags;
}
// Note that stack faults must be handled before any arith, softfloat.c may clear them.
static void fpu_stack_fault(void)
{
//__asm__("int3");
fpu.status.float_exception_flags = FPU_EXCEPTION_INVALID_OPERATION | FPU_EXCEPTION_STACK_FAULT;
//if(fpu.status.float_exception_masks & FPU_EXCEPTION_INVALID_OPERATION) return 1;
//return 0;
}
static uint32_t partial_sw, bits_to_clear;
static void fpu_commit_sw(void)
{
// XXX this is a really, really bad kludge
fpu.status_word |= partial_sw;
fpu.status_word &= ~bits_to_clear | partial_sw;
bits_to_clear = 0;
partial_sw = 0;
}
static int fpu_check_exceptions2(int commit_sw)
{
int flags = fpu.status.float_exception_flags;
int unmasked_exceptions = (flags & ~fpu.status.float_exception_masks) & 0x3F;
// Note: #P is ignored if #U or #O is set.
if (flags & FPU_EXCEPTION_PRECISION && (flags & (FPU_EXCEPTION_UNDERFLOW | FPU_EXCEPTION_OVERFLOW))) {
flags &= ~FPU_EXCEPTION_PRECISION;
unmasked_exceptions &= ~FPU_EXCEPTION_PRECISION;
}
// Note: C1 is set if the result was rounded up, but cleared if a stack underflow occurred
if (flags & 0x10000) {
// Stack underflow occurred
flags &= ~(1 << 9);
}
// If #I, #D, or #Z, then ignore others.
if (flags & (FPU_EXCEPTION_INVALID_OPERATION | FPU_EXCEPTION_ZERO_DIVIDE | FPU_EXCEPTION_DENORMALIZED)) {
unmasked_exceptions &= FPU_EXCEPTION_INVALID_OPERATION | FPU_EXCEPTION_ZERO_DIVIDE | FPU_EXCEPTION_DENORMALIZED;
flags &= FPU_EXCEPTION_INVALID_OPERATION | FPU_EXCEPTION_ZERO_DIVIDE | FPU_EXCEPTION_DENORMALIZED | FPU_EXCEPTION_STACK_FAULT;
}
if (commit_sw)
fpu.status_word |= flags;
else
partial_sw |= flags;
if (unmasked_exceptions) {
fpu.status_word |= 0x8080;
if (unmasked_exceptions & ~FPU_EXCEPTION_PRECISION)
return 1;
return 0; // Only #P is raised but we can ignore that
}
return 0;
}
static int fpu_check_exceptions(void)
{
return fpu_check_exceptions2(1);
}
static void fninit(void)
{
// https://www.felixcloutier.com/x86/finit:fninit
fpu_set_control_word(0x37F);
fpu.status_word = 0;
fpu.tag_word = 0xFFFF;
fpu.ftop = 0;
fpu.fpu_data_ptr = 0;
fpu.fpu_data_seg = 0;
fpu.fpu_eip = 0;
fpu.fpu_cs = 0; // Not in the docs, but assuming that it's the case
fpu.fpu_opcode = 0;
}
static inline int fpu_nm_check(void)
{
if (cpu.cr[0] & (CR0_EM | CR0_TS))
EXCEPTION_NM();
return 0;
}
static inline floatx80* fpu_get_st_ptr(int st)
{
return &fpu.st[(fpu.ftop + st) & 7];
}
static inline floatx80 fpu_get_st(int st)
{
return fpu.st[(fpu.ftop + st) & 7];
}
static inline void fpu_set_st(int st, floatx80 data)
{
fpu_set_tag(st, fpu_get_tag_from_value(&data));
fpu.st[(fpu.ftop + st) & 7] = data;
}
// Fault if ST register is not empty.
static int fpu_check_stack_overflow(int st)
{
int tag = fpu_get_tag(st);
if (tag != FPU_TAG_EMPTY) {
SET_C1(1);
fpu_stack_fault();
return 1;
}
SET_C1(0);
return 0;
}
// Fault if ST register is empty.
static int fpu_check_stack_underflow(int st, int commit_sw)
{
int tag = fpu_get_tag(st);
if (tag == FPU_TAG_EMPTY) {
fpu_stack_fault();
if (commit_sw)
SET_C1(1);
else
partial_sw = 1 << 9;
return 1;
}
if (commit_sw)
SET_C1(0);
else
bits_to_clear = 1 << 9;
return 0;
}
static int fpu_exception_masked(int excep)
{
if (excep == FPU_EXCEPTION_STACK_FAULT)
excep = FPU_EXCEPTION_INVALID_OPERATION;
return (fpu.control_word & excep);
}
static int fpu_push(floatx80 data)
{
fpu.ftop = (fpu.ftop - 1) & 7;
fpu_set_st(0, data);
return 0;
}
static void fpu_pop()
{
fpu_set_tag(0, FPU_TAG_EMPTY);
fpu.ftop = (fpu.ftop + 1) & 7;
}
static void fpu_update_pointers(uint32_t opcode)
{
//if (VIRT_EIP() == 0x759783bb)
// __asm__("int3");
fpu.fpu_cs = cpu.seg[CS];
fpu.fpu_eip = VIRT_EIP();
fpu.fpu_opcode = opcode;
}
static void fpu_update_pointers2(uint32_t opcode, uint32_t virtaddr, uint32_t seg)
{
//if (VIRT_EIP() == 0x759783bb)
// __asm__("int3");
fpu.fpu_cs = cpu.seg[CS];
fpu.fpu_eip = VIRT_EIP();
fpu.fpu_opcode = opcode;
fpu.fpu_data_ptr = virtaddr;
fpu.fpu_data_seg = cpu.seg[seg];
}
#if 0
static int read_float32(uint32_t linaddr, float32* dest)
{
uint32_t low;
cpu_read32(linaddr, low, cpu.tlb_shift_read);
*dest = low;
return 0;
}
#endif
static int write_float32(uint32_t linaddr, float32 src)
{
cpu_write32(linaddr, src, cpu.tlb_shift_write);
return 0;
}
#if 0
static int read_float64(uint32_t linaddr, float64* dest)
{
uint32_t low, hi;
cpu_read32(linaddr, low, cpu.tlb_shift_read);
cpu_read32(linaddr + 4, hi, cpu.tlb_shift_read);
*dest = (uint64_t)low | (uint64_t)hi << 32;
return 0;
}
#endif
static int write_float64(uint32_t linaddr, float64 dest)
{
uint64_t x = dest;
cpu_write32(linaddr, (uint32_t)x, cpu.tlb_shift_write);
cpu_write32(linaddr + 4, (uint32_t)(x >> 32), cpu.tlb_shift_write);
return 0;
}
static int fpu_check_push(void)
{
if (fpu_check_stack_overflow(-1)) {
fpu_check_exceptions();
if (fpu.control_word & FPU_EXCEPTION_INVALID_OPERATION) {
// masked response
fpu_push(IndefiniteNaN);
} else
fpu.status_word |= 0x80; // ?
return 1;
}
return 0;
}
static int fpu_store_f80(uint32_t linaddr, floatx80* data)
{
uint16_t exponent;
uint64_t mantissa;
floatx80_unpack(data, exponent, mantissa);
int shift = cpu.tlb_shift_write;
cpu_write32(linaddr, (uint32_t)mantissa, shift);
cpu_write32(linaddr + 4, (uint32_t)(mantissa >> 32), shift);
cpu_write16(linaddr + 8, exponent, shift);
return 0;
}
static int fpu_read_f80(uint32_t linaddr, floatx80* data)
{
uint16_t exponent;
uint32_t low, hi;
int shift = cpu.tlb_shift_read;
cpu_read32(linaddr, low, shift);
cpu_read32(linaddr + 4, hi, shift);
cpu_read16(linaddr + 8, exponent, shift);
floatx80_repack(data, exponent, (uint64_t)low | (uint64_t)hi << 32);
return 0;
}
// Actual FPU operations
static int fpu_fcom(floatx80 op1, floatx80 op2, int unordered)
{
int relation = floatx80_compare_internal(op1, op2, unordered, &fpu.status);
if (fpu_check_exceptions())
return 1;
int bad = relation == float_relation_unordered;
SET_C0(bad | (relation == float_relation_less));
SET_C2(bad);
SET_C3(bad | (relation == float_relation_equal));
return 0;
}
static int fpu_fcomi(floatx80 op1, floatx80 op2, int unordered)
{
int relation = floatx80_compare_internal(op1, op2, unordered, &fpu.status);
if (fpu_check_exceptions())
return 1;
int bad = relation == float_relation_unordered;
int cf = bad | (relation == float_relation_less);
int pf = bad;
int zf = bad | (relation == float_relation_equal);
cpu_set_cf(cf);
cpu_set_pf(pf);
cpu_set_zf(zf);
return 0;
}
//void fpu_debug(void);
static int fstenv(uint32_t linaddr, int code16)
{
//fpu_debug();
for (int i = 0; i < 8; i++) {
if (fpu_get_tag(i) != FPU_TAG_EMPTY)
fpu_set_tag(i, fpu_get_tag_from_value(&fpu.st[(fpu.ftop + i) & 7]));
}
// https://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-vol-1-manual.pdf
// page 203
int x = cpu.tlb_shift_write;
//fpu_debug();
//__asm__("int3");
if (!code16) {
cpu_write32(linaddr, 0xFFFF0000 | fpu.control_word, x);
cpu_write32(linaddr + 4, 0xFFFF0000 | fpu_get_status_word(), x);
cpu_write32(linaddr + 8, 0xFFFF0000 | fpu.tag_word, x);
if (cpu.cr[0] & CR0_PE) {
cpu_write32(linaddr + 12, fpu.fpu_eip, x);
cpu_write32(linaddr + 16, fpu.fpu_cs | (fpu.fpu_opcode << 16), x);
cpu_write32(linaddr + 20, fpu.fpu_data_ptr, x);
cpu_write32(linaddr + 24, 0xFFFF0000 | fpu.fpu_data_seg, x);
} else {
uint32_t linear_fpu_eip = fpu.fpu_eip + (fpu.fpu_cs << 4);
uint32_t linear_fpu_data = fpu.fpu_data_ptr + (fpu.fpu_data_seg << 4);
cpu_write32(linaddr + 12, linear_fpu_eip | 0xFFFF0000, x);
cpu_write32(linaddr + 16, (fpu.fpu_opcode & 0x7FF) | (linear_fpu_eip >> 4 & 0x0FFFF000), x);
cpu_write32(linaddr + 20, linear_fpu_data | 0xFFFF0000, x);
cpu_write32(linaddr + 24, linear_fpu_data >> 4 & 0x0FFFF000, x);
}
} else {
cpu_write16(linaddr, fpu.control_word, x);
cpu_write16(linaddr + 2, fpu_get_status_word(), x);
cpu_write16(linaddr + 4, fpu.tag_word, x);
if (cpu.cr[0] & CR0_PE) {
cpu_write16(linaddr + 6, fpu.fpu_eip, x);
cpu_write16(linaddr + 8, fpu.fpu_cs, x);
cpu_write16(linaddr + 10, fpu.fpu_data_ptr, x);
cpu_write16(linaddr + 12, fpu.fpu_data_seg, x);
} else {
uint32_t linear_fpu_eip = fpu.fpu_eip + (fpu.fpu_cs << 4);
uint32_t linear_fpu_data = fpu.fpu_data_ptr + (fpu.fpu_data_seg << 4);
cpu_write16(linaddr + 6, linear_fpu_eip, x);
cpu_write16(linaddr + 8, (fpu.fpu_opcode & 0x7FF) | (linear_fpu_eip >> 4 & 0xF000), x);
cpu_write16(linaddr + 10, linear_fpu_data, x);
cpu_write16(linaddr + 12, linear_fpu_data >> 4 & 0xF000, x);
}
}
return 0;
}
static int fldenv(uint32_t linaddr, int code16)
{
uint32_t temp32;
if (!code16) {
cpu_read32(linaddr, temp32, cpu.tlb_shift_read);
fpu_set_control_word(temp32);
cpu_read16(linaddr + 4, fpu.status_word, cpu.tlb_shift_read);
fpu.ftop = fpu.status_word >> 11 & 7;
fpu.status_word &= ~(7 << 11); // Clear FTOP.
cpu_read16(linaddr + 8, fpu.tag_word, cpu.tlb_shift_read);
if (cpu.cr[0] & CR0_PE) {
cpu_read32(linaddr + 12, fpu.fpu_eip, cpu.tlb_shift_read);
cpu_read32(linaddr + 16, temp32, cpu.tlb_shift_read);
fpu.fpu_cs = temp32 & 0xFFFF;
fpu.fpu_opcode = temp32 >> 16 & 0x7FF;
cpu_read32(linaddr + 20, fpu.fpu_data_ptr, cpu.tlb_shift_read);
cpu_read32(linaddr + 24, fpu.fpu_data_seg, cpu.tlb_shift_read);
} else {
fpu.fpu_cs = 0;
fpu.fpu_eip = 0;
cpu_read16(linaddr + 12, fpu.fpu_eip, cpu.tlb_shift_read);
cpu_read32(linaddr + 16, temp32, cpu.tlb_shift_read);
fpu.fpu_opcode = temp32 & 0x7FF;
fpu.fpu_eip |= temp32 << 4 & 0xFFFF0000;
cpu_read32(linaddr + 20, temp32, cpu.tlb_shift_read);
fpu.fpu_data_ptr = temp32 & 0xFFFF;
cpu_read32(linaddr + 24, temp32, cpu.tlb_shift_read);
fpu.fpu_eip |= temp32 << 4 & 0xFFFF0000;
}
} else {
cpu_read16(linaddr, temp32, cpu.tlb_shift_read);
fpu_set_control_word(temp32);
cpu_read16(linaddr + 2, fpu.status_word, cpu.tlb_shift_read);
fpu.ftop = fpu.status_word >> 11 & 7;
fpu.status_word &= ~(7 << 11); // Clear FTOP.
cpu_read16(linaddr + 4, fpu.tag_word, cpu.tlb_shift_read);
if (cpu.cr[0] & CR0_PE) {
cpu_read16(linaddr + 6, fpu.fpu_eip, cpu.tlb_shift_read);
cpu_read16(linaddr + 8, fpu.fpu_cs, cpu.tlb_shift_read);
cpu_read16(linaddr + 10, fpu.fpu_data_ptr, cpu.tlb_shift_read);
cpu_read16(linaddr + 12, fpu.fpu_data_seg, cpu.tlb_shift_read);
} else {
fpu.fpu_cs = 0;
fpu.fpu_eip = 0;
cpu_read16(linaddr + 6, fpu.fpu_eip, cpu.tlb_shift_read);
cpu_read16(linaddr + 8, temp32, cpu.tlb_shift_read);
fpu.fpu_opcode = temp32 & 0x7FF;
fpu.fpu_eip |= temp32 << 4 & 0xF0000;
cpu_read16(linaddr + 10, temp32, cpu.tlb_shift_read);
fpu.fpu_data_ptr = temp32 & 0xFFFF;
cpu_read32(linaddr + 12, temp32, cpu.tlb_shift_read);
fpu.fpu_eip |= temp32 << 4 & 0xF0000;
}
}
if (fpu.status_word & ~fpu.control_word & 0x3F)
fpu.status_word |= 0x8080;
else
fpu.status_word &= ~0x8080;
return 0;
}
static void fpu_watchpoint(void)
{
// For debugging purposes
//if(VIRT_EIP() == 0x71961cad) __asm__("int3");
//if(fpu.st[5].fraction == 0x00000006e8b877f6) __asm__("int3");
}
static void fpu_watchpoint2(void)
{
// For debugging purposes
//if(fpu.fpu_opcode == 0x77F8) __asm__("int3");
}
#define FPU_EXCEP() return 1
#define FPU_ABORT() \
do { \
fpu_watchpoint2(); \
return 0; \
} while (0) // Not an exception, so keep on goings
// Run a FPU operation that does not require memory
#define OP(op, reg) (op & 7) << 3 | reg
int fpu_reg_op(struct decoded_instruction* i, uint32_t flags)
{
UNUSED(flags);
UNUSED(fpu_exception_raised);
UNUSED(fpu_get_st_ptr);
uint32_t opcode = i->imm32;
floatx80 temp80;
if (fpu_nm_check())
return 1;
#ifdef INSTRUMENT
cpu_instrument_pre_fpu();
#endif
fpu_watchpoint();
fpu.status.float_exception_flags = 0;
int smaller_opcode = (opcode >> 5 & 0x38) | (opcode >> 3 & 7);
switch (smaller_opcode) {
case OP(0xD8, 0):
case OP(0xD8, 1):
case OP(0xD8, 4):
case OP(0xD8, 5):
case OP(0xD8, 6):
case OP(0xD8, 7):
case OP(0xDC, 0):
case OP(0xDC, 1):
case OP(0xDC, 4):
case OP(0xDC, 5):
case OP(0xDC, 6):
case OP(0xDC, 7):
case OP(0xDE, 0):
case OP(0xDE, 1):
case OP(0xDE, 4):
case OP(0xDE, 5):
case OP(0xDE, 6):
case OP(0xDE, 7): {
int st_index = opcode & 7;
floatx80 dst;
if (fpu_fwait())
return 1;
fpu_update_pointers(opcode);
if (fpu_check_stack_underflow(0, 1) || fpu_check_stack_underflow(st_index, 1))
FPU_ABORT();
switch (smaller_opcode & 7) {
case 0: // FADD - Floating point add
dst = floatx80_add(fpu_get_st(0), fpu_get_st(st_index), &fpu.status);
break;
case 1: // FMUL - Floating point multiply
dst = floatx80_mul(fpu_get_st(0), fpu_get_st(st_index), &fpu.status);
break;
case 4: // FSUB - Floating point subtract
dst = floatx80_sub(fpu_get_st(0), fpu_get_st(st_index), &fpu.status);
break;
case 5: // FSUBR - Floating point subtract reverse
dst = floatx80_sub(fpu_get_st(st_index), fpu_get_st(0), &fpu.status);
break;
case 6: // FDIV - Floating point divide
dst = floatx80_div(fpu_get_st(0), fpu_get_st(st_index), &fpu.status);
break;
case 7: // FDIVR - Floating point divide reverse
dst = floatx80_div(fpu_get_st(st_index), fpu_get_st(0), &fpu.status);
break;
}
if (!fpu_check_exceptions()) {
if (smaller_opcode & 32) {
fpu_set_st(st_index, dst);
if (smaller_opcode & 16)
fpu_pop();
} else
fpu_set_st(0, dst);
}
break;
}
case OP(0xD8, 2): // FCOM - Floating point compare
case OP(0xD8, 3): // FCOMP - Floating point compare and pop
case OP(0xDC, 2):
case OP(0xDC, 3):
case OP(0xDE, 2): { // Aliases of the DB opcodes
if (fpu_fwait())
FPU_ABORT();
if (fpu_check_stack_underflow(0, 1) || fpu_check_stack_underflow(opcode & 7, 1)) {
SET_C0(1);
SET_C2(1);
SET_C3(1);
}
fpu_update_pointers(opcode);
if (!fpu_fcom(fpu_get_st(0), fpu_get_st(opcode & 7), 0)) {
if (smaller_opcode & 1 || smaller_opcode == (OP(0xDE, 2)))
fpu_pop();
}
break;
}
case OP(0xD9, 0): // FLD - Load floating point value
if (fpu_fwait())
FPU_ABORT();
fpu_update_pointers(opcode);
if (fpu_check_stack_underflow(opcode & 7, 1) || fpu_check_push())
FPU_ABORT();
temp80 = fpu_get_st(opcode & 7);
fpu_push(temp80);
break;
case OP(0xD9, 1): // FXCH - Floating point exchange
case OP(0xDD, 1):
case OP(0xDF, 1): // alias of FXCH
if (fpu_fwait())
FPU_ABORT();
fpu_update_pointers(opcode);
if (fpu_check_stack_underflow(0, 1) || fpu_check_stack_underflow(1, 1))
FPU_ABORT();
temp80 = fpu_get_st(0);
fpu_set_st(0, fpu_get_st(opcode & 7));
fpu_set_st(opcode & 7, temp80);
break;
case OP(0xD9, 2): // FNOP
if (fpu_fwait())
FPU_ABORT();
fpu_update_pointers(opcode);
break;
case OP(0xD9, 4):
if (fpu_fwait())
FPU_ABORT();
fpu_update_pointers(opcode);
if ((opcode & 7) != 5)
if (fpu_check_stack_underflow(0, 1))
FPU_ABORT();
temp80 = fpu_get_st(0);
switch (opcode & 7) {
case 0: // FCHS - Flip sign of floating point number
floatx80_chs(&temp80);
break;
case 1: // FABS - Find absolute value of floating point number
floatx80_abs(&temp80);
break;
case 4: // FTST - Compare floating point register to 0
if (fpu_fcom(temp80, Zero, 0))
FPU_ABORT();
return 0;
case 5: { // FXAM - Examine floating point number
int unordered = 0;
uint16_t exponent;
uint64_t mantissa;
floatx80_unpack(&temp80, exponent, mantissa);
if (fpu_get_tag(0) == FPU_TAG_EMPTY)
unordered = 5;
else {
if (is_invalid(exponent, mantissa))
unordered = 0;
else if (is_nan(exponent, mantissa))
unordered = 1;
else if (is_infinity(exponent, mantissa))
unordered = 3;
else if (is_zero_any_sign(exponent, mantissa))
unordered = 4;
else if (is_denormal(exponent, mantissa))
unordered = 6;
else
unordered = 2;
}
SET_C0(unordered & 1);
SET_C1(exponent >> 15 & 1); // Get sign
SET_C2(unordered >> 1 & 1);
SET_C3(unordered >> 2 & 1);
return 0;
}
}
fpu_set_st(0, temp80);
break;
case OP(0xD9, 5): // FLD - Load floating point constants
if (fpu_fwait())
FPU_ABORT();
fpu_update_pointers(opcode);
if (fpu_check_push())
FPU_ABORT();
fpu_push(*Constants[opcode & 7]);
break;
case OP(0xD9, 6): { // Various complex FPU operations
if (fpu_fwait())
FPU_ABORT();
fpu_update_pointers(opcode);
floatx80 res, temp;
int temp2, old_rounding;
switch (opcode & 7) {
case 0: // D9 F0: F2XM1 - Compute 2^ST(0) - 1
if (fpu_check_stack_underflow(0, 1))
FPU_ABORT();
res = f2xm1(fpu_get_st(0), &fpu.status);
if (!fpu_check_exceptions())
fpu_set_st(0, res);
break;
case 1: // D9 F1: FYL2X - Compute ST(1) * log2(ST(0)) and then pop
if (fpu_check_stack_underflow(0, 1) || fpu_check_stack_underflow(1, 1))
FPU_ABORT();
old_rounding = fpu.status.float_rounding_precision;
fpu.status.float_rounding_precision = 80;
res = fyl2x(fpu_get_st(0), fpu_get_st(1), &fpu.status);
fpu.status.float_rounding_precision = old_rounding;
if (!fpu_check_exceptions()) {
fpu_set_st(1, res);
fpu_pop();
}
break;
case 2: // D9 F2: FPTAN - Compute tan(ST(0)) partially
if (fpu_check_stack_underflow(0, 1))
FPU_ABORT();
res = fpu_get_st(0);
if (!ftan(&res, &fpu.status))
fpu_set_st(0, res);
break;
case 3: // D9 F3: FPATAN - Compute tan-1(ST(0)) partially
if (fpu_check_stack_underflow(0, 1) || fpu_check_stack_underflow(1, 1))
FPU_ABORT();
res = fpatan(fpu_get_st(0), fpu_get_st(1), &fpu.status);
if (!fpu_check_exceptions()) {
fpu_pop();
fpu_set_st(0, res);
}
break;
case 4: // D9 F4: FXTRACT - Extract Exponent and mantissa of ST0
if (fpu_check_stack_underflow(0, 1))
FPU_ABORT();
if (fpu_check_stack_overflow(-1))
FPU_ABORT();
temp = fpu_get_st(0);
res = floatx80_extract(&temp, &fpu.status);
if (!fpu_check_exceptions()) {
fpu_set_st(0, res);
fpu_push(temp);
}
break;
case 5: { // D9 F5: FPREM1 - Partial floating point remainder
floatx80 st0 = fpu_get_st(0), st1 = fpu_get_st(1);
uint64_t quo;
temp2 = floatx80_ieee754_remainder(st0, st1, &temp, &quo, &fpu.status);
if (!fpu_check_exceptions()) {
if (!(temp2 < 0)) {
SET_C0(0);
SET_C2(0);
SET_C3(0);
if (flags) {
SET_C2(1);
} else {
// 1 2 4 - 1 3 0
if (quo & 1)
SET_C1(1);
if (quo & 2)
SET_C3(1);
if (quo & 4)
SET_C0(1);
}
}
fpu_set_st(0, temp);
}
break;
case 6: // D9 F6: FDECSTP - Decrement stack pointer
SET_C1(0);
fpu.ftop = (fpu.ftop - 1) & 7;
break;
case 7: // D9 F7: FINCSTP - Increment stack pointer
SET_C1(0);
fpu.ftop = (fpu.ftop + 1) & 7;
break;
}
}
break;
}
case OP(0xD9, 7): {
if (fpu_fwait())
return 1;
fpu_update_pointers(opcode);
// Check for FPU registers
if (fpu_check_stack_underflow(0, 1))
FPU_ABORT();
int flags, pop = 0;
floatx80 dest;
uint64_t quotient;
switch (opcode & 7) {
case 0: // FPREM - Floating point partial remainder (8087/80287 compatible)
if (fpu_check_stack_underflow(1, 1))
FPU_ABORT();
flags = floatx80_remainder(fpu_get_st(0), fpu_get_st(1), &dest, "ient, &fpu.status);
if (!fpu_check_exceptions()) {
if (flags < 0) {
SET_C0(0);
SET_C1(0);
SET_C2(0);
SET_C3(0);
} else {