v.rs

use ckb_vm_definitions::instructions as insts;

use super::utils::{self, funct3, opcode, rd, rs1, rs2};
use super::{
    set_instruction_length_4, Instruction, Itype, Register, Rtype, VItype, VVtype, VXtype,
};

// vle8_v     ... 000 . 00000 ..... 000 ..... 0000111 @r2_nfvm
// vle16_v    ... 000 . 00000 ..... 101 ..... 0000111 @r2_nfvm
// vle32_v    ... 000 . 00000 ..... 110 ..... 0000111 @r2_nfvm
// vle64_v    ... 000 . 00000 ..... 111 ..... 0000111 @r2_nfvm
// vle128_v   ... 100 . 00000 ..... 000 ..... 0000111 @r2_nfvm
// vle256_v   ... 100 . 00000 ..... 101 ..... 0000111 @r2_nfvm
// vle512_v   ... 100 . 00000 ..... 110 ..... 0000111 @r2_nfvm
// vle1024_v  ... 100 . 00000 ..... 111 ..... 0000111 @r2_nfvm
// vse8_v     ... 000 . 00000 ..... 000 ..... 0100111 @r2_nfvm
// vse16_v    ... 000 . 00000 ..... 101 ..... 0100111 @r2_nfvm
// vse32_v    ... 000 . 00000 ..... 110 ..... 0100111 @r2_nfvm
// vse64_v    ... 000 . 00000 ..... 111 ..... 0100111 @r2_nfvm
// vse128_v   ... 100 . 00000 ..... 000 ..... 0100111 @r2_nfvm
// vse256_v   ... 100 . 00000 ..... 101 ..... 0100111 @r2_nfvm
// vse512_v   ... 100 . 00000 ..... 110 ..... 0100111 @r2_nfvm
// vse1024_v  ... 100 . 00000 ..... 111 ..... 0100111 @r2_nfvm

// # Vector unit-stride mask load/store insns.
// vle1_v     000 000 1 01011 ..... 000 ..... 0000111 @r2
// vse1_v     000 000 1 01011 ..... 000 ..... 0100111 @r2

// # Vector strided insns.
// vlse8_v     ... 010 . ..... ..... 000 ..... 0000111 @r_nfvm
// vlse16_v    ... 010 . ..... ..... 101 ..... 0000111 @r_nfvm
// vlse32_v    ... 010 . ..... ..... 110 ..... 0000111 @r_nfvm
// vlse64_v    ... 010 . ..... ..... 111 ..... 0000111 @r_nfvm
// vlse128_v   ... 110 . ..... ..... 000 ..... 0000111 @r_nfvm
// vlse256_v   ... 110 . ..... ..... 101 ..... 0000111 @r_nfvm
// vlse512_v   ... 110 . ..... ..... 110 ..... 0000111 @r_nfvm
// vlse1024_v  ... 110 . ..... ..... 111 ..... 0000111 @r_nfvm
// vsse8_v     ... 010 . ..... ..... 000 ..... 0100111 @r_nfvm
// vsse16_v    ... 010 . ..... ..... 101 ..... 0100111 @r_nfvm
// vsse32_v    ... 010 . ..... ..... 110 ..... 0100111 @r_nfvm
// vsse64_v    ... 010 . ..... ..... 111 ..... 0100111 @r_nfvm
// vsse128_v   ... 110 . ..... ..... 000 ..... 0100111 @r_nfvm
// vsse256_v   ... 110 . ..... ..... 101 ..... 0100111 @r_nfvm
// vsse512_v   ... 110 . ..... ..... 110 ..... 0100111 @r_nfvm
// vsse1024_v  ... 110 . ..... ..... 111 ..... 0100111 @r_nfvm

// # Vector ordered-indexed and unordered-indexed load insns.
// vlxei8_v      ... 0-1 . ..... ..... 000 ..... 0000111 @r_nfvm
// vlxei16_v     ... 0-1 . ..... ..... 101 ..... 0000111 @r_nfvm
// vlxei32_v     ... 0-1 . ..... ..... 110 ..... 0000111 @r_nfvm
// vlxei64_v     ... 0-1 . ..... ..... 111 ..... 0000111 @r_nfvm

// # Vector ordered-indexed and unordered-indexed store insns.
// vsxei8_v      ... 0-1 . ..... ..... 000 ..... 0100111 @r_nfvm
// vsxei16_v     ... 0-1 . ..... ..... 101 ..... 0100111 @r_nfvm
// vsxei32_v     ... 0-1 . ..... ..... 110 ..... 0100111 @r_nfvm
// vsxei64_v     ... 0-1 . ..... ..... 111 ..... 0100111 @r_nfvm

// # Vector unit-stride fault-only-first load insns.
// vle8ff_v      ... 000 . 10000 ..... 000 ..... 0000111 @r2_nfvm
// vle16ff_v     ... 000 . 10000 ..... 101 ..... 0000111 @r2_nfvm
// vle32ff_v     ... 000 . 10000 ..... 110 ..... 0000111 @r2_nfvm
// vle64ff_v     ... 000 . 10000 ..... 111 ..... 0000111 @r2_nfvm

// # Vector whole register insns
// vl1re8_v      000 000 1 01000 ..... 000 ..... 0000111 @r2
// vl1re16_v     000 000 1 01000 ..... 101 ..... 0000111 @r2
// vl1re32_v     000 000 1 01000 ..... 110 ..... 0000111 @r2
// vl1re64_v     000 000 1 01000 ..... 111 ..... 0000111 @r2
// vl2re8_v      001 000 1 01000 ..... 000 ..... 0000111 @r2
// vl2re16_v     001 000 1 01000 ..... 101 ..... 0000111 @r2
// vl2re32_v     001 000 1 01000 ..... 110 ..... 0000111 @r2
// vl2re64_v     001 000 1 01000 ..... 111 ..... 0000111 @r2
// vl4re8_v      011 000 1 01000 ..... 000 ..... 0000111 @r2
// vl4re16_v     011 000 1 01000 ..... 101 ..... 0000111 @r2
// vl4re32_v     011 000 1 01000 ..... 110 ..... 0000111 @r2
// vl4re64_v     011 000 1 01000 ..... 111 ..... 0000111 @r2
// vl8re8_v      111 000 1 01000 ..... 000 ..... 0000111 @r2
// vl8re16_v     111 000 1 01000 ..... 101 ..... 0000111 @r2
// vl8re32_v     111 000 1 01000 ..... 110 ..... 0000111 @r2
// vl8re64_v     111 000 1 01000 ..... 111 ..... 0000111 @r2
// vs1r_v        000 000 1 01000 ..... 000 ..... 0100111 @r2
// vs2r_v        001 000 1 01000 ..... 000 ..... 0100111 @r2
// vs4r_v        011 000 1 01000 ..... 000 ..... 0100111 @r2
// vs8r_v        111 000 1 01000 ..... 000 ..... 0100111 @r2

// #*** Vector AMO operations are encoded under the standard AMO major opcode ***
// vamoswapei8_v   00001 . . ..... ..... 000 ..... 0101111 @r_wdvm
// vamoswapei16_v  00001 . . ..... ..... 101 ..... 0101111 @r_wdvm
// vamoswapei32_v  00001 . . ..... ..... 110 ..... 0101111 @r_wdvm
// vamoaddei8_v    00000 . . ..... ..... 000 ..... 0101111 @r_wdvm
// vamoaddei16_v   00000 . . ..... ..... 101 ..... 0101111 @r_wdvm
// vamoaddei32_v   00000 . . ..... ..... 110 ..... 0101111 @r_wdvm
// vamoxorei8_v    00100 . . ..... ..... 000 ..... 0101111 @r_wdvm
// vamoxorei16_v   00100 . . ..... ..... 101 ..... 0101111 @r_wdvm
// vamoxorei32_v   00100 . . ..... ..... 110 ..... 0101111 @r_wdvm
// vamoandei8_v    01100 . . ..... ..... 000 ..... 0101111 @r_wdvm
// vamoandei16_v   01100 . . ..... ..... 101 ..... 0101111 @r_wdvm
// vamoandei32_v   01100 . . ..... ..... 110 ..... 0101111 @r_wdvm
// vamoorei8_v     01000 . . ..... ..... 000 ..... 0101111 @r_wdvm
// vamoorei16_v    01000 . . ..... ..... 101 ..... 0101111 @r_wdvm
// vamoorei32_v    01000 . . ..... ..... 110 ..... 0101111 @r_wdvm
// vamominei8_v    10000 . . ..... ..... 000 ..... 0101111 @r_wdvm
// vamominei16_v   10000 . . ..... ..... 101 ..... 0101111 @r_wdvm
// vamominei32_v   10000 . . ..... ..... 110 ..... 0101111 @r_wdvm
// vamomaxei8_v    10100 . . ..... ..... 000 ..... 0101111 @r_wdvm
// vamomaxei16_v   10100 . . ..... ..... 101 ..... 0101111 @r_wdvm
// vamomaxei32_v   10100 . . ..... ..... 110 ..... 0101111 @r_wdvm
// vamominuei8_v   11000 . . ..... ..... 000 ..... 0101111 @r_wdvm
// vamominuei16_v  11000 . . ..... ..... 101 ..... 0101111 @r_wdvm
// vamominuei32_v  11000 . . ..... ..... 110 ..... 0101111 @r_wdvm
// vamomaxuei8_v   11100 . . ..... ..... 000 ..... 0101111 @r_wdvm
// vamomaxuei16_v  11100 . . ..... ..... 101 ..... 0101111 @r_wdvm
// vamomaxuei32_v  11100 . . ..... ..... 110 ..... 0101111 @r_wdvm

// # *** new major opcode OP-V ***
// vadd_vv         000000 . ..... ..... 000 ..... 1010111 @r_vm
// vadd_vx         000000 . ..... ..... 100 ..... 1010111 @r_vm
// vadd_vi         000000 . ..... ..... 011 ..... 1010111 @r_vm
// vsub_vv         000010 . ..... ..... 000 ..... 1010111 @r_vm
// vsub_vx         000010 . ..... ..... 100 ..... 1010111 @r_vm
// vrsub_vx        000011 . ..... ..... 100 ..... 1010111 @r_vm
// vrsub_vi        000011 . ..... ..... 011 ..... 1010111 @r_vm
// vwaddu_vv       110000 . ..... ..... 010 ..... 1010111 @r_vm
// vwaddu_vx       110000 . ..... ..... 110 ..... 1010111 @r_vm
// vwadd_vv        110001 . ..... ..... 010 ..... 1010111 @r_vm
// vwadd_vx        110001 . ..... ..... 110 ..... 1010111 @r_vm
// vwsubu_vv       110010 . ..... ..... 010 ..... 1010111 @r_vm
// vwsubu_vx       110010 . ..... ..... 110 ..... 1010111 @r_vm
// vwsub_vv        110011 . ..... ..... 010 ..... 1010111 @r_vm
// vwsub_vx        110011 . ..... ..... 110 ..... 1010111 @r_vm
// vwaddu_wv       110100 . ..... ..... 010 ..... 1010111 @r_vm
// vwaddu_wx       110100 . ..... ..... 110 ..... 1010111 @r_vm
// vwadd_wv        110101 . ..... ..... 010 ..... 1010111 @r_vm
// vwadd_wx        110101 . ..... ..... 110 ..... 1010111 @r_vm
// vwsubu_wv       110110 . ..... ..... 010 ..... 1010111 @r_vm
// vwsubu_wx       110110 . ..... ..... 110 ..... 1010111 @r_vm
// vwsub_wv        110111 . ..... ..... 010 ..... 1010111 @r_vm
// vwsub_wx        110111 . ..... ..... 110 ..... 1010111 @r_vm
// vadc_vvm        010000 0 ..... ..... 000 ..... 1010111 @r_vm_1
// vadc_vxm        010000 0 ..... ..... 100 ..... 1010111 @r_vm_1
// vadc_vim        010000 0 ..... ..... 011 ..... 1010111 @r_vm_1
// vmadc_vvm       010001 . ..... ..... 000 ..... 1010111 @r_vm
// vmadc_vxm       010001 . ..... ..... 100 ..... 1010111 @r_vm
// vmadc_vim       010001 . ..... ..... 011 ..... 1010111 @r_vm
// vsbc_vvm        010010 0 ..... ..... 000 ..... 1010111 @r_vm_1
// vsbc_vxm        010010 0 ..... ..... 100 ..... 1010111 @r_vm_1
// vmsbc_vvm       010011 . ..... ..... 000 ..... 1010111 @r_vm
// vmsbc_vxm       010011 . ..... ..... 100 ..... 1010111 @r_vm
// vand_vv         001001 . ..... ..... 000 ..... 1010111 @r_vm
// vand_vx         001001 . ..... ..... 100 ..... 1010111 @r_vm
// vand_vi         001001 . ..... ..... 011 ..... 1010111 @r_vm
// vor_vv          001010 . ..... ..... 000 ..... 1010111 @r_vm
// vor_vx          001010 . ..... ..... 100 ..... 1010111 @r_vm
// vor_vi          001010 . ..... ..... 011 ..... 1010111 @r_vm
// vxor_vv         001011 . ..... ..... 000 ..... 1010111 @r_vm
// vxor_vx         001011 . ..... ..... 100 ..... 1010111 @r_vm
// vxor_vi         001011 . ..... ..... 011 ..... 1010111 @r_vm
// vsll_vv         100101 . ..... ..... 000 ..... 1010111 @r_vm
// vsll_vx         100101 . ..... ..... 100 ..... 1010111 @r_vm
// vsll_vi         100101 . ..... ..... 011 ..... 1010111 @r_vm
// vsrl_vv         101000 . ..... ..... 000 ..... 1010111 @r_vm
// vsrl_vx         101000 . ..... ..... 100 ..... 1010111 @r_vm
// vsrl_vi         101000 . ..... ..... 011 ..... 1010111 @r_vm
// vsra_vv         101001 . ..... ..... 000 ..... 1010111 @r_vm
// vsra_vx         101001 . ..... ..... 100 ..... 1010111 @r_vm
// vsra_vi         101001 . ..... ..... 011 ..... 1010111 @r_vm
// vnsrl_wv        101100 . ..... ..... 000 ..... 1010111 @r_vm
// vnsrl_wx        101100 . ..... ..... 100 ..... 1010111 @r_vm
// vnsrl_wi        101100 . ..... ..... 011 ..... 1010111 @r_vm
// vnsra_wv        101101 . ..... ..... 000 ..... 1010111 @r_vm
// vnsra_wx        101101 . ..... ..... 100 ..... 1010111 @r_vm
// vnsra_wi        101101 . ..... ..... 011 ..... 1010111 @r_vm
// vmseq_vv        011000 . ..... ..... 000 ..... 1010111 @r_vm
// vmseq_vx        011000 . ..... ..... 100 ..... 1010111 @r_vm
// vmseq_vi        011000 . ..... ..... 011 ..... 1010111 @r_vm
// vmsne_vv        011001 . ..... ..... 000 ..... 1010111 @r_vm
// vmsne_vx        011001 . ..... ..... 100 ..... 1010111 @r_vm
// vmsne_vi        011001 . ..... ..... 011 ..... 1010111 @r_vm
// vmsltu_vv       011010 . ..... ..... 000 ..... 1010111 @r_vm
// vmsltu_vx       011010 . ..... ..... 100 ..... 1010111 @r_vm
// vmslt_vv        011011 . ..... ..... 000 ..... 1010111 @r_vm
// vmslt_vx        011011 . ..... ..... 100 ..... 1010111 @r_vm
// vmsleu_vv       011100 . ..... ..... 000 ..... 1010111 @r_vm
// vmsleu_vx       011100 . ..... ..... 100 ..... 1010111 @r_vm
// vmsleu_vi       011100 . ..... ..... 011 ..... 1010111 @r_vm
// vmsle_vv        011101 . ..... ..... 000 ..... 1010111 @r_vm
// vmsle_vx        011101 . ..... ..... 100 ..... 1010111 @r_vm
// vmsle_vi        011101 . ..... ..... 011 ..... 1010111 @r_vm
// vmsgtu_vx       011110 . ..... ..... 100 ..... 1010111 @r_vm
// vmsgtu_vi       011110 . ..... ..... 011 ..... 1010111 @r_vm
// vmsgt_vx        011111 . ..... ..... 100 ..... 1010111 @r_vm
// vmsgt_vi        011111 . ..... ..... 011 ..... 1010111 @r_vm
// vminu_vv        000100 . ..... ..... 000 ..... 1010111 @r_vm
// vminu_vx        000100 . ..... ..... 100 ..... 1010111 @r_vm
// vmin_vv         000101 . ..... ..... 000 ..... 1010111 @r_vm
// vmin_vx         000101 . ..... ..... 100 ..... 1010111 @r_vm
// vmaxu_vv        000110 . ..... ..... 000 ..... 1010111 @r_vm
// vmaxu_vx        000110 . ..... ..... 100 ..... 1010111 @r_vm
// vmax_vv         000111 . ..... ..... 000 ..... 1010111 @r_vm
// vmax_vx         000111 . ..... ..... 100 ..... 1010111 @r_vm
// vmul_vv         100101 . ..... ..... 010 ..... 1010111 @r_vm
// vmul_vx         100101 . ..... ..... 110 ..... 1010111 @r_vm
// vmulh_vv        100111 . ..... ..... 010 ..... 1010111 @r_vm
// vmulh_vx        100111 . ..... ..... 110 ..... 1010111 @r_vm
// vmulhu_vv       100100 . ..... ..... 010 ..... 1010111 @r_vm
// vmulhu_vx       100100 . ..... ..... 110 ..... 1010111 @r_vm
// vmulhsu_vv      100110 . ..... ..... 010 ..... 1010111 @r_vm
// vmulhsu_vx      100110 . ..... ..... 110 ..... 1010111 @r_vm
// vdivu_vv        100000 . ..... ..... 010 ..... 1010111 @r_vm
// vdivu_vx        100000 . ..... ..... 110 ..... 1010111 @r_vm
// vdiv_vv         100001 . ..... ..... 010 ..... 1010111 @r_vm
// vdiv_vx         100001 . ..... ..... 110 ..... 1010111 @r_vm
// vremu_vv        100010 . ..... ..... 010 ..... 1010111 @r_vm
// vremu_vx        100010 . ..... ..... 110 ..... 1010111 @r_vm
// vrem_vv         100011 . ..... ..... 010 ..... 1010111 @r_vm
// vrem_vx         100011 . ..... ..... 110 ..... 1010111 @r_vm
// vwmulu_vv       111000 . ..... ..... 010 ..... 1010111 @r_vm
// vwmulu_vx       111000 . ..... ..... 110 ..... 1010111 @r_vm
// vwmulsu_vv      111010 . ..... ..... 010 ..... 1010111 @r_vm
// vwmulsu_vx      111010 . ..... ..... 110 ..... 1010111 @r_vm
// vwmul_vv        111011 . ..... ..... 010 ..... 1010111 @r_vm
// vwmul_vx        111011 . ..... ..... 110 ..... 1010111 @r_vm
// vmacc_vv        101101 . ..... ..... 010 ..... 1010111 @r_vm
// vmacc_vx        101101 . ..... ..... 110 ..... 1010111 @r_vm
// vnmsac_vv       101111 . ..... ..... 010 ..... 1010111 @r_vm
// vnmsac_vx       101111 . ..... ..... 110 ..... 1010111 @r_vm
// vmadd_vv        101001 . ..... ..... 010 ..... 1010111 @r_vm
// vmadd_vx        101001 . ..... ..... 110 ..... 1010111 @r_vm
// vnmsub_vv       101011 . ..... ..... 010 ..... 1010111 @r_vm
// vnmsub_vx       101011 . ..... ..... 110 ..... 1010111 @r_vm
// vwmaccu_vv      111100 . ..... ..... 010 ..... 1010111 @r_vm
// vwmaccu_vx      111100 . ..... ..... 110 ..... 1010111 @r_vm
// vwmacc_vv       111101 . ..... ..... 010 ..... 1010111 @r_vm
// vwmacc_vx       111101 . ..... ..... 110 ..... 1010111 @r_vm
// vwmaccsu_vv     111111 . ..... ..... 010 ..... 1010111 @r_vm
// vwmaccsu_vx     111111 . ..... ..... 110 ..... 1010111 @r_vm
// vwmaccus_vx     111110 . ..... ..... 110 ..... 1010111 @r_vm
// vmv_v_v         010111 1 00000 ..... 000 ..... 1010111 @r2
// vmv_v_x         010111 1 00000 ..... 100 ..... 1010111 @r2
// vmv_v_i         010111 1 00000 ..... 011 ..... 1010111 @r2
// vmerge_vvm      010111 0 ..... ..... 000 ..... 1010111 @r_vm_0
// vmerge_vxm      010111 0 ..... ..... 100 ..... 1010111 @r_vm_0
// vmerge_vim      010111 0 ..... ..... 011 ..... 1010111 @r_vm_0
// vsaddu_vv       100000 . ..... ..... 000 ..... 1010111 @r_vm
// vsaddu_vx       100000 . ..... ..... 100 ..... 1010111 @r_vm
// vsaddu_vi       100000 . ..... ..... 011 ..... 1010111 @r_vm
// vsadd_vv        100001 . ..... ..... 000 ..... 1010111 @r_vm
// vsadd_vx        100001 . ..... ..... 100 ..... 1010111 @r_vm
// vsadd_vi        100001 . ..... ..... 011 ..... 1010111 @r_vm
// vssubu_vv       100010 . ..... ..... 000 ..... 1010111 @r_vm
// vssubu_vx       100010 . ..... ..... 100 ..... 1010111 @r_vm
// vssub_vv        100011 . ..... ..... 000 ..... 1010111 @r_vm
// vssub_vx        100011 . ..... ..... 100 ..... 1010111 @r_vm
// vaadd_vv        001001 . ..... ..... 010 ..... 1010111 @r_vm
// vaadd_vx        001001 . ..... ..... 110 ..... 1010111 @r_vm
// vaaddu_vv       001000 . ..... ..... 010 ..... 1010111 @r_vm
// vaaddu_vx       001000 . ..... ..... 110 ..... 1010111 @r_vm
// vasub_vv        001011 . ..... ..... 010 ..... 1010111 @r_vm
// vasub_vx        001011 . ..... ..... 110 ..... 1010111 @r_vm
// vasubu_vv       001010 . ..... ..... 010 ..... 1010111 @r_vm
// vasubu_vx       001010 . ..... ..... 110 ..... 1010111 @r_vm
// vsmul_vv        100111 . ..... ..... 000 ..... 1010111 @r_vm
// vsmul_vx        100111 . ..... ..... 100 ..... 1010111 @r_vm
// vssrl_vv        101010 . ..... ..... 000 ..... 1010111 @r_vm
// vssrl_vx        101010 . ..... ..... 100 ..... 1010111 @r_vm
// vssrl_vi        101010 . ..... ..... 011 ..... 1010111 @r_vm
// vssra_vv        101011 . ..... ..... 000 ..... 1010111 @r_vm
// vssra_vx        101011 . ..... ..... 100 ..... 1010111 @r_vm
// vssra_vi        101011 . ..... ..... 011 ..... 1010111 @r_vm
// vnclipu_wv      101110 . ..... ..... 000 ..... 1010111 @r_vm
// vnclipu_wx      101110 . ..... ..... 100 ..... 1010111 @r_vm
// vnclipu_wi      101110 . ..... ..... 011 ..... 1010111 @r_vm
// vnclip_wv       101111 . ..... ..... 000 ..... 1010111 @r_vm
// vnclip_wx       101111 . ..... ..... 100 ..... 1010111 @r_vm
// vnclip_wi       101111 . ..... ..... 011 ..... 1010111 @r_vm
// vfadd_vv        000000 . ..... ..... 001 ..... 1010111 @r_vm
// vfadd_vf        000000 . ..... ..... 101 ..... 1010111 @r_vm
// vfsub_vv        000010 . ..... ..... 001 ..... 1010111 @r_vm
// vfsub_vf        000010 . ..... ..... 101 ..... 1010111 @r_vm
// vfrsub_vf       100111 . ..... ..... 101 ..... 1010111 @r_vm
// vfwadd_vv       110000 . ..... ..... 001 ..... 1010111 @r_vm
// vfwadd_vf       110000 . ..... ..... 101 ..... 1010111 @r_vm
// vfwadd_wv       110100 . ..... ..... 001 ..... 1010111 @r_vm
// vfwadd_wf       110100 . ..... ..... 101 ..... 1010111 @r_vm
// vfwsub_vv       110010 . ..... ..... 001 ..... 1010111 @r_vm
// vfwsub_vf       110010 . ..... ..... 101 ..... 1010111 @r_vm
// vfwsub_wv       110110 . ..... ..... 001 ..... 1010111 @r_vm
// vfwsub_wf       110110 . ..... ..... 101 ..... 1010111 @r_vm
// vfmul_vv        100100 . ..... ..... 001 ..... 1010111 @r_vm
// vfmul_vf        100100 . ..... ..... 101 ..... 1010111 @r_vm
// vfdiv_vv        100000 . ..... ..... 001 ..... 1010111 @r_vm
// vfdiv_vf        100000 . ..... ..... 101 ..... 1010111 @r_vm
// vfrdiv_vf       100001 . ..... ..... 101 ..... 1010111 @r_vm
// vfwmul_vv       111000 . ..... ..... 001 ..... 1010111 @r_vm
// vfwmul_vf       111000 . ..... ..... 101 ..... 1010111 @r_vm
// vfmacc_vv       101100 . ..... ..... 001 ..... 1010111 @r_vm
// vfnmacc_vv      101101 . ..... ..... 001 ..... 1010111 @r_vm
// vfnmacc_vf      101101 . ..... ..... 101 ..... 1010111 @r_vm
// vfmacc_vf       101100 . ..... ..... 101 ..... 1010111 @r_vm
// vfmsac_vv       101110 . ..... ..... 001 ..... 1010111 @r_vm
// vfmsac_vf       101110 . ..... ..... 101 ..... 1010111 @r_vm
// vfnmsac_vv      101111 . ..... ..... 001 ..... 1010111 @r_vm
// vfnmsac_vf      101111 . ..... ..... 101 ..... 1010111 @r_vm
// vfmadd_vv       101000 . ..... ..... 001 ..... 1010111 @r_vm
// vfmadd_vf       101000 . ..... ..... 101 ..... 1010111 @r_vm
// vfnmadd_vv      101001 . ..... ..... 001 ..... 1010111 @r_vm
// vfnmadd_vf      101001 . ..... ..... 101 ..... 1010111 @r_vm
// vfmsub_vv       101010 . ..... ..... 001 ..... 1010111 @r_vm
// vfmsub_vf       101010 . ..... ..... 101 ..... 1010111 @r_vm
// vfnmsub_vv      101011 . ..... ..... 001 ..... 1010111 @r_vm
// vfnmsub_vf      101011 . ..... ..... 101 ..... 1010111 @r_vm
// vfwmacc_vv      111100 . ..... ..... 001 ..... 1010111 @r_vm
// vfwmacc_vf      111100 . ..... ..... 101 ..... 1010111 @r_vm
// vfwnmacc_vv     111101 . ..... ..... 001 ..... 1010111 @r_vm
// vfwnmacc_vf     111101 . ..... ..... 101 ..... 1010111 @r_vm
// vfwmsac_vv      111110 . ..... ..... 001 ..... 1010111 @r_vm
// vfwmsac_vf      111110 . ..... ..... 101 ..... 1010111 @r_vm
// vfwnmsac_vv     111111 . ..... ..... 001 ..... 1010111 @r_vm
// vfwnmsac_vf     111111 . ..... ..... 101 ..... 1010111 @r_vm
// vfsqrt_v        010011 . ..... 00000 001 ..... 1010111 @r2_vm
// vfrsqrte7_v     010011 . ..... 00100 001 ..... 1010111 @r2_vm
// vfrece7_v       010011 . ..... 00101 001 ..... 1010111 @r2_vm
// vfmin_vv        000100 . ..... ..... 001 ..... 1010111 @r_vm
// vfmin_vf        000100 . ..... ..... 101 ..... 1010111 @r_vm
// vfmax_vv        000110 . ..... ..... 001 ..... 1010111 @r_vm
// vfmax_vf        000110 . ..... ..... 101 ..... 1010111 @r_vm
// vfsgnj_vv       001000 . ..... ..... 001 ..... 1010111 @r_vm
// vfsgnj_vf       001000 . ..... ..... 101 ..... 1010111 @r_vm
// vfsgnjn_vv      001001 . ..... ..... 001 ..... 1010111 @r_vm
// vfsgnjn_vf      001001 . ..... ..... 101 ..... 1010111 @r_vm
// vfsgnjx_vv      001010 . ..... ..... 001 ..... 1010111 @r_vm
// vfsgnjx_vf      001010 . ..... ..... 101 ..... 1010111 @r_vm
// vfslide1up_vf   001110 . ..... ..... 101 ..... 1010111 @r_vm
// vfslide1down_vf 001111 . ..... ..... 101 ..... 1010111 @r_vm
// vmfeq_vv        011000 . ..... ..... 001 ..... 1010111 @r_vm
// vmfeq_vf        011000 . ..... ..... 101 ..... 1010111 @r_vm
// vmfne_vv        011100 . ..... ..... 001 ..... 1010111 @r_vm
// vmfne_vf        011100 . ..... ..... 101 ..... 1010111 @r_vm
// vmflt_vv        011011 . ..... ..... 001 ..... 1010111 @r_vm
// vmflt_vf        011011 . ..... ..... 101 ..... 1010111 @r_vm
// vmfle_vv        011001 . ..... ..... 001 ..... 1010111 @r_vm
// vmfle_vf        011001 . ..... ..... 101 ..... 1010111 @r_vm
// vmfgt_vf        011101 . ..... ..... 101 ..... 1010111 @r_vm
// vmfge_vf        011111 . ..... ..... 101 ..... 1010111 @r_vm
// vfclass_v       010011 . ..... 10000 001 ..... 1010111 @r2_vm
// vfmerge_vfm     010111 0 ..... ..... 101 ..... 1010111 @r_vm_0
// vfmv_v_f        010111 1 00000 ..... 101 ..... 1010111 @r2

// vfcvt_xu_f_v       010010 . ..... 00000 001 ..... 1010111 @r2_vm
// vfcvt_x_f_v        010010 . ..... 00001 001 ..... 1010111 @r2_vm
// vfcvt_f_xu_v       010010 . ..... 00010 001 ..... 1010111 @r2_vm
// vfcvt_f_x_v        010010 . ..... 00011 001 ..... 1010111 @r2_vm
// vfcvt_rtz_xu_f_v   010010 . ..... 00110 001 ..... 1010111 @r2_vm
// vfcvt_rtz_x_f_v    010010 . ..... 00111 001 ..... 1010111 @r2_vm

// vfwcvt_xu_f_v      010010 . ..... 01000 001 ..... 1010111 @r2_vm
// vfwcvt_x_f_v       010010 . ..... 01001 001 ..... 1010111 @r2_vm
// vfwcvt_f_xu_v      010010 . ..... 01010 001 ..... 1010111 @r2_vm
// vfwcvt_f_x_v       010010 . ..... 01011 001 ..... 1010111 @r2_vm
// vfwcvt_f_f_v       010010 . ..... 01100 001 ..... 1010111 @r2_vm
// vfwcvt_rtz_xu_f_v  010010 . ..... 01110 001 ..... 1010111 @r2_vm
// vfwcvt_rtz_x_f_v   010010 . ..... 01111 001 ..... 1010111 @r2_vm

// vfncvt_xu_f_w      010010 . ..... 10000 001 ..... 1010111 @r2_vm
// vfncvt_x_f_w       010010 . ..... 10001 001 ..... 1010111 @r2_vm
// vfncvt_f_xu_w      010010 . ..... 10010 001 ..... 1010111 @r2_vm
// vfncvt_f_x_w       010010 . ..... 10011 001 ..... 1010111 @r2_vm
// vfncvt_f_f_w       010010 . ..... 10100 001 ..... 1010111 @r2_vm
// vfncvt_rod_f_f_w   010010 . ..... 10101 001 ..... 1010111 @r2_vm
// vfncvt_rtz_xu_f_w  010010 . ..... 10110 001 ..... 1010111 @r2_vm
// vfncvt_rtz_x_f_w   010010 . ..... 10111 001 ..... 1010111 @r2_vm

// vredsum_vs      000000 . ..... ..... 010 ..... 1010111 @r_vm
// vredand_vs      000001 . ..... ..... 010 ..... 1010111 @r_vm
// vredor_vs       000010 . ..... ..... 010 ..... 1010111 @r_vm
// vredxor_vs      000011 . ..... ..... 010 ..... 1010111 @r_vm
// vredminu_vs     000100 . ..... ..... 010 ..... 1010111 @r_vm
// vredmin_vs      000101 . ..... ..... 010 ..... 1010111 @r_vm
// vredmaxu_vs     000110 . ..... ..... 010 ..... 1010111 @r_vm
// vredmax_vs      000111 . ..... ..... 010 ..... 1010111 @r_vm
// vwredsumu_vs    110000 . ..... ..... 000 ..... 1010111 @r_vm
// vwredsum_vs     110001 . ..... ..... 000 ..... 1010111 @r_vm
// # Vector ordered and unordered reduction sum
// vfredsum_vs     000001 . ..... ..... 001 ..... 1010111 @r_vm
// vfredosum_vs    000011 . ..... ..... 001 ..... 1010111 @r_vm
// vfredmin_vs     000101 . ..... ..... 001 ..... 1010111 @r_vm
// vfredmax_vs     000111 . ..... ..... 001 ..... 1010111 @r_vm
// # Vector widening ordered and unordered float reduction sum
// vfwredsum_vs    110001 . ..... ..... 001 ..... 1010111 @r_vm
// vfwredosum_vs   110011 . ..... ..... 001 ..... 1010111 @r_vm
// vmand_mm        011001 - ..... ..... 010 ..... 1010111 @r
// vmnand_mm       011101 - ..... ..... 010 ..... 1010111 @r
// vmandnot_mm     011000 - ..... ..... 010 ..... 1010111 @r
// vmxor_mm        011011 - ..... ..... 010 ..... 1010111 @r
// vmor_mm         011010 - ..... ..... 010 ..... 1010111 @r
// vmnor_mm        011110 - ..... ..... 010 ..... 1010111 @r
// vmornot_mm      011100 - ..... ..... 010 ..... 1010111 @r
// vmxnor_mm       011111 - ..... ..... 010 ..... 1010111 @r
// vpopc_m         010000 . ..... 10000 010 ..... 1010111 @r2_vm
// vfirst_m        010000 . ..... 10001 010 ..... 1010111 @r2_vm
// vmsbf_m         010100 . ..... 00001 010 ..... 1010111 @r2_vm
// vmsif_m         010100 . ..... 00011 010 ..... 1010111 @r2_vm
// vmsof_m         010100 . ..... 00010 010 ..... 1010111 @r2_vm
// viota_m         010100 . ..... 10000 010 ..... 1010111 @r2_vm
// vid_v           010100 . 00000 10001 010 ..... 1010111 @r1_vm
// vmv_x_s         010000 1 ..... 00000 010 ..... 1010111 @r2rd
// vmv_s_x         010000 1 00000 ..... 110 ..... 1010111 @r2
// vfmv_f_s        010000 1 ..... 00000 001 ..... 1010111 @r2rd
// vfmv_s_f        010000 1 00000 ..... 101 ..... 1010111 @r2
// vslideup_vx     001110 . ..... ..... 100 ..... 1010111 @r_vm
// vslideup_vi     001110 . ..... ..... 011 ..... 1010111 @r_vm
// vslide1up_vx    001110 . ..... ..... 110 ..... 1010111 @r_vm
// vslidedown_vx   001111 . ..... ..... 100 ..... 1010111 @r_vm
// vslidedown_vi   001111 . ..... ..... 011 ..... 1010111 @r_vm
// vslide1down_vx  001111 . ..... ..... 110 ..... 1010111 @r_vm
// vrgather_vv     001100 . ..... ..... 000 ..... 1010111 @r_vm
// vrgatherei16_vv 001110 . ..... ..... 000 ..... 1010111 @r_vm
// vrgather_vx     001100 . ..... ..... 100 ..... 1010111 @r_vm
// vrgather_vi     001100 . ..... ..... 011 ..... 1010111 @r_vm
// vcompress_vm    010111 - ..... ..... 010 ..... 1010111 @r
// vmv1r_v         100111 1 ..... 00000 011 ..... 1010111 @r2rd
// vmv2r_v         100111 1 ..... 00001 011 ..... 1010111 @r2rd
// vmv4r_v         100111 1 ..... 00011 011 ..... 1010111 @r2rd
// vmv8r_v         100111 1 ..... 00111 011 ..... 1010111 @r2rd

// # Vector Integer Extension
// vzext_vf2       010010 . ..... 00110 010 ..... 1010111 @r2_vm
// vzext_vf4       010010 . ..... 00100 010 ..... 1010111 @r2_vm
// vzext_vf8       010010 . ..... 00010 010 ..... 1010111 @r2_vm
// vsext_vf2       010010 . ..... 00111 010 ..... 1010111 @r2_vm
// vsext_vf4       010010 . ..... 00101 010 ..... 1010111 @r2_vm
// vsext_vf8       010010 . ..... 00011 010 ..... 1010111 @r2_vm

// vsetvli         0 ........... ..... 111 ..... 1010111  @r2_zimm11
// vsetivli        11 .......... ..... 111 ..... 1010111  @r2_zimm10
// vsetvl          1000000 ..... ..... 111 ..... 1010111  @r

fn vm(instruction_bits: u32) -> bool {
    instruction_bits & 0x2000000 != 0
}

pub fn factory<R: Register>(instruction_bits: u32, _: u32) -> Option<Instruction> {
    let bit_length = R::BITS;
    if bit_length != 32 && bit_length != 64 {
        return None;
    }
    let inst = match opcode(instruction_bits) {
        0b0000111 => {
            #[rustfmt::skip]
            let inst_opt = match instruction_bits {
                x if x & 0b11111111111100000111000001111111 == 0b00000010101100000000000000000111 => Some(insts::OP_VLM_V),
                x if x & 0b00011101111100000111000001111111 == 0b00000000000000000000000000000111 => Some(insts::OP_VLE8_V),
                x if x & 0b00011101111100000111000001111111 == 0b00000000000000000101000000000111 => Some(insts::OP_VLE16_V),
                x if x & 0b00011101111100000111000001111111 == 0b00000000000000000110000000000111 => Some(insts::OP_VLE32_V),
                x if x & 0b00011101111100000111000001111111 == 0b00000000000000000111000000000111 => Some(insts::OP_VLE64_V),
                x if x & 0b00011101111100000111000001111111 == 0b00010000000000000000000000000111 => Some(insts::OP_VLE128_V),
                x if x & 0b00011101111100000111000001111111 == 0b00010000000000000101000000000111 => Some(insts::OP_VLE256_V),
                x if x & 0b00011101111100000111000001111111 == 0b00010000000000000110000000000111 => Some(insts::OP_VLE512_V),
                x if x & 0b00011101111100000111000001111111 == 0b00010000000000000111000000000111 => Some(insts::OP_VLE1024_V),
                x if x & 0b00011100000000000111000001111111 == 0b00001000000000000000000000000111 => Some(insts::OP_VLSE8_V),
                x if x & 0b00011100000000000111000001111111 == 0b00001000000000000101000000000111 => Some(insts::OP_VLSE16_V),
                x if x & 0b00011100000000000111000001111111 == 0b00001000000000000110000000000111 => Some(insts::OP_VLSE32_V),
                x if x & 0b00011100000000000111000001111111 == 0b00001000000000000111000000000111 => Some(insts::OP_VLSE64_V),
                x if x & 0b00011100000000000111000001111111 == 0b00011000000000000000000000000111 => Some(insts::OP_VLSE128_V),
                x if x & 0b00011100000000000111000001111111 == 0b00011000000000000101000000000111 => Some(insts::OP_VLSE256_V),
                x if x & 0b00011100000000000111000001111111 == 0b00011000000000000110000000000111 => Some(insts::OP_VLSE512_V),
                x if x & 0b00011100000000000111000001111111 == 0b00011000000000000111000000000111 => Some(insts::OP_VLSE1024_V),
                x if x & 0b00011100000000000111000001111111 == 0b00000100000000000000000000000111 => Some(insts::OP_VLUXEI8_V),
                x if x & 0b00011100000000000111000001111111 == 0b00000100000000000101000000000111 => Some(insts::OP_VLUXEI16_V),
                x if x & 0b00011100000000000111000001111111 == 0b00000100000000000110000000000111 => Some(insts::OP_VLUXEI32_V),
                x if x & 0b00011100000000000111000001111111 == 0b00000100000000000111000000000111 => Some(insts::OP_VLUXEI64_V),
                x if x & 0b00011100000000000111000001111111 == 0b00010100000000000000000000000111 => Some(insts::OP_VLUXEI128_V),
                x if x & 0b00011100000000000111000001111111 == 0b00010100000000000101000000000111 => Some(insts::OP_VLUXEI256_V),
                x if x & 0b00011100000000000111000001111111 == 0b00010100000000000110000000000111 => Some(insts::OP_VLUXEI512_V),
                x if x & 0b00011100000000000111000001111111 == 0b00010100000000000111000000000111 => Some(insts::OP_VLUXEI1024_V),
                x if x & 0b00011100000000000111000001111111 == 0b00001100000000000000000000000111 => Some(insts::OP_VLOXEI8_V),
                x if x & 0b00011100000000000111000001111111 == 0b00001100000000000101000000000111 => Some(insts::OP_VLOXEI16_V),
                x if x & 0b00011100000000000111000001111111 == 0b00001100000000000110000000000111 => Some(insts::OP_VLOXEI32_V),
                x if x & 0b00011100000000000111000001111111 == 0b00001100000000000111000000000111 => Some(insts::OP_VLOXEI64_V),
                x if x & 0b00011100000000000111000001111111 == 0b00011100000000000000000000000111 => Some(insts::OP_VLOXEI128_V),
                x if x & 0b00011100000000000111000001111111 == 0b00011100000000000101000000000111 => Some(insts::OP_VLOXEI256_V),
                x if x & 0b00011100000000000111000001111111 == 0b00011100000000000110000000000111 => Some(insts::OP_VLOXEI512_V),
                x if x & 0b00011100000000000111000001111111 == 0b00011100000000000111000000000111 => Some(insts::OP_VLOXEI1024_V),
                x if x & 0b11111111111100000111000001111111 == 0b00000010100000000000000000000111 => Some(insts::OP_VL1RE8_V),
                x if x & 0b11111111111100000111000001111111 == 0b00000010100000000101000000000111 => Some(insts::OP_VL1RE16_V),
                x if x & 0b11111111111100000111000001111111 == 0b00000010100000000110000000000111 => Some(insts::OP_VL1RE32_V),
                x if x & 0b11111111111100000111000001111111 == 0b00000010100000000111000000000111 => Some(insts::OP_VL1RE64_V),
                x if x & 0b11111111111100000111000001111111 == 0b00100010100000000000000000000111 => Some(insts::OP_VL2RE8_V),
                x if x & 0b11111111111100000111000001111111 == 0b00100010100000000101000000000111 => Some(insts::OP_VL2RE16_V),
                x if x & 0b11111111111100000111000001111111 == 0b00100010100000000110000000000111 => Some(insts::OP_VL2RE32_V),
                x if x & 0b11111111111100000111000001111111 == 0b00100010100000000111000000000111 => Some(insts::OP_VL2RE64_V),
                x if x & 0b11111111111100000111000001111111 == 0b01100010100000000000000000000111 => Some(insts::OP_VL4RE8_V),
                x if x & 0b11111111111100000111000001111111 == 0b01100010100000000101000000000111 => Some(insts::OP_VL4RE16_V),
                x if x & 0b11111111111100000111000001111111 == 0b01100010100000000110000000000111 => Some(insts::OP_VL4RE32_V),
                x if x & 0b11111111111100000111000001111111 == 0b01100010100000000111000000000111 => Some(insts::OP_VL4RE64_V),
                x if x & 0b11111111111100000111000001111111 == 0b_11100010100000000000000000000111 => Some(insts::OP_VL8RE8_V),
                x if x & 0b11111111111100000111000001111111 == 0b_11100010100000000101000000000111 => Some(insts::OP_VL8RE16_V),
                x if x & 0b11111111111100000111000001111111 == 0b_11100010100000000110000000000111 => Some(insts::OP_VL8RE32_V),
                x if x & 0b11111111111100000111000001111111 == 0b_11100010100000000111000000000111 => Some(insts::OP_VL8RE64_V),
                _ => None,
            };
            inst_opt.map(|inst| {
                VXtype::new(
                    inst,
                    rd(instruction_bits),
                    rs1(instruction_bits),
                    rs2(instruction_bits),
                    vm(instruction_bits),
                )
                .0
            })
        }
        0b0100111 => {
            #[rustfmt::skip]
            let inst_opt = match instruction_bits {
                x if x & 0b11111111111100000111000001111111 == 0b00000010101100000000000000100111 => Some(insts::OP_VSM_V),
                x if x & 0b00011101111100000111000001111111 == 0b00000000000000000000000000100111 => Some(insts::OP_VSE8_V),
                x if x & 0b00011101111100000111000001111111 == 0b00000000000000000101000000100111 => Some(insts::OP_VSE16_V),
                x if x & 0b00011101111100000111000001111111 == 0b00000000000000000110000000100111 => Some(insts::OP_VSE32_V),
                x if x & 0b00011101111100000111000001111111 == 0b00000000000000000111000000100111 => Some(insts::OP_VSE64_V),
                x if x & 0b00011101111100000111000001111111 == 0b00010000000000000000000000100111 => Some(insts::OP_VSE128_V),
                x if x & 0b00011101111100000111000001111111 == 0b00010000000000000101000000100111 => Some(insts::OP_VSE256_V),
                x if x & 0b00011101111100000111000001111111 == 0b00010000000000000110000000100111 => Some(insts::OP_VSE512_V),
                x if x & 0b00011101111100000111000001111111 == 0b00010000000000000111000000100111 => Some(insts::OP_VSE1024_V),
                x if x & 0b00011100000000000111000001111111 == 0b00001000000000000000000000100111 => Some(insts::OP_VSSE8_V),
                x if x & 0b00011100000000000111000001111111 == 0b00001000000000000101000000100111 => Some(insts::OP_VSSE16_V),
                x if x & 0b00011100000000000111000001111111 == 0b00001000000000000110000000100111 => Some(insts::OP_VSSE32_V),
                x if x & 0b00011100000000000111000001111111 == 0b00001000000000000111000000100111 => Some(insts::OP_VSSE64_V),
                x if x & 0b00011100000000000111000001111111 == 0b00011000000000000000000000100111 => Some(insts::OP_VSSE128_V),
                x if x & 0b00011100000000000111000001111111 == 0b00011000000000000101000000100111 => Some(insts::OP_VSSE256_V),
                x if x & 0b00011100000000000111000001111111 == 0b00011000000000000110000000100111 => Some(insts::OP_VSSE512_V),
                x if x & 0b00011100000000000111000001111111 == 0b00011000000000000111000000100111 => Some(insts::OP_VSSE1024_V),
                x if x & 0b00011100000000000111000001111111 == 0b00000100000000000000000000100111 => Some(insts::OP_VSUXEI8_V),
                x if x & 0b00011100000000000111000001111111 == 0b00000100000000000101000000100111 => Some(insts::OP_VSUXEI16_V),
                x if x & 0b00011100000000000111000001111111 == 0b00000100000000000110000000100111 => Some(insts::OP_VSUXEI32_V),
                x if x & 0b00011100000000000111000001111111 == 0b00000100000000000111000000100111 => Some(insts::OP_VSUXEI64_V),
                x if x & 0b00011100000000000111000001111111 == 0b00010100000000000000000000100111 => Some(insts::OP_VSUXEI128_V),
                x if x & 0b00011100000000000111000001111111 == 0b00010100000000000101000000100111 => Some(insts::OP_VSUXEI256_V),
                x if x & 0b00011100000000000111000001111111 == 0b00010100000000000110000000100111 => Some(insts::OP_VSUXEI512_V),
                x if x & 0b00011100000000000111000001111111 == 0b00010100000000000111000000100111 => Some(insts::OP_VSUXEI1024_V),
                x if x & 0b00011100000000000111000001111111 == 0b00001100000000000000000000100111 => Some(insts::OP_VSOXEI8_V),
                x if x & 0b00011100000000000111000001111111 == 0b00001100000000000101000000100111 => Some(insts::OP_VSOXEI16_V),
                x if x & 0b00011100000000000111000001111111 == 0b00001100000000000110000000100111 => Some(insts::OP_VSOXEI32_V),
                x if x & 0b00011100000000000111000001111111 == 0b00001100000000000111000000100111 => Some(insts::OP_VSOXEI64_V),
                x if x & 0b00011100000000000111000001111111 == 0b00011100000000000000000000100111 => Some(insts::OP_VSOXEI128_V),
                x if x & 0b00011100000000000111000001111111 == 0b00011100000000000101000000100111 => Some(insts::OP_VSOXEI256_V),
                x if x & 0b00011100000000000111000001111111 == 0b00011100000000000110000000100111 => Some(insts::OP_VSOXEI512_V),
                x if x & 0b00011100000000000111000001111111 == 0b00011100000000000111000000100111 => Some(insts::OP_VSOXEI1024_V),
                x if x & 0b11111111111100000111000001111111 == 0b00000010100000000000000000100111 => Some(insts::OP_VS1R_V),
                x if x & 0b11111111111100000111000001111111 == 0b00100010100000000000000000100111 => Some(insts::OP_VS2R_V),
                x if x & 0b11111111111100000111000001111111 == 0b01100010100000000000000000100111 => Some(insts::OP_VS4R_V),
                x if x & 0b11111111111100000111000001111111 == 0b11100010100000000000000000100111 => Some(insts::OP_VS8R_V),
                _ => None,
            };
            inst_opt.map(|inst| {
                VXtype::new(
                    inst,
                    rd(instruction_bits),
                    rs1(instruction_bits),
                    rs2(instruction_bits),
                    vm(instruction_bits),
                )
                .0
            })
        }
        0b1010111 => match funct3(instruction_bits) {
            0b000 => {
                #[rustfmt::skip]
                let inst_opt = match instruction_bits {
                    x if x & 0b11111100000000000111000001111111 == 0b00000000000000000000000001010111 => Some(insts::OP_VADD_VV),
                    x if x & 0b11111100000000000111000001111111 == 0b00001000000000000000000001010111 => Some(insts::OP_VSUB_VV),
                    x if x & 0b11111100000000000111000001111111 == 0b00010000000000000000000001010111 => Some(insts::OP_VMINU_VV),
                    x if x & 0b11111100000000000111000001111111 == 0b00010100000000000000000001010111 => Some(insts::OP_VMIN_VV),
                    x if x & 0b11111100000000000111000001111111 == 0b00011000000000000000000001010111 => Some(insts::OP_VMAXU_VV),
                    x if x & 0b11111100000000000111000001111111 == 0b00011100000000000000000001010111 => Some(insts::OP_VMAX_VV),
                    x if x & 0b11111100000000000111000001111111 == 0b01100000000000000000000001010111 => Some(insts::OP_VMSEQ_VV),
                    x if x & 0b11111100000000000111000001111111 == 0b01100100000000000000000001010111 => Some(insts::OP_VMSNE_VV),
                    x if x & 0b11111100000000000111000001111111 == 0b01101000000000000000000001010111 => Some(insts::OP_VMSLTU_VV),
                    x if x & 0b11111100000000000111000001111111 == 0b01101100000000000000000001010111 => Some(insts::OP_VMSLT_VV),
                    x if x & 0b11111100000000000111000001111111 == 0b01110000000000000000000001010111 => Some(insts::OP_VMSLEU_VV),
                    x if x & 0b11111100000000000111000001111111 == 0b01110100000000000000000001010111 => Some(insts::OP_VMSLE_VV),
                    x if x & 0b11111100000000000111000001111111 == 0b10010100000000000000000001010111 => Some(insts::OP_VSLL_VV),
                    x if x & 0b11111100000000000111000001111111 == 0b10100000000000000000000001010111 => Some(insts::OP_VSRL_VV),
                    x if x & 0b11111100000000000111000001111111 == 0b10100100000000000000000001010111 => Some(insts::OP_VSRA_VV),
                    x if x & 0b11111100000000000111000001111111 == 0b00100100000000000000000001010111 => Some(insts::OP_VAND_VV),
                    x if x & 0b11111100000000000111000001111111 == 0b00101000000000000000000001010111 => Some(insts::OP_VOR_VV),
                    x if x & 0b11111100000000000111000001111111 == 0b00101100000000000000000001010111 => Some(insts::OP_VXOR_VV),
                    x if x & 0b11111100000000000111000001111111 == 0b10000000000000000000000001010111 => Some(insts::OP_VSADDU_VV),
                    x if x & 0b11111100000000000111000001111111 == 0b10000100000000000000000001010111 => Some(insts::OP_VSADD_VV),
                    x if x & 0b11111100000000000111000001111111 == 0b10001000000000000000000001010111 => Some(insts::OP_VSSUBU_VV),
                    x if x & 0b11111100000000000111000001111111 == 0b10001100000000000000000001010111 => Some(insts::OP_VSSUB_VV),
                    x if x & 0b11111111111100000111000001111111 == 0b01011110000000000000000001010111 => Some(insts::OP_VMV_V_V),
                    x if x & 0b11111100000000000111000001111111 == 0b10110000000000000000000001010111 => Some(insts::OP_VNSRL_WV),
                    x if x & 0b11111100000000000111000001111111 == 0b10110100000000000000000001010111 => Some(insts::OP_VNSRA_WV),
                    x if x & 0b11111110000000000111000001111111 == 0b01000110000000000000000001010111 => Some(insts::OP_VMADC_VV),
                    x if x & 0b11111110000000000111000001111111 == 0b01001110000000000000000001010111 => Some(insts::OP_VMSBC_VV),
                    x if x & 0b11111110000000000111000001111111 == 0b01000000000000000000000001010111 => Some(insts::OP_VADC_VVM),
                    x if x & 0b11111110000000000111000001111111 == 0b01001000000000000000000001010111 => Some(insts::OP_VSBC_VVM),
                    x if x & 0b11111100000000000111000001111111 == 0b01000100000000000000000001010111 => Some(insts::OP_VMADC_VVM),
                    x if x & 0b11111100000000000111000001111111 == 0b01001100000000000000000001010111 => Some(insts::OP_VMSBC_VVM),
                    x if x & 0b11111100000000000111000001111111 == 0b10101000000000000000000001010111 => Some(insts::OP_VSSRL_VV),
                    x if x & 0b11111100000000000111000001111111 == 0b10101100000000000000000001010111 => Some(insts::OP_VSSRA_VV),
                    x if x & 0b11111100000000000111000001111111 == 0b10011100000000000000000001010111 => Some(insts::OP_VSMUL_VV),
                    x if x & 0b11111110000000000111000001111111 == 0b01011100000000000000000001010111 => Some(insts::OP_VMERGE_VVM),
                    x if x & 0b11111100000000000111000001111111 == 0b10111000000000000000000001010111 => Some(insts::OP_VNCLIPU_WV),
                    x if x & 0b11111100000000000111000001111111 == 0b10111100000000000000000001010111 => Some(insts::OP_VNCLIP_WV),
                    x if x & 0b11111100000000000111000001111111 == 0b11000000000000000000000001010111 => Some(insts::OP_VWREDSUMU_VS),
                    x if x & 0b11111100000000000111000001111111 == 0b11000100000000000000000001010111 => Some(insts::OP_VWREDSUM_VS),
                    x if x & 0b11111100000000000111000001111111 == 0b00110000000000000000000001010111 => Some(insts::OP_VRGATHER_VV),
                    x if x & 0b11111100000000000111000001111111 == 0b00111000000000000000000001010111 => Some(insts::OP_VRGATHEREI16_VV),
                    _ => None,
                };
                inst_opt.map(|inst| {
                    VVtype::new(
                        inst,
                        rd(instruction_bits),
                        rs1(instruction_bits),
                        rs2(instruction_bits),
                        vm(instruction_bits),
                    )
                    .0
                })
            }
            0b010 => {
                #[rustfmt::skip]
                let inst_opt = match instruction_bits {
                    x if x & 0b11111100000000000111000001111111 == 0b10000000000000000010000001010111 => Some(insts::OP_VDIVU_VV),
                    x if x & 0b11111100000000000111000001111111 == 0b10001000000000000010000001010111 => Some(insts::OP_VREMU_VV),
                    x if x & 0b11111100000000000111000001111111 == 0b10000100000000000010000001010111 => Some(insts::OP_VDIV_VV),
                    x if x & 0b11111100000000000111000001111111 == 0b10001100000000000010000001010111 => Some(insts::OP_VREM_VV),
                    x if x & 0b11111100000000000111000001111111 == 0b10010100000000000010000001010111 => Some(insts::OP_VMUL_VV),
                    x if x & 0b11111100000000000111000001111111 == 0b10011100000000000010000001010111 => Some(insts::OP_VMULH_VV),
                    x if x & 0b11111100000000000111000001111111 == 0b10010000000000000010000001010111 => Some(insts::OP_VMULHU_VV),
                    x if x & 0b11111100000000000111000001111111 == 0b10011000000000000010000001010111 => Some(insts::OP_VMULHSU_VV),
                    x if x & 0b11111100000000000111000001111111 == 0b00100100000000000010000001010111 => Some(insts::OP_VAADD_VV),
                    x if x & 0b11111100000000000111000001111111 == 0b00100000000000000010000001010111 => Some(insts::OP_VAADDU_VV),
                    x if x & 0b11111100000000000111000001111111 == 0b00101100000000000010000001010111 => Some(insts::OP_VASUB_VV),
                    x if x & 0b11111100000000000111000001111111 == 0b00101000000000000010000001010111 => Some(insts::OP_VASUBU_VV),
                    x if x & 0b11111100000011111111000001111111 == 0b01000000000010001010000001010111 => Some(insts::OP_VFIRST_M),
                    x if x & 0b11111100000011111111000001111111 == 0b01000000000010000010000001010111 => Some(insts::OP_VCPOP_M),
                    x if x & 0b11111100000000000111000001111111 == 0b11000000000000000010000001010111 => Some(insts::OP_VWADDU_VV),
                    x if x & 0b11111100000000000111000001111111 == 0b11000100000000000010000001010111 => Some(insts::OP_VWADD_VV),
                    x if x & 0b11111100000000000111000001111111 == 0b11001000000000000010000001010111 => Some(insts::OP_VWSUBU_VV),
                    x if x & 0b11111100000000000111000001111111 == 0b11001100000000000010000001010111 => Some(insts::OP_VWSUB_VV),
                    x if x & 0b11111100000000000111000001111111 == 0b11010000000000000010000001010111 => Some(insts::OP_VWADDU_WV),
                    x if x & 0b11111100000000000111000001111111 == 0b11010100000000000010000001010111 => Some(insts::OP_VWADD_WV),
                    x if x & 0b11111100000000000111000001111111 == 0b11011000000000000010000001010111 => Some(insts::OP_VWSUBU_WV),
                    x if x & 0b11111100000000000111000001111111 == 0b11011100000000000010000001010111 => Some(insts::OP_VWSUB_WV),
                    x if x & 0b11111100000000000111000001111111 == 0b11100000000000000010000001010111 => Some(insts::OP_VWMULU_VV),
                    x if x & 0b11111100000000000111000001111111 == 0b11101000000000000010000001010111 => Some(insts::OP_VWMULSU_VV),
                    x if x & 0b11111100000000000111000001111111 == 0b11101100000000000010000001010111 => Some(insts::OP_VWMUL_VV),
                    x if x & 0b11111100000011111111000001111111 == 0b01001000000000110010000001010111 => Some(insts::OP_VZEXT_VF2),
                    x if x & 0b11111100000011111111000001111111 == 0b01001000000000100010000001010111 => Some(insts::OP_VZEXT_VF4),
                    x if x & 0b11111100000011111111000001111111 == 0b01001000000000010010000001010111 => Some(insts::OP_VZEXT_VF8),
                    x if x & 0b11111100000011111111000001111111 == 0b01001000000000111010000001010111 => Some(insts::OP_VSEXT_VF2),
                    x if x & 0b11111100000011111111000001111111 == 0b01001000000000101010000001010111 => Some(insts::OP_VSEXT_VF4),
                    x if x & 0b11111100000011111111000001111111 == 0b01001000000000011010000001010111 => Some(insts::OP_VSEXT_VF8),
                    x if x & 0b11111100000000000111000001111111 == 0b01100000000000000010000001010111 => Some(insts::OP_VMANDNOT_MM),
                    x if x & 0b11111100000000000111000001111111 == 0b01100100000000000010000001010111 => Some(insts::OP_VMAND_MM),
                    x if x & 0b11111100000000000111000001111111 == 0b01101000000000000010000001010111 => Some(insts::OP_VMOR_MM),
                    x if x & 0b11111100000000000111000001111111 == 0b01101100000000000010000001010111 => Some(insts::OP_VMXOR_MM),
                    x if x & 0b11111100000000000111000001111111 == 0b01110000000000000010000001010111 => Some(insts::OP_VMORNOT_MM),
                    x if x & 0b11111100000000000111000001111111 == 0b01110100000000000010000001010111 => Some(insts::OP_VMNAND_MM),
                    x if x & 0b11111100000000000111000001111111 == 0b01111000000000000010000001010111 => Some(insts::OP_VMNOR_MM),
                    x if x & 0b11111100000000000111000001111111 == 0b01111100000000000010000001010111 => Some(insts::OP_VMXNOR_MM),
                    x if x & 0b11111100000000000111000001111111 == 0b10110100000000000010000001010111 => Some(insts::OP_VMACC_VV),
                    x if x & 0b11111100000000000111000001111111 == 0b10111100000000000010000001010111 => Some(insts::OP_VNMSAC_VV),
                    x if x & 0b11111100000000000111000001111111 == 0b10100100000000000010000001010111 => Some(insts::OP_VMADD_VV),
                    x if x & 0b11111100000000000111000001111111 == 0b10101100000000000010000001010111 => Some(insts::OP_VNMSUB_VV),
                    x if x & 0b11111100000000000111000001111111 == 0b11110000000000000010000001010111 => Some(insts::OP_VWMACCU_VV),
                    x if x & 0b11111100000000000111000001111111 == 0b11110100000000000010000001010111 => Some(insts::OP_VWMACC_VV),
                    x if x & 0b11111100000000000111000001111111 == 0b11111100000000000010000001010111 => Some(insts::OP_VWMACCSU_VV),
                    x if x & 0b11111100000000000111000001111111 == 0b00000000000000000010000001010111 => Some(insts::OP_VREDSUM_VS),
                    x if x & 0b11111100000000000111000001111111 == 0b00000100000000000010000001010111 => Some(insts::OP_VREDAND_VS),
                    x if x & 0b11111100000000000111000001111111 == 0b00001000000000000010000001010111 => Some(insts::OP_VREDOR_VS),
                    x if x & 0b11111100000000000111000001111111 == 0b00001100000000000010000001010111 => Some(insts::OP_VREDXOR_VS),
                    x if x & 0b11111100000000000111000001111111 == 0b00010000000000000010000001010111 => Some(insts::OP_VREDMINU_VS),
                    x if x & 0b11111100000000000111000001111111 == 0b00010100000000000010000001010111 => Some(insts::OP_VREDMIN_VS),
                    x if x & 0b11111100000000000111000001111111 == 0b00011000000000000010000001010111 => Some(insts::OP_VREDMAXU_VS),
                    x if x & 0b11111100000000000111000001111111 == 0b00011100000000000010000001010111 => Some(insts::OP_VREDMAX_VS),
                    x if x & 0b11111100000011111111000001111111 == 0b01010000000000001010000001010111 => Some(insts::OP_VMSBF_M),
                    x if x & 0b11111100000011111111000001111111 == 0b01010000000000011010000001010111 => Some(insts::OP_VMSIF_M),
                    x if x & 0b11111100000011111111000001111111 == 0b01010000000000010010000001010111 => Some(insts::OP_VMSOF_M),
                    x if x & 0b11111100000011111111000001111111 == 0b01010000000010000010000001010111 => Some(insts::OP_VIOTA_M),
                    x if x & 0b11111101111111111111000001111111 == 0b01010000000010001010000001010111 => Some(insts::OP_VID_V),
                    x if x & 0b11111110000011111111000001111111 == 0b01000010000000000010000001010111 => Some(insts::OP_VMV_X_S),
                    x if x & 0b11111100000000000111000001111111 == 0b01011100000000000010000001010111 => Some(insts::OP_VCOMPRESS_VM),
                    _ => None,
                };
                inst_opt.map(|inst| {
                    VVtype::new(
                        inst,
                        rd(instruction_bits),
                        rs1(instruction_bits),
                        rs2(instruction_bits),
                        vm(instruction_bits),
                    )
                    .0
                })
            }
            0b011 => {
                #[rustfmt::skip]
                let inst_opt = match instruction_bits {
                    x if x & 0b11111100000000000111000001111111 == 0b00000000000000000011000001010111 => Some(insts::OP_VADD_VI),
                    x if x & 0b11111100000000000111000001111111 == 0b00001100000000000011000001010111 => Some(insts::OP_VRSUB_VI),
                    x if x & 0b11111100000000000111000001111111 == 0b01100000000000000011000001010111 => Some(insts::OP_VMSEQ_VI),
                    x if x & 0b11111100000000000111000001111111 == 0b01100100000000000011000001010111 => Some(insts::OP_VMSNE_VI),
                    x if x & 0b11111100000000000111000001111111 == 0b01110000000000000011000001010111 => Some(insts::OP_VMSLEU_VI),
                    x if x & 0b11111100000000000111000001111111 == 0b01110100000000000011000001010111 => Some(insts::OP_VMSLE_VI),
                    x if x & 0b11111100000000000111000001111111 == 0b01111000000000000011000001010111 => Some(insts::OP_VMSGTU_VI),
                    x if x & 0b11111100000000000111000001111111 == 0b01111100000000000011000001010111 => Some(insts::OP_VMSGT_VI),
                    x if x & 0b11111100000000000111000001111111 == 0b10010100000000000011000001010111 => Some(insts::OP_VSLL_VI),
                    x if x & 0b11111100000000000111000001111111 == 0b10100000000000000011000001010111 => Some(insts::OP_VSRL_VI),
                    x if x & 0b11111100000000000111000001111111 == 0b10100100000000000011000001010111 => Some(insts::OP_VSRA_VI),
                    x if x & 0b11111100000000000111000001111111 == 0b00100100000000000011000001010111 => Some(insts::OP_VAND_VI),
                    x if x & 0b11111100000000000111000001111111 == 0b00101000000000000011000001010111 => Some(insts::OP_VOR_VI),
                    x if x & 0b11111100000000000111000001111111 == 0b00101100000000000011000001010111 => Some(insts::OP_VXOR_VI),
                    x if x & 0b11111110000011111111000001111111 == 0b10011110000000000011000001010111 => Some(insts::OP_VMV1R_V),
                    x if x & 0b11111110000011111111000001111111 == 0b10011110000000001011000001010111 => Some(insts::OP_VMV2R_V),
                    x if x & 0b11111110000011111111000001111111 == 0b10011110000000011011000001010111 => Some(insts::OP_VMV4R_V),
                    x if x & 0b11111110000011111111000001111111 == 0b10011110000000111011000001010111 => Some(insts::OP_VMV8R_V),
                    x if x & 0b11111100000000000111000001111111 == 0b10000000000000000011000001010111 => Some(insts::OP_VSADDU_VI),
                    x if x & 0b11111100000000000111000001111111 == 0b10000100000000000011000001010111 => Some(insts::OP_VSADD_VI),
                    x if x & 0b11111111111100000111000001111111 == 0b01011110000000000011000001010111 => Some(insts::OP_VMV_V_I),
                    x if x & 0b11111100000000000111000001111111 == 0b10110000000000000011000001010111 => Some(insts::OP_VNSRL_WI),
                    x if x & 0b11111100000000000111000001111111 == 0b10110100000000000011000001010111 => Some(insts::OP_VNSRA_WI),
                    x if x & 0b11111110000000000111000001111111 == 0b01000110000000000011000001010111 => Some(insts::OP_VMADC_VI),
                    x if x & 0b11111110000000000111000001111111 == 0b01000000000000000011000001010111 => Some(insts::OP_VADC_VIM),
                    x if x & 0b11111100000000000111000001111111 == 0b01000100000000000011000001010111 => Some(insts::OP_VMADC_VIM),
                    x if x & 0b11111100000000000111000001111111 == 0b10101000000000000011000001010111 => Some(insts::OP_VSSRL_VI),
                    x if x & 0b11111100000000000111000001111111 == 0b10101100000000000011000001010111 => Some(insts::OP_VSSRA_VI),
                    x if x & 0b11111110000000000111000001111111 == 0b01011100000000000011000001010111 => Some(insts::OP_VMERGE_VIM),
                    x if x & 0b11111100000000000111000001111111 == 0b10111000000000000011000001010111 => Some(insts::OP_VNCLIPU_WI),
                    x if x & 0b11111100000000000111000001111111 == 0b10111100000000000011000001010111 => Some(insts::OP_VNCLIP_WI),
                    x if x & 0b11111100000000000111000001111111 == 0b00111000000000000011000001010111 => Some(insts::OP_VSLIDEUP_VI),
                    x if x & 0b11111100000000000111000001111111 == 0b00111100000000000011000001010111 => Some(insts::OP_VSLIDEDOWN_VI),
                    x if x & 0b11111100000000000111000001111111 == 0b00110000000000000011000001010111 => Some(insts::OP_VRGATHER_VI),
                    _ => None,
                };
                inst_opt.map(|inst| {
                    VItype::new(
                        inst,
                        rd(instruction_bits),
                        rs2(instruction_bits),
                        utils::x(instruction_bits, 15, 5, 0),
                        vm(instruction_bits),
                    )
                    .0
                })
            }
            0b100 => {
                #[rustfmt::skip]
                let inst_opt = match instruction_bits {
                    x if x & 0b11111100000000000111000001111111 == 0b00000000000000000100000001010111 => Some(insts::OP_VADD_VX),
                    x if x & 0b11111100000000000111000001111111 == 0b00001000000000000100000001010111 => Some(insts::OP_VSUB_VX),
                    x if x & 0b11111100000000000111000001111111 == 0b00001100000000000100000001010111 => Some(insts::OP_VRSUB_VX),
                    x if x & 0b11111100000000000111000001111111 == 0b00010000000000000100000001010111 => Some(insts::OP_VMINU_VX),
                    x if x & 0b11111100000000000111000001111111 == 0b00010100000000000100000001010111 => Some(insts::OP_VMIN_VX),
                    x if x & 0b11111100000000000111000001111111 == 0b00011000000000000100000001010111 => Some(insts::OP_VMAXU_VX),
                    x if x & 0b11111100000000000111000001111111 == 0b00011100000000000100000001010111 => Some(insts::OP_VMAX_VX),
                    x if x & 0b11111100000000000111000001111111 == 0b01100000000000000100000001010111 => Some(insts::OP_VMSEQ_VX),
                    x if x & 0b11111100000000000111000001111111 == 0b01100100000000000100000001010111 => Some(insts::OP_VMSNE_VX),
                    x if x & 0b11111100000000000111000001111111 == 0b01101000000000000100000001010111 => Some(insts::OP_VMSLTU_VX),
                    x if x & 0b11111100000000000111000001111111 == 0b01101100000000000100000001010111 => Some(insts::OP_VMSLT_VX),
                    x if x & 0b11111100000000000111000001111111 == 0b01110000000000000100000001010111 => Some(insts::OP_VMSLEU_VX),
                    x if x & 0b11111100000000000111000001111111 == 0b01110100000000000100000001010111 => Some(insts::OP_VMSLE_VX),
                    x if x & 0b11111100000000000111000001111111 == 0b01111000000000000100000001010111 => Some(insts::OP_VMSGTU_VX),
                    x if x & 0b11111100000000000111000001111111 == 0b01111100000000000100000001010111 => Some(insts::OP_VMSGT_VX),
                    x if x & 0b11111100000000000111000001111111 == 0b10010100000000000100000001010111 => Some(insts::OP_VSLL_VX),
                    x if x & 0b11111100000000000111000001111111 == 0b10100000000000000100000001010111 => Some(insts::OP_VSRL_VX),
                    x if x & 0b11111100000000000111000001111111 == 0b10100100000000000100000001010111 => Some(insts::OP_VSRA_VX),
                    x if x & 0b11111100000000000111000001111111 == 0b00100100000000000100000001010111 => Some(insts::OP_VAND_VX),
                    x if x & 0b11111100000000000111000001111111 == 0b00101000000000000100000001010111 => Some(insts::OP_VOR_VX),
                    x if x & 0b11111100000000000111000001111111 == 0b00101100000000000100000001010111 => Some(insts::OP_VXOR_VX),
                    x if x & 0b11111100000000000111000001111111 == 0b10000000000000000100000001010111 => Some(insts::OP_VSADDU_VX),
                    x if x & 0b11111100000000000111000001111111 == 0b10000100000000000100000001010111 => Some(insts::OP_VSADD_VX),
                    x if x & 0b11111100000000000111000001111111 == 0b10001000000000000100000001010111 => Some(insts::OP_VSSUBU_VX),
                    x if x & 0b11111100000000000111000001111111 == 0b10001100000000000100000001010111 => Some(insts::OP_VSSUB_VX),
                    x if x & 0b11111111111100000111000001111111 == 0b01011110000000000100000001010111 => Some(insts::OP_VMV_V_X),
                    x if x & 0b11111100000000000111000001111111 == 0b10110000000000000100000001010111 => Some(insts::OP_VNSRL_WX),
                    x if x & 0b11111100000000000111000001111111 == 0b10110100000000000100000001010111 => Some(insts::OP_VNSRA_WX),
                    x if x & 0b11111110000000000111000001111111 == 0b01000110000000000100000001010111 => Some(insts::OP_VMADC_VX),
                    x if x & 0b11111110000000000111000001111111 == 0b01001110000000000100000001010111 => Some(insts::OP_VMSBC_VX),
                    x if x & 0b11111110000000000111000001111111 == 0b01000000000000000100000001010111 => Some(insts::OP_VADC_VXM),
                    x if x & 0b11111110000000000111000001111111 == 0b01001000000000000100000001010111 => Some(insts::OP_VSBC_VXM),
                    x if x & 0b11111100000000000111000001111111 == 0b01000100000000000100000001010111 => Some(insts::OP_VMADC_VXM),
                    x if x & 0b11111100000000000111000001111111 == 0b01001100000000000100000001010111 => Some(insts::OP_VMSBC_VXM),
                    x if x & 0b11111100000000000111000001111111 == 0b10101000000000000100000001010111 => Some(insts::OP_VSSRL_VX),
                    x if x & 0b11111100000000000111000001111111 == 0b10101100000000000100000001010111 => Some(insts::OP_VSSRA_VX),
                    x if x & 0b11111100000000000111000001111111 == 0b10011100000000000100000001010111 => Some(insts::OP_VSMUL_VX),
                    x if x & 0b11111110000000000111000001111111 == 0b01011100000000000100000001010111 => Some(insts::OP_VMERGE_VXM),
                    x if x & 0b11111100000000000111000001111111 == 0b10111000000000000100000001010111 => Some(insts::OP_VNCLIPU_WX),
                    x if x & 0b11111100000000000111000001111111 == 0b10111100000000000100000001010111 => Some(insts::OP_VNCLIP_WX),
                    x if x & 0b11111100000000000111000001111111 == 0b00111100000000000100000001010111 => Some(insts::OP_VSLIDEDOWN_VX),
                    x if x & 0b11111100000000000111000001111111 == 0b00111000000000000100000001010111 => Some(insts::OP_VSLIDEUP_VX),
                    x if x & 0b11111100000000000111000001111111 == 0b00110000000000000100000001010111 => Some(insts::OP_VRGATHER_VX),
                    _ => None,
                };
                inst_opt.map(|inst| {
                    VXtype::new(
                        inst,
                        rd(instruction_bits),
                        rs1(instruction_bits),
                        rs2(instruction_bits),
                        vm(instruction_bits),
                    )
                    .0
                })
            }
            0b110 => {
                #[rustfmt::skip]
                let inst_opt = match instruction_bits {
                    x if x & 0b11111100000000000111000001111111 == 0b10000000000000000110000001010111 => Some(insts::OP_VDIVU_VX),
                    x if x & 0b11111100000000000111000001111111 == 0b10000100000000000110000001010111 => Some(insts::OP_VDIV_VX),
                    x if x & 0b11111100000000000111000001111111 == 0b10001000000000000110000001010111 => Some(insts::OP_VREMU_VX),
                    x if x & 0b11111100000000000111000001111111 == 0b10001100000000000110000001010111 => Some(insts::OP_VREM_VX),
                    x if x & 0b11111100000000000111000001111111 == 0b10010100000000000110000001010111 => Some(insts::OP_VMUL_VX),
                    x if x & 0b11111100000000000111000001111111 == 0b10011100000000000110000001010111 => Some(insts::OP_VMULH_VX),
                    x if x & 0b11111100000000000111000001111111 == 0b10010000000000000110000001010111 => Some(insts::OP_VMULHU_VX),
                    x if x & 0b11111100000000000111000001111111 == 0b10011000000000000110000001010111 => Some(insts::OP_VMULHSU_VX),
                    x if x & 0b11111100000000000111000001111111 == 0b11000000000000000110000001010111 => Some(insts::OP_VWADDU_VX),
                    x if x & 0b11111100000000000111000001111111 == 0b11000100000000000110000001010111 => Some(insts::OP_VWADD_VX),
                    x if x & 0b11111100000000000111000001111111 == 0b11001000000000000110000001010111 => Some(insts::OP_VWSUBU_VX),
                    x if x & 0b11111100000000000111000001111111 == 0b11100000000000000110000001010111 => Some(insts::OP_VWMULU_VX),
                    x if x & 0b11111100000000000111000001111111 == 0b11101000000000000110000001010111 => Some(insts::OP_VWMULSU_VX),
                    x if x & 0b11111100000000000111000001111111 == 0b11101100000000000110000001010111 => Some(insts::OP_VWMUL_VX),
                    x if x & 0b11111100000000000111000001111111 == 0b11001100000000000110000001010111 => Some(insts::OP_VWSUB_VX),
                    x if x & 0b11111100000000000111000001111111 == 0b11010000000000000110000001010111 => Some(insts::OP_VWADDU_WX),
                    x if x & 0b11111100000000000111000001111111 == 0b11010100000000000110000001010111 => Some(insts::OP_VWADD_WX),
                    x if x & 0b11111100000000000111000001111111 == 0b11011000000000000110000001010111 => Some(insts::OP_VWSUBU_WX),
                    x if x & 0b11111100000000000111000001111111 == 0b11011100000000000110000001010111 => Some(insts::OP_VWSUB_WX),
                    x if x & 0b11111100000000000111000001111111 == 0b00100100000000000110000001010111 => Some(insts::OP_VAADD_VX),
                    x if x & 0b11111100000000000111000001111111 == 0b00100000000000000110000001010111 => Some(insts::OP_VAADDU_VX),
                    x if x & 0b11111100000000000111000001111111 == 0b00101100000000000110000001010111 => Some(insts::OP_VASUB_VX),
                    x if x & 0b11111100000000000111000001111111 == 0b00101000000000000110000001010111 => Some(insts::OP_VASUBU_VX),
                    x if x & 0b11111100000000000111000001111111 == 0b10110100000000000110000001010111 => Some(insts::OP_VMACC_VX),
                    x if x & 0b11111100000000000111000001111111 == 0b10111100000000000110000001010111 => Some(insts::OP_VNMSAC_VX),
                    x if x & 0b11111100000000000111000001111111 == 0b10100100000000000110000001010111 => Some(insts::OP_VMADD_VX),
                    x if x & 0b11111100000000000111000001111111 == 0b10101100000000000110000001010111 => Some(insts::OP_VNMSUB_VX),
                    x if x & 0b11111100000000000111000001111111 == 0b11110000000000000110000001010111 => Some(insts::OP_VWMACCU_VX),
                    x if x & 0b11111100000000000111000001111111 == 0b11110100000000000110000001010111 => Some(insts::OP_VWMACC_VX),
                    x if x & 0b11111100000000000111000001111111 == 0b11111100000000000110000001010111 => Some(insts::OP_VWMACCSU_VX),
                    x if x & 0b11111100000000000111000001111111 == 0b11111000000000000110000001010111 => Some(insts::OP_VWMACCUS_VX),
                    x if x & 0b11111111111100000111000001111111 == 0b01000010000000000110000001010111 => Some(insts::OP_VMV_S_X),
                    x if x & 0b11111100000000000111000001111111 == 0b00111000000000000110000001010111 => Some(insts::OP_VSLIDE1UP_VX),
                    x if x & 0b11111100000000000111000001111111 == 0b00111100000000000110000001010111 => Some(insts::OP_VSLIDE1DOWN_VX),
                    _ => None,
                };
                inst_opt.map(|inst| {
                    VXtype::new(
                        inst,
                        rd(instruction_bits),
                        rs1(instruction_bits),
                        rs2(instruction_bits),
                        vm(instruction_bits),
                    )
                    .0
                })
            }
            0b111 => {
                #[rustfmt::skip]
                let r = match instruction_bits {
                    x if x & 0b10000000000000000111000001111111 == 0b00000000000000000111000001010111 => Some(Itype::new_u(insts::OP_VSETVLI, rd(instruction_bits), rs1(instruction_bits), utils::x(instruction_bits, 20, 11, 0)).0),
                    x if x & 0b11000000000000000111000001111111 == 0b11000000000000000111000001010111 => Some(Itype::new_u(insts::OP_VSETIVLI, rd(instruction_bits), rs1(instruction_bits), utils::x(instruction_bits, 20, 10, 0)).0),
                    x if x & 0b11111110000000000111000001111111 == 0b10000000000000000111000001010111 => Some(Rtype::new(insts::OP_VSETVL, rd(instruction_bits), rs1(instruction_bits), rs2(instruction_bits)).0),
                    _ => None,
                };
                r
            }
            _ => None,
        },
        _ => None,
    };

    inst.map(set_instruction_length_4)
}