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Changelog.md

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Version 3.1a

  • Added
    • Print TLB stats to the terminal after the simulation completes
    • Specify latency for each FPU ALU instruction (fadd, fsub, fmul, fdiv, fmin, fmax, fcvt, cvt, fle, flt, feq, fsgnj, fqsrt, fmv, fclass) via TinyEMU config file
    • Figure showing the high-level overview of MARSS-RISCV in README.md
  • Changed
    • Simplify the base DRAM model
      • All memory accesses simulate a fixed latency mem_access_latency
      • Any subsequent accesses to the same physical page occupies a lower delay, which is roughly 60 percent of the fixed mem_access_latency
      • More info here
    • Parallel operation of functional units can be enabled or disabled in the in-order core via TinyEMU config file
    • Clean exception handling code
    • Simulate page table entry read/write delays directly via memory controller using a configurable fixed latency pte_rw_latency
    • Don't stall the pipeline stage for the write request to complete on the memory controller
    • Make FPU-ALU non-pipelined
    • Rename dram_dispatch_queue tomem_request_queue
    • Update MARSS-RISCV Docs
    • Update README.md
    • Update TinyEMU config file here
  • Fixed
    • memory leaks

Version 3.0a

  • Added
    • Support for separate RISC-V Bios and Kernel
    • Command line option flush-sim-mem to flush simulator memory hierarchy on every fresh simulation run
    • Command line option sim-trace to generate instruction commit trace during simulation
    • Distinct configurable read-hit and write-hit latency for all the caches
    • Return address stack (RAS)
    • Branch prediction and speculative execution support for out of order core
    • Print performance counters on terminal when the simulation completes
    • More performance counters:
      • Instruction types
      • ecall
      • page walks for loads, stores and instructions
      • memory controller delay for data and instructions
      • hardware interrupts
  • Changed
    • Port to TinyEMU version 2019-12-21
    • For bimodal branch predictor, store prediction bits in a separate Branch history table (BHT)
    • For in-order core, non-memory instructions can forward their result from MEM stage in addition to EX stage
    • For in-order core, relaxed interlocking on WAW data hazard
    • Simplified out of order core design, ROB slots are now used as physical registers along with a single rename table and a single global issue queue
  • Fixed
    • Correctly calculated the rounding mode for floating pointing instruction decoding
    • Converted c.addiw result buffer into int32_t on 64-bit simulation
    • Set the data type to unint64_t for 64-bit simulation, for the buffer which holds the memory address for atomic instructions
    • Issue #13 and #14 (thanks to Okhotnikov Grigory)

Version 2.0a

  • Added
  • Changed
    • Flush all the CPU caches and DRAM models for every new simulation run
  • Fixed
    • Issue #8: useless cleaning of local variables

Version 1.1a

  • Added
    • Add 16550A UART support (thanks to Marc Gauthier)
    • Add a timestamp suffix to the stats file
  • Changed
    • Reworked the dram latency parameters to match the Sifive HiFive U540 Board
    • Increased the dram dispatch queue size from 32 to 64
  • Fixed
    • Calculation of hardware page walk latency
    • Miscalculation in page fault counters
    • Issue #2: memory leaks in copy_file
    • Issue #3: 'log' instead 'log2'