/
tlcs900h.sinc
1392 lines (1302 loc) · 82 KB
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tlcs900h.sinc
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# TLCS900H sleigh include file
define pcodeop normal_mode;
define pcodeop maximum_mode;
define pcodeop halt;
define token ins8 (8)
op_00 = (0,0)
op_00_01 = (0,1)
op_00_02 = (0,2)
op_00_03 = (0,3)
op_00_07 = (0,7)
op_01 = (1,1)
op_03 = (3,3)
op_04_05 = (4,5)
op_04_07 = (4,7)
op_06 = (6,6)
op_06_07 = (6,7)
op_07 = (7,7)
r8 = (0,2)
r16 = (0,2)
r32 = (0,2)
r8b_00_07 = (0,7)
r16b_00_07 = (0,7)
r32b_00_07 = (0,7)
r32b_02_07 = (2,7)
r8c_00_07 = (0,5)
r16c_00_07 = (0,5)
r32c_00_07 = (0,5)
imm3_00_02 = (0,2)
flags_00_03 = (0,3)
;
define token ins16 (16)
w_op_00_07 = (0,7)
w_op_00_02 = (0,2)
w_op_02 = (2,2)
w_op_03 = (3,3)
w_op_04_07 = (4,7)
w_op_08_15 = (8,15)
w_op_11 = (11,11)
w_op_12_15 = (12,15)
w_rm8_00_02 = (0,2)
w_rm8x_00_02 = (0,2)
w_rm16_00_02 = (0,2)
w_rm32_00_02 = (0,2)
w_rn8_08_10 = (8,10)
w_rn8x_08_10 = (8,10)
w_rn16_08_10 = (8,10)
w_rn32_08_10 = (8,10)
w_imm3_00_02 = (0,2)
w_imm3_08_10 = (8,10)
w_flags_08_11 = (8,11)
w_imm8_08_15 = (8,15)
;
define token ins24 (24)
l_op_00_01 = (0,1)
l_op_00_07 = (0,7)
l_op_03 = (3,3)
l_op_04_07 = (4,7)
l_r8_00_02 = (0,2)
l_r16_00_02 = (0,2)
l_r32_00_02 = (0,2)
l_r8b_16_23 = (16,23)
l_r16b_16_23 = (16,23)
l_r32b_02_07 = (2,7)
l_r32b_08_15 = (8,15)
l_imm16_08_23 = (8,23)
;
define token data8 (8)
imm8 = (0,7)
simm8 = (0,7) signed
;
define token data16 (16)
imm16 = (0,15)
simm16 = (0,15) signed
;
define token data24 (24)
imm24 = (0,23)
simm24 = (0,23) signed
;
define token data32 (32)
imm32 = (0,31)
simm32 = (0,31) signed
;
attach variables [ r32 w_rm32_00_02 w_rn32_08_10 ] [ XWA XBC XDE XHL XIX XIY XIZ XSP ];
attach variables [ r16 w_rm16_00_02 w_rn16_08_10 ] [ WA BC DE HL IX IY IZ SP ];
attach variables [ w_rm8x_00_02 w_rn8x_08_10 ] [ WA WA BC BC DE DE HL HL ];
attach variables [ r8 w_rm8_00_02 w_rn8_08_10 ] [ W A B C D E H L ];
# Banked registers
attach variables [ r8b_00_07 l_r8b_16_23 ] [
RA_0 RW_0 QA_0 QW_0 RC_0 RB_0 QC_0 QB_0 RE_0 RD_0 QE_0 QD_0 RL_0 RH_0 QL_0 QH_0
RA_1 RW_1 QA_1 QW_1 RC_1 RB_1 QC_1 QB_1 RE_1 RD_1 QE_1 QD_1 RL_1 RH_1 QL_1 QH_1
RA_2 RW_2 QA_2 QW_2 RC_2 RB_2 QC_2 QB_2 RE_2 RD_2 QE_2 QD_2 RL_2 RH_2 QL_2 QH_2
RA_3 RW_3 QA_3 QW_3 RC_3 RB_3 QC_3 QB_3 RE_3 RD_3 QE_3 QD_3 RL_3 RH_3 QL_3 QH_3
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
RA_P RW_P QA_P QW_P RC_P RB_P QC_P QB_P RE_P RD_P QE_P QD_P RL_P RH_P QL_P QH_P
A W QA QW C B QC QB E D QE QD L H QL QH
IXL IXH QIXL QIXH IYL IYH QIYL QIYH IZL IZH QIZL QIZH SPL SPH QSPL QSPH
];
attach variables [ r16b_00_07 l_r16b_16_23 ] [
RWA_0 RWA_0 QWA_0 QWA_0 RBC_0 RBC_0 QBC_0 QBC_0 RDE_0 RDE_0 QDE_0 QDE_0 RHL_0 RHL_0 QHL_0 QHL_0
RWA_1 RWA_1 QWA_1 QWA_1 RBC_1 RBC_1 QBC_1 QBC_1 RDE_1 RDE_1 QDE_1 QDE_1 RHL_1 RHL_1 QHL_1 QHL_1
RWA_2 RWA_2 QWA_2 QWA_2 RBC_2 RBC_2 QBC_2 QBC_2 RDE_2 RDE_2 QDE_2 QDE_2 RHL_2 RHL_2 QHL_2 QHL_2
RWA_3 RWA_3 QWA_3 QWA_3 RBC_3 RBC_3 QBC_3 QBC_3 RDE_3 RDE_3 QDE_3 QDE_3 RHL_3 RHL_3 QHL_3 QHL_3
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
RWA_P RWA_P QWA_P QWA_P RBC_P RBC_P QBC_P QBC_P RDE_P RDE_P QDE_P QDE_P RHL_P RHL_P QHL_P QHL_P
WA WA QWA QWA BC BC QBC QBC DE DE QDE QDE HL HL QHL QHL
IX IX QIX QIX IY IY QIY QIY IZ IZ QIZ QIZ SP SP QSP QSP
];
attach variables [ r32b_00_07 l_r32b_08_15 ] [
XWA_0 XWA_0 XWA_0 XWA_0 XBC_0 XBC_0 XBC_0 XBC_0 XDE_0 XDE_0 XDE_0 XDE_0 XHL_0 XHL_0 XHL_0 XHL_0
XWA_1 XWA_1 XWA_1 XWA_1 XBC_1 XBC_1 XBC_1 XBC_1 XDE_1 XDE_1 XDE_1 XDE_1 XHL_1 XHL_1 XHL_1 XHL_1
XWA_2 XWA_2 XWA_2 XWA_2 XBC_2 XBC_2 XBC_2 XBC_2 XDE_2 XDE_2 XDE_2 XDE_2 XHL_2 XHL_2 XHL_2 XHL_2
XWA_3 XWA_3 XWA_3 XWA_3 XBC_3 XBC_3 XBC_3 XBC_3 XDE_3 XDE_3 XDE_3 XDE_3 XHL_3 XHL_3 XHL_3 XHL_3
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
XWA_P XWA_P XWA_P XWA_P XBC_P XBC_P XBC_P XBC_P XDE_P XDE_P XDE_P XDE_P XHL_P XHL_P XHL_P XHL_P
XWA XWA XWA XWA XBC XBC XBC XBC XDE XDE XDE XDE XHL XHL XHL XHL
XIX XIX XIX XIX XIY XIY XIY XIY XIZ XIZ XIZ XIZ XSP XSP XSP XSP
];
# Banked register encoded in 6-bits, see "Appendix A: Memory addressing mode specify code"
attach variables [ r32b_02_07 l_r32b_02_07 ] [
XWA_0 XBC_0 XDE_0 XHL_0
XWA_1 XBC_1 XDE_1 XHL_1
XWA_2 XBC_2 XDE_2 XHL_2
XWA_3 XBC_3 XDE_3 XHL_3
_ _ _ _
_ _ _ _
_ _ _ _
_ _ _ _
_ _ _ _
_ _ _ _
_ _ _ _
_ _ _ _
_ _ _ _
XWA_P XBC_P XDE_P XHL_P
XWA XBC XDE XHL
XIX XIY XIZ XSP
];
# Control registers
attach variables [ r32c_00_07 ] [
DMAS_0 _ _ _
DMAS_1 _ _ _
DMAS_2 _ _ _
DMAS_3 _ _ _
DMAD_0 _ _ _
DMAD_1 _ _ _
DMAD_2 _ _ _
DMAD_3 _ _ _
_ _ _ _
_ _ _ _
_ _ _ _
_ _ _ _
_ _ _ _
_ _ _ _
_ _ _ _
XNSP _ _ _
];
attach variables [ r16c_00_07 ] [
_ _ _ _
_ _ _ _
_ _ _ _
_ _ _ _
_ _ _ _
_ _ _ _
_ _ _ _
_ _ _ _
DMAC_0 _ _ _
DMAC_1 _ _ _
DMAC_2 _ _ _
DMAC_3 _ _ _
_ _ _ _
_ _ _ _
_ _ _ _
NSP _ _ _
];
attach variables [ r8c_00_07 ] [
_ _ _ _
_ _ _ _
_ _ _ _
_ _ _ _
_ _ _ _
_ _ _ _
_ _ _ _
_ _ _ _
_ _ DMAM_0 _
_ _ DMAM_1 _
_ _ DMAM_2 _
_ _ DMAM_3 _
_ _ _ _
_ _ _ _
_ _ _ _
_ _ _ _
];
# Macros, see "Appendix B: Instruction Lists"
# Flag setters
macro setResultFlags(result) {
$(S_flag) = result s< 0;
$(Z_flag) = result == 0;
}
macro setAddFlags(result, op1, op2) {
setResultFlags(result);
$(H_flag) = (((op1 ^ op2 ^ result) >> 4) & 1) != 0;
$(V_flag) = ((op1 ^ result) & (op2 ^ result)) s< 0;
$(N_flag) = 0;
}
macro setSubtractFlags(result, op1, op2) {
setResultFlags(result);
$(H_flag) = (((op1 ^ op2 ^ result) >> 4) & 1) != 0;
$(V_flag) = ((op1 ^ result) & (op1 ^ op2)) s< 0;
$(N_flag) = 1;
}
macro setShiftFlags(result) {
setResultFlags(result);
$(H_flag) = 0;
$(V_flag) = (popcount(result) & 1:1) == 0;
$(N_flag) = 0;
}
macro setLogicalFlags(result) {
setResultFlags(result);
$(V_flag) = (popcount(result) & 1:1) == 0;
$(N_flag) = 0;
$(C_flag) = 0;
}
# (2) Exchange
macro ex(dst, src) {
local tmp = dst;
dst = src;
src = tmp;
}
macro mirr(dst) {
local tmp:2 = ((dst & 0b1000000000000000) >> 15)
| ((dst & 0b0100000000000000) >> 13)
| ((dst & 0b0010000000000000) >> 11)
| ((dst & 0b0001000000000000) >> 9)
| ((dst & 0b0000100000000000) >> 7)
| ((dst & 0b0000010000000000) >> 5)
| ((dst & 0b0000001000000000) >> 3)
| ((dst & 0b0000000100000000) >> 1)
| ((dst & 0b0000000010000000) << 1)
| ((dst & 0b0000000001000000) << 3)
| ((dst & 0b0000000000100000) << 5)
| ((dst & 0b0000000000010000) << 7)
| ((dst & 0b0000000000001000) << 9)
| ((dst & 0b0000000000000100) << 11)
| ((dst & 0b0000000000000010) << 13)
| ((dst & 0b0000000000000001) << 15);
dst = tmp;
}
# (4) Arithmetic Operations
macro add(op1, op2) {
local tmp_op1 = op1;
local tmp_op2 = op2;
op1 = op1 + op2;
setAddFlags(op1, tmp_op1, tmp_op2);
$(C_flag) = carry(tmp_op1, tmp_op2);
}
macro add32(op1, op2) {
add(op1, op2);
$(H_flag) = 0; # Undefined
}
macro adc(op1, op2) {
local tmp_op1 = op1;
local tmp_op2 = op2;
local tmp_C = $(C_flag);
op1 = op1 + op2 + zext(tmp_C);
setAddFlags(op1, tmp_op1, tmp_op2);
$(C_flag) = (carry(tmp_op1, zext(tmp_C)) || carry(tmp_op2, tmp_op1 + zext(tmp_C)));
}
macro adc32(op1, op2) {
adc(op1, op2);
$(H_flag) = 0; # Undefined
}
macro sub(op1, op2) {
local tmp_op1 = op1;
local tmp_op2 = op2;
op1 = op1 - op2;
setSubtractFlags(op1, tmp_op1, tmp_op2);
$(C_flag) = tmp_op1 < tmp_op2;
}
macro sub32(op1, op2) {
sub(op1, op2);
$(H_flag) = 0; # Undefined
}
macro sbc(op1, op2) {
local tmp_op1 = op1;
local tmp_op2 = op2;
local tmp_C = $(C_flag);
op1 = op1 - op2 - zext(tmp_C);
setSubtractFlags(op1, tmp_op1, tmp_op2);
local carries = tmp_op1 ^ tmp_op2 ^ op1;
local overflow = (tmp_op1 ^ op1) & (tmp_op2 ^ tmp_op1);
$(C_flag) = (carries ^ overflow) s< 0;
}
macro sbc32(op1, op2) {
sbc(op1, op2);
$(H_flag) = 0; # Undefined
}
macro cp(op1, op2) {
local tmp = op1 - op2;
setSubtractFlags(tmp, op1, op2);
$(C_flag) = tmp > op1;
}
macro cp32(op1, op2) {
cp(op1, op2);
$(H_flag) = 0; # Undefined
}
macro inc(op1, op2) {
# #3 in operands indicates from 1 to 8; object codes correspond from 1 to 7,0.
local tmp_imm = op2;
if (tmp_imm != 0) goto <result>;
tmp_imm = 8;
<result>
local tmp_C = $(C_flag);
add(op1, tmp_imm);
$(C_flag) = tmp_C;
}
macro incwl(op1, op2) {
# #3 in operands indicates from 1 to 8; object codes correspond from 1 to 7,0.
local tmp_imm:1 = op2;
if (tmp_imm != 0) goto <result>;
tmp_imm = 8;
<result>
# With the INC #3,r instruction, if the operand is a word or a long word, no flags change.
op1 = op1 + zext(tmp_imm);
}
macro dec(op1, op2) {
# #3 in operands indicates from 1 to 8; object codes correspond from 1 to 7,0.
local tmp_imm = op2;
if (tmp_imm != 0) goto <result>;
tmp_imm = 8;
<result>
local tmp_C = $(C_flag);
sub(op1, tmp_imm);
$(C_flag) = tmp_C;
}
macro decwl(op1, op2) {
# #3 in operands indicates from 1 to 8; object codes correspond from 1 to 7,0.
local tmp_imm:1 = op2;
if (tmp_imm != 0) goto <result>;
tmp_imm = 8;
<result>
# With the DEC #3,r instruction, if the operand is a word or a long word, no flags change.
op1 = op1 - zext(tmp_imm);
}
macro neg(op1) {
local tmp_op1 = op1;
op1 = -op1;
setSubtractFlags(op1, 0, tmp_op1);
$(C_flag) = 0 < tmp_op1;
}
macro daa(dst) {
local tmp:1 = dst;
if ($(C_flag) || (tmp > 0x99)) goto <c_or_tmp8_gt_0x99>;
goto <h_test>;
<c_or_tmp8_gt_0x99>
if ($(N_flag) != 0) goto <c_or_tmp8_gt_0x99_n_flag_eq_1>;
tmp = tmp + 0x60;
goto <h_test>;
<c_or_tmp8_gt_0x99_n_flag_eq_1>
tmp = tmp - 0x60;
<h_test>
if ($(H_flag) || ((tmp & 0x0f) > 0x09)) goto <h_or_tmp4_gt_0x09>;
goto <n_test>;
<h_or_tmp4_gt_0x09>
if ($(N_flag) != 0) goto <h_or_tmp4_gt_0x09_n_flag_eq_1>;
tmp = tmp + 0x06;
goto <n_test>;
<h_or_tmp4_gt_0x09_n_flag_eq_1>
tmp = tmp - 0x06;
<n_test>
if ($(N_flag) != 0) goto <n_flag_eq_1>;
$(C_flag) = $(C_flag) | (tmp < dst);
goto <c_flag_updated>;
<n_flag_eq_1>
$(C_flag) = $(C_flag) | (tmp > dst);
<c_flag_updated>
$(V_flag) = (popcount(tmp) & 1:1) == 0;
$(H_flag) = (((tmp ^ dst) >> 4) & 1) != 0;
$(Z_flag) = tmp == 0;
$(S_flag) = tmp s< 0;
dst = tmp;
}
macro extz16(dst) { dst = zext(dst:1); }
macro extz32(dst) { dst = zext(dst:2); }
macro exts16(dst) { dst = sext(dst:1); }
macro exts32(dst) { dst = sext(dst:2); }
macro paa(dst) {
if ((dst & 1) == 0) goto <end>;
dst = dst + 1;
<end>
}
macro mul8(op1, op2) { op1 = zext(op1:1) * zext(op2); }
macro mul16(op1, op2) { op1 = zext(op1:2) * zext(op2); }
macro mul(op1, op2) { op1 = op1 * op2; }
macro muls8(op1, op2) { op1 = sext(op1:1) * sext(op2); }
macro muls16(op1, op2) { op1 = sext(op1:2) * sext(op2); }
macro muls(op1, op2) { op1 = sext(op1) * sext(op2); }
macro div(op1, op2) {
$(V_flag) = op2 == 0;
local quotient = zext(op1) / zext(op2);
local remainder = zext(op1) % zext(op2);
op1 = ((remainder & 0xffff) << 16) | quotient;
}
macro divs(op1, op2) {
$(V_flag) = op2 == 0;
local quotient = sext(op1) s/ sext(op2);
local remainder = sext(op1) % sext(op2);
op1 = ((remainder & 0xffff) << 16) | quotient;
}
macro mula(dst) {
local mul_result:2 = (*:2 XDE) * (*:2 XHL);
dst = dst + mul_result;
XHL = XHL - 2;
$(Z_flag) = (dst == 0);
$(V_flag) = (mul_result / (*:2 XDE) == (*:2 XHL));
}
macro minc(n, dst, step) {
if ((dst % n) == n - step) goto <cycle>;
dst = dst + step;
goto <end>;
<cycle>
dst = dst - (n - step);
<end>
}
macro mdec(n, dst, step) {
if ((dst % n) == 0) goto <cycle>;
dst = dst - step;
goto <end>;
<cycle>
dst = dst + (n - step);
<end>
}
# (3) Load Increment/Decrement & Compare Increment/Decrement Size
macro ld_rep(rm, rn, step, once) {
<top>
rm = rm + step; rn = rn + step; *:4 rm = *:4 rn; BC = BC - 1;
if (once == 1:1) goto <end>;
if (BC == 0) goto <end>;
goto <top>;
<end>
$(H_flag) = 0;
$(V_flag) = (BC != 0);
$(N_flag) = 0;
}
macro cp_rep(rm, rn, step, once) {
<top>
cp(rm, rn); rn = rn + step; BC = BC - 1;
if (once == 1:1) goto <end>;
if (BC == 0) goto <end>;
if (rm == rn) goto <end>;
goto <top>;
<end>
$(V_flag) = (BC != 0);
$(N_flag) = 1;
}
# (5) Logical operations
macro and(op1, op2) {
op1 = op1 & op2;
setLogicalFlags(op1);
$(H_flag) = 1;
}
macro and32(op1, op2) {
and(op1, op2);
$(V_flag) = 0; # Undefined
}
macro or(op1, op2) {
op1 = op1 | op2;
setLogicalFlags(op1);
$(H_flag) = 0;
}
macro or32(op1, op2) {
or(op1, op2);
$(V_flag) = 0; # Undefined
}
macro xor(op1, op2) {
op1 = op1 ^ op2;
setLogicalFlags(op1);
$(H_flag) = 0;
}
macro xor32(op1, op2) {
xor(op1, op2);
$(V_flag) = 0; # Undefined
}
macro cpl(op1) {
op1 = ~op1;
$(H_flag) = 1;
$(N_flag) = 1;
}
# (6) Bit operations
macro ldcf(n, src) {
local src_bit:1 = ((src >> n) & 1) != 0;
$(C_flag) = src_bit;
}
macro stcf(n, dst) {
local mask = ($(C_flag) << n);
dst = dst | zext(mask);
}
macro andcf(n, src) {
local src_bit:1 = ((src >> n) & 1) != 0;
local val:1 = $(C_flag) & src_bit;
$(C_flag) = val;
}
macro orcf(n, src) {
local src_bit:1 = ((src >> n) & 1) != 0;
local val:1 = $(C_flag) | src_bit;
$(C_flag) = val;
}
macro xorcf(n, src) {
local src_bit:1 = ((src >> n) & 1) != 0;
local val:1 = $(C_flag) ^ src_bit;
$(C_flag) = val;
}
macro bit(n, src) {
local src_bit:1 = ((src >> n) & 1) != 0;
$(S_flag) = 0; # Undefined
$(Z_flag) = src_bit == 0;
$(H_flag) = 1;
$(V_flag) = 0; # Undefined
$(N_flag) = 0;
}
macro res(n, dst) {
local mask = ~(1 << n);
dst = dst & mask;
}
macro set(n, dst) {
local mask = (1 << n);
dst = dst | mask;
}
macro chg(n, dst) {
local dst_bit:1 = (((dst >> n) & 1) ^ 1) != 0;
local mask = dst_bit << n;
dst = dst & zext(mask);
}
macro tset(n, dst) {
local dst_bit:1 = ((dst >> n) & 1) != 0;
$(S_flag) = 0; # Undefined
$(Z_flag) = dst_bit == 0;
$(H_flag) = 1;
$(V_flag) = 0; # Undefined
$(N_flag) = 0;
set(n, dst);
}
macro bs1f(dst, src) {
local i:1 = 0;
<search>
local b = 1 << i;
if ((src & b) == 0) goto <next_bit>;
dst = i;
$(V_flag) = 0;
goto <end>;
<next_bit>
i = i + 1;
if (i < 16) goto <search>;
$(V_flag) = 1;
<end>
}
macro bs1b(dst, src) {
local i:1 = 15;
<search>
local b = 1 << i;
if ((src & b) == 0) goto <next_bit>;
dst = i;
$(V_flag) = 0;
goto <end>;
<next_bit>
i = i - 1;
if (i > -1) goto <search>;
$(V_flag) = 1;
<end>
}
# (7) Special operations and CPU control
macro sync_banks(prev_rfp) {
# To simplify register updates, we only synchronize
# the current and previous banks when switching to another bank.
XWA_P = XWA; XBC_P = XBC; XDE_P = XDE; XHL_P = XHL;
if (prev_rfp == 1) goto <prev_st1>;
if (prev_rfp == 2) goto <prev_st2>;
if (prev_rfp == 3) goto <prev_st3>;
XWA_0 = XWA; XBC_0 = XBC; XDE_0 = XDE; XHL_0 = XHL;
goto <prev_end>;
<prev_st1>
XWA_1 = XWA; XBC_1 = XBC; XDE_1 = XDE; XHL_1 = XHL;
goto <prev_end>;
<prev_st2>
XWA_2 = XWA; XBC_2 = XBC; XDE_2 = XDE; XHL_2 = XHL;
goto <prev_end>;
<prev_st3>
XWA_3 = XWA; XBC_3 = XBC; XDE_3 = XDE; XHL_3 = XHL;
<prev_end>
if ($(RFP) == 1) goto <ld1>;
if ($(RFP) == 2) goto <ld2>;
if ($(RFP) == 3) goto <ld3>;
XWA = XWA_0; XBC = XBC_0; XDE = XDE_0; XHL = XHL_0;
goto <end>;
<ld1>
XWA = XWA_1; XBC = XBC_1; XDE = XDE_1; XHL = XHL_1;
goto <end>;
<ld2>
XWA = XWA_2; XBC = XBC_2; XDE = XDE_2; XHL = XHL_2;
goto <end>;
<ld3>
XWA = XWA_3; XBC = XBC_3; XDE = XDE_3; XHL = XHL_3;
<end>
}
macro switch_bank(i) {
local prev_rfp = $(RFP);
$(RFP) = i & 0b111;
if ($(MAX) == 0) goto <prev_ld>;
$(RFP) = $(RFP) & 0b011;
<prev_ld>
sync_banks(prev_rfp);
}
macro push32(val32) {
XSP = XSP - 4;
*:4 XSP = val32;
}
macro push16(val16) {
XSP = XSP - 2;
*:2 XSP = val16;
}
macro push8(val8) {
XSP = XSP - 1;
*:1 XSP = val8;
}
macro pop32(ret32) {
ret32 = *:4 XSP;
XSP = XSP + 4;
}
macro pop16(ret16) {
ret16 = *:2 XSP;
XSP = XSP + 2;
}
macro pop8(ret8) {
ret8 = *:1 XSP;
XSP = XSP + 1;
}
macro pop16_sr() {
local prev_rfp = $(RFP);
pop16(SR);
if (prev_rfp == $(RFP)) goto <end>;
sync_banks(prev_rfp);
<end>
}
macro link(dst, n) {
XSP = XSP - 4;
*:4 XSP = dst;
dst = XSP;
XSP = XSP + n;
}
macro unlk(dst) {
XSP = dst;
XSP = XSP + 4;
dst = *:4 XSP;
}
# (8) Rotate and shift
macro rlc(count, reg, width) {
reg = (reg << count) | (reg >> (width - count));
setShiftFlags(reg);
}
macro rrc(count, reg, width) {
reg = (reg >> count) | (reg << (width - count));
setShiftFlags(reg);
}
macro rl(count, reg, width) {
reg = (reg << count) | (reg >> (width - count)) | (zext($(C_flag)) << (count - 1));
setShiftFlags(reg);
}
macro rr(count, reg, width) {
reg = (reg >> count) | (reg << (width - count)) | (zext($(C_flag)) << (width - count));
setShiftFlags(reg);
}
macro sll(count, reg) {
local i = count;
<cycle>
if (i == 0:1) goto <end>;
$(C_flag) = reg s< 0;
reg = reg << 1;
i = i - 1:1;
goto <cycle>;
<end>
setShiftFlags(reg);
}
macro srl(count, reg) {
$(C_flag) = (reg & (1 << (count - 1))) != 0;
reg = reg >> count;
setShiftFlags(reg);
}
macro sla(count, reg) {
sll(count, reg);
}
macro sra(count, reg) {
$(C_flag) = (reg & (1 << (count - 1))) != 0;
reg = reg s>> count;
setShiftFlags(reg);
}
macro rld(dst1, dst2) {
local dst1_00_03:1 = dst1:1 & 0x0f;
local dst1_04_07:1 = dst1:1 & 0xf0;
local dst2_00_03:1 = dst2:1 & 0x0f;
local dst2_04_07:1 = dst2:1 & 0xf0;
dst1 = ((dst1 >> 8) << 8) | dst1_04_07 | (dst2_04_07 >> 4);
dst2 = ((dst2 >> 8) << 8) | zext((dst2_00_03 << 4) | dst1_00_03);
$(S_flag) = dst1 s< 0;
$(Z_flag) = dst1 == 0;
$(H_flag) = 0;
$(V_flag) = (popcount(dst1) & 1:1) == 0;
$(N_flag) = 0;
}
macro rrd(dst1, dst2) {
local dst1_00_03:1 = dst1:1 & 0x0f;
local dst1_04_07:1 = dst1:1 & 0xf0;
local dst2_00_03:1 = dst2:1 & 0x0f;
local dst2_04_07:1 = dst2:1 & 0xf0;
dst1 = ((dst1 >> 8) << 8) | dst1_04_07 | dst2_00_03;
dst2 = ((dst2 >> 8) << 8) | zext((dst1_04_07 << 4) | (dst2_04_07 >> 4));
$(S_flag) = dst1 s< 0;
$(Z_flag) = dst1 == 0;
$(H_flag) = 0;
$(V_flag) = (popcount(dst1) & 1:1) == 0;
$(N_flag) = 0;
}
# Constructors
# See "4. Addressing Modes"
# Absolute
addr8: imm8 is imm8 { export *:1 imm8; }
addr16: imm16 is imm16 { export *:2 imm16; }
addr24: imm24 is imm24 { export *:3 imm24; }
addr32: imm32 is imm32 { export *:4 imm32; }
addr8i8: imm8 is imm8 { export *:1 imm8; }
addr8i16: imm8 is imm8 { export *:2 imm8; }
addr8i32: imm8 is imm8 { export *:4 imm8; }
addr16i8: imm16 is imm16 { export *:1 imm16; }
addr16i8_: imm16 is imm16 { export *:1 imm16; }
addr16i16: imm16 is imm16 { export *:2 imm16; }
addr16i16_: imm16 is imm16 { export *:2 imm16; }
addr16i32: imm16 is imm16 { export *:4 imm16; }
addr24i8: imm24 is imm24 { export *:1 imm24; }
addr24i16: imm24 is imm24 { export *:2 imm24; }
addr24i24: imm24 is imm24 { export *:3 imm24; }
addr24i32: imm24 is imm24 { export *:4 imm24; }
# Register
addr32m8: w_rm32_00_02 is w_rm32_00_02 { export *:1 w_rm32_00_02; }
addr32m16: w_rm32_00_02 is w_rm32_00_02 { export *:2 w_rm32_00_02; }
addr32m32: w_rm32_00_02 is w_rm32_00_02 { export *:4 w_rm32_00_02; }
# Register indirect + post-increment / pre-decrement
r32b_mem: r32b_02_07 is op_06=0b1 & op_00_03=0b0011 ; r32b_02_07 & op_00_01=0b00 { export r32b_02_07; }
r32b_mem: "-"^r32b_02_07 is op_06=0b1 & op_00_03=0b0100 ; r32b_02_07 & op_00_01 { r32b_02_07 = r32b_02_07 - (1 << op_00_01); export r32b_02_07; }
r32b_mem: r32b_02_07^"+" is op_06=0b1 & op_00_03=0b0101 ; r32b_02_07 & op_00_01 { tmp = r32b_02_07; r32b_02_07 = r32b_02_07 + (1 << op_00_01); export tmp; }
r32b_eam: r32b_mem is r32b_mem { export *:4 r32b_mem; }
# Register displacement
r32d8: w_rm32_00_02^"+"^w_imm8_08_15 is w_rm32_00_02 & w_imm8_08_15 { tmp:4 = (w_rm32_00_02 + w_imm8_08_15); export tmp; }
addr32d8: r32d8 is r32d8 { export *:1 r32d8; }
addr32d16: r32d8 is r32d8 { export *:2 r32d8; }
addr32d32: r32d8 is r32d8 { export *:4 r32d8; }
# Banked register index + displacement
r32b_dsp: l_r32b_02_07^"+"^l_imm16_08_23 is l_r32b_02_07 & l_op_00_01=0b01 & l_imm16_08_23 { tmp:4 = (l_r32b_02_07 + l_imm16_08_23); export tmp; }
r32b_dsp: l_r32b_08_15^"+"^l_r8b_16_23 is l_op_00_07=0b011 & l_r32b_08_15 & l_r8b_16_23 { tmp:4 = (l_r32b_08_15 + zext(l_r8b_16_23)); export tmp; }
r32b_dsp: l_r32b_08_15^"+"^l_r16b_16_23 is l_op_00_07=0b111 & l_r32b_08_15 & l_r16b_16_23 { tmp:4 = (l_r32b_08_15 + zext(l_r16b_16_23)); export tmp; }
r32b_ead: r32b_dsp is r32b_dsp { export *:4 r32b_dsp; }
# Relative
rel8: reloc is simm8 [ reloc=inst_next+simm8; ] { export *[ram]:4 reloc; }
rel16: reloc is simm16 [ reloc=((inst_next >> 16) << 16) | ((inst_next + simm16) & 0xFFFF); ] { export *[ram]:4 reloc; }
rel32: reloc is simm32 [ reloc=inst_next+simm32; ] { export *[ram]:4 reloc; }
cc: "F" is flags_00_03=0x0 { c:1 = 0; export c; }
cc: "LT" is flags_00_03=0x1 { c:1 = ($(S_flag) ^ $(V_flag)); export c; }
cc: "LE" is flags_00_03=0x2 { c:1 = ($(Z_flag) | ($(S_flag) ^ $(V_flag))); export c; }
cc: "ULE" is flags_00_03=0x3 { c:1 = ($(C_flag) | $(Z_flag)); export c; }
cc: "PE/OV" is flags_00_03=0x4 { c:1 = $(V_flag); export c; }
cc: "M/MI" is flags_00_03=0x5 { c:1 = $(S_flag); export c; }
cc: "Z" is flags_00_03=0x6 { c:1 = $(Z_flag); export c; }
cc: "C/ULT" is flags_00_03=0x7 { c:1 = $(C_flag); export c; }
cc: "T" is flags_00_03=0x8 { c:1 = 1; export c; }
cc: "GE" is flags_00_03=0x9 { c:1 = ($(S_flag) ^ $(V_flag)) == 0; export c; }
cc: "GT" is flags_00_03=0xa { c:1 = ($(Z_flag) | ($(S_flag) ^ $(V_flag))) == 0; export c; }
cc: "UGT" is flags_00_03=0xb { c:1 = ($(C_flag) | $(Z_flag)) == 0; export c; }
cc: "PO/NOV" is flags_00_03=0xc { c:1 = $(V_flag) == 0; export c; }
cc: "P/PL" is flags_00_03=0xd { c:1 = $(S_flag) == 0; export c; }
cc: "NZ/NE" is flags_00_03=0xe { c:1 = $(Z_flag) == 0; export c; }
cc: "NC/UGE" is flags_00_03=0xf { c:1 = $(C_flag) == 0; export c; }
w_cc: "F" is w_flags_08_11=0x0 { c:1 = 0; export c; }
w_cc: "LT" is w_flags_08_11=0x1 { c:1 = ($(S_flag) ^ $(V_flag)); export c; }
w_cc: "LE" is w_flags_08_11=0x2 { c:1 = ($(Z_flag) | ($(S_flag) ^ $(V_flag))); export c; }
w_cc: "ULE" is w_flags_08_11=0x3 { c:1 = ($(C_flag) | $(Z_flag)); export c; }
w_cc: "PE/OV" is w_flags_08_11=0x4 { c:1 = $(V_flag); export c; }
w_cc: "M/MI" is w_flags_08_11=0x5 { c:1 = $(S_flag); export c; }
w_cc: "Z" is w_flags_08_11=0x6 { c:1 = $(Z_flag); export c; }
w_cc: "C/ULT" is w_flags_08_11=0x7 { c:1 = $(C_flag); export c; }
w_cc: "T" is w_flags_08_11=0x8 { c:1 = 1; export c; }
w_cc: "GE" is w_flags_08_11=0x9 { c:1 = ($(S_flag) ^ $(V_flag)) == 0; export c; }
w_cc: "GT" is w_flags_08_11=0xa { c:1 = ($(Z_flag) | ($(S_flag) ^ $(V_flag))) == 0; export c; }
w_cc: "UGT" is w_flags_08_11=0xb { c:1 = ($(C_flag) | $(Z_flag)) == 0; export c; }
w_cc: "PO/NOV" is w_flags_08_11=0xc { c:1 = $(V_flag) == 0; export c; }
w_cc: "P/PL" is w_flags_08_11=0xd { c:1 = $(S_flag) == 0; export c; }
w_cc: "NZ/NE" is w_flags_08_11=0xe { c:1 = $(Z_flag) == 0; export c; }
w_cc: "NC/UGE" is w_flags_08_11=0xf { c:1 = $(C_flag) == 0; export c; }
# Instructions, see "Appendix C: Instruction Code Maps"
## 1-byte op code instructions
:nop is op_00_07=0x00 {}
:normal is op_00_07=0x01 { normal_mode(); }
:push SR is op_00_07=0x02 & SR { push16(SR); }
:pop SR is op_00_07=0x03 & SR { pop16_sr(); }
:max is op_00_07=0x04 { maximum_mode(); }
:halt is op_00_07=0x05 { halt(); }
:ei imm8 is op_00_07=0x06 ; imm8 { $(IFF) = imm8 & 0b111; }
:reti is op_00_07=0x07 {
pop16_sr();
pop32(PC);
return [PC];
}
:ld (addr8),imm8 is op_00_07=0x08 ; addr8 ; imm8 { addr8 = imm8; }
:push imm8 is op_00_07=0x09 ; imm8 { push8(imm8:1); }
:ldw (addr8),imm16 is op_00_07=0x0a ; addr8 ; imm16 { addr8 = imm16; }
:pushw imm16 is op_00_07=0x0b ; imm16 { push16(imm16:2); }
:incf is op_00_07=0x0c { switch_bank($(RFP) + 1); }
:decf is op_00_07=0x0d { switch_bank($(RFP) - 1); }
:ret is op_00_07=0x0e {
pop32(PC);
return [PC];
}
:retd imm16 is op_00_07=0x0f ; imm16 {
pop32(PC);
XSP = XSP + imm16;
return [PC];
}
# User manual has a typo on RCF's flags caption, which doesn't match
# its diagram. Update the same flags as SCF, which has consistent info.
:rcf is op_00_07=0x10 { $(N_flag) = 0; $(C_flag) = 0; $(H_flag) = 0; }
:scf is op_00_07=0x11 { $(N_flag) = 0; $(C_flag) = 1; $(H_flag) = 0; }
:ccf is op_00_07=0x12 {
$(N_flag) = 0;
$(C_flag) = ~$(C_flag);
$(H_flag) = 0; # Undefined
}
:zcf is op_00_07=0x13 {
$(N_flag) = 0;
$(C_flag) = ~$(Z_flag);
$(H_flag) = 0; # Undefined
}
:push A is op_00_07=0x14 & A { push8(A); }
:pop A is op_00_07=0x15 & A { pop8(A); }
:ex F,F_I is op_00_07=0x16 & F & F_I { ex(F, F_I); }
:ldf imm8 is op_00_07=0x17 ; imm8 { switch_bank(imm8); }
:push F is op_00_07=0x18 & F { push8(F); }
:pop F is op_00_07=0x19 & F { pop8(F); }
:jp addr16 is op_00_07=0x1a; addr16 { goto addr16; }
:jp addr24 is op_00_07=0x1b; addr24 { goto addr24; }
:call addr16 is op_00_07=0x1c; addr16 {
push32(&:4 inst_next);
call addr16;
}
:call addr24 is op_00_07=0x1d; addr24 {
push32(&:4 inst_next);
call addr24;
}
:calr rel16 is op_00_07=0x1e; rel16 {
push32(&:4 inst_next);
call rel16;
}
:ld r8,imm8 is op_04_07=0b0010 & op_03=0b0 & r8 ; imm8 { r8 = imm8; }
:ld r16,imm16 is op_04_07=0b0011 & op_03=0b0 & r16 ; imm16 { r16 = imm16; }
:ld r32,imm32 is op_04_07=0b0100 & op_03=0b0 & r32 ; imm32 { r32 = imm32; }
:push r16 is op_04_07=0b0010 & op_03=0b1 & r16 { push16(r16); }
:push r32 is op_04_07=0b0011 & op_03=0b1 & r32 { push32(r32); }
:pop r16 is op_04_07=0b0100 & op_03=0b1 & r16 { pop16(r16); }
:pop r32 is op_04_07=0b0101 & op_03=0b1 & r32 { pop32(r32); }
:jr cc, rel8 is op_04_07=0b0110 & cc & flags_00_03 ; rel8 { if (cc) goto rel8; }
:jrl cc, rel16 is op_04_07=0b0111 & cc & flags_00_03 ; rel16 { if (cc) goto rel16; }
:ldx (addr8),imm8 is op_00_07=0xf7 ; addr8 ; imm8 { addr8 = imm8; }
:swi imm3_00_02 is op_04_07=0b1111 & op_03=0b1 & imm3_00_02 {
push32(&:4 inst_next);
push16(SR);
$(SYSM) = 1;
local handler = *[ram]:4 (0xffff00:4 + zext(imm3_00_02:1 << 2));
call [handler];
}
## 1st byte: reg
:ld w_rm8_00_02,imm8 is w_op_08_15=0b0011 & w_op_04_07=0b1100 & w_op_03=0b1 & w_rm8_00_02 ; imm8 { w_rm8_00_02 = imm8; }
:ld w_rm16_00_02,imm16 is w_op_08_15=0b0011 & w_op_04_07=0b1101 & w_op_03=0b1 & w_rm16_00_02 ; imm16 { w_rm16_00_02 = imm16; }
:ld w_rm32_00_02,imm32 is w_op_08_15=0b0011 & w_op_04_07=0b1110 & w_op_03=0b1 & w_rm32_00_02 ; imm32 { w_rm32_00_02 = imm32; }
:push w_rm8_00_02 is w_op_08_15=0b0100 & w_op_04_07=0b1100 & w_op_03=0b1 & w_rm8_00_02 { push8(w_rm8_00_02); }
:push w_rm16_00_02 is w_op_08_15=0b0100 & w_op_04_07=0b1101 & w_op_03=0b1 & w_rm16_00_02 { push16(w_rm16_00_02); }
:push w_rm32_00_02 is w_op_08_15=0b0100 & w_op_04_07=0b1110 & w_op_03=0b1 & w_rm32_00_02 { push32(w_rm32_00_02); }
:pop w_rm8_00_02 is w_op_08_15=0b0101 & w_op_04_07=0b1100 & w_op_03=0b1 & w_rm8_00_02 { pop8(w_rm8_00_02); }
:pop w_rm16_00_02 is w_op_08_15=0b0101 & w_op_04_07=0b1101 & w_op_03=0b1 & w_rm16_00_02 { pop16(w_rm16_00_02); }
:pop w_rm32_00_02 is w_op_08_15=0b0101 & w_op_04_07=0b1110 & w_op_03=0b1 & w_rm32_00_02 { pop32(w_rm32_00_02); }
:cpl w_rm8_00_02 is w_op_08_15=0b0110 & w_op_04_07=0b1100 & w_op_03=0b1 & w_rm8_00_02 { cpl(w_rm8_00_02); }
:cpl w_rm16_00_02 is w_op_08_15=0b0110 & w_op_04_07=0b1101 & w_op_03=0b1 & w_rm16_00_02 { cpl(w_rm16_00_02); }
:cpl w_rm32_00_02 is w_op_08_15=0b0110 & w_op_04_07=0b1110 & w_op_03=0b1 & w_rm32_00_02 { cpl(w_rm32_00_02); }
:neg w_rm8_00_02 is w_op_08_15=0b0111 & w_op_04_07=0b1100 & w_op_03=0b1 & w_rm8_00_02 { neg(w_rm8_00_02); }
:neg w_rm16_00_02 is w_op_08_15=0b0111 & w_op_04_07=0b1101 & w_op_03=0b1 & w_rm16_00_02 { neg(w_rm16_00_02); }
:neg w_rm32_00_02 is w_op_08_15=0b0111 & w_op_04_07=0b1110 & w_op_03=0b1 & w_rm32_00_02 { neg(w_rm32_00_02); }
# These (and other) mul/div instructions use larger registers
# than specified in the User Manual. This is a workaround for
# expanded storage of the operation result without register space
# hacks. We use truncation in macros to compute expected results.
:mul w_rm8x_00_02,imm8 is w_op_08_15=0b1000 & w_op_04_07=0b1100 & w_op_03=0b1 & w_rm8x_00_02 ; imm8 { mul8(w_rm8x_00_02,imm8:1); }
:mul w_rm32_00_02,imm16 is w_op_08_15=0b1000 & w_op_04_07=0b1101 & w_op_03=0b1 & w_rm32_00_02 ; imm16 { mul16(w_rm32_00_02,imm16:2); }
:mul w_rm32_00_02,imm32 is w_op_08_15=0b1000 & w_op_04_07=0b1110 & w_op_03=0b1 & w_rm32_00_02 ; imm32 { mul(w_rm32_00_02,imm32:4); }
:muls w_rm8x_00_02,imm8 is w_op_08_15=0b1001 & w_op_04_07=0b1100 & w_op_03=0b1 & w_rm8x_00_02 ; imm8 { muls8(w_rm8x_00_02,imm8:1); }
:muls w_rm32_00_02,imm16 is w_op_08_15=0b1001 & w_op_04_07=0b1101 & w_op_03=0b1 & w_rm32_00_02 ; imm16 { muls16(w_rm32_00_02,imm16:2); }
:muls w_rm32_00_02,imm32 is w_op_08_15=0b1001 & w_op_04_07=0b1110 & w_op_03=0b1 & w_rm32_00_02 ; imm32 { muls(w_rm32_00_02,imm32:4); }
:div w_rm8x_00_02,imm8 is w_op_08_15=0b1010 & w_op_04_07=0b1100 & w_op_03=0b1 & w_rm8x_00_02 ; imm8 { div(w_rm8x_00_02,imm8:1); }
:div w_rm32_00_02,imm16 is w_op_08_15=0b1010 & w_op_04_07=0b1101 & w_op_03=0b1 & w_rm32_00_02 ; imm16 { div(w_rm32_00_02,imm16:2); }
:div w_rm32_00_02,imm32 is w_op_08_15=0b1010 & w_op_04_07=0b1110 & w_op_03=0b1 & w_rm32_00_02 ; imm32 { div(w_rm32_00_02,imm32:4); }
:divs w_rm8x_00_02,imm8 is w_op_08_15=0b1011 & w_op_04_07=0b1100 & w_op_03=0b1 & w_rm8x_00_02 ; imm8 { divs(w_rm8x_00_02,imm8:1); }
:divs w_rm32_00_02,imm16 is w_op_08_15=0b1011 & w_op_04_07=0b1101 & w_op_03=0b1 & w_rm32_00_02 ; imm16 { divs(w_rm32_00_02,imm16:2); }
:divs w_rm32_00_02,imm32 is w_op_08_15=0b1011 & w_op_04_07=0b1110 & w_op_03=0b1 & w_rm32_00_02 ; imm32 { divs(w_rm32_00_02,imm32:4); }
:link w_rm32_00_02,imm16 is w_op_08_15=0x0c & w_op_04_07=0b1110 & w_op_03=0b1 & w_rm32_00_02 ; imm16 { link(w_rm32_00_02, imm16); }
:unlk w_rm32_00_02 is w_op_08_15=0x0d & w_op_04_07=0b1110 & w_op_03=0b1 & w_rm32_00_02 { unlk(w_rm32_00_02); }
:bs1f A,w_rm16_00_02 is w_op_08_15=0x0e & A & w_op_04_07=0b1101 & w_op_03=0b1 & w_rm16_00_02 { bs1f(A,w_rm16_00_02); }
:bs1b A,w_rm16_00_02 is w_op_08_15=0x0f & A & w_op_04_07=0b1101 & w_op_03=0b1 & w_rm16_00_02 { bs1b(A,w_rm16_00_02); }
:daa w_rm8_00_02 is w_op_08_15=0x10 & w_op_04_07=0b1100 & w_op_03=0b1 & w_rm8_00_02 { daa(w_rm8_00_02); }
:extz w_rm16_00_02 is w_op_08_15=0x12 & w_op_04_07=0b1101 & w_op_03=0b1 & w_rm16_00_02 { extz16(w_rm16_00_02); }
:extz w_rm32_00_02 is w_op_08_15=0x12 & w_op_04_07=0b1110 & w_op_03=0b1 & w_rm32_00_02 { extz32(w_rm32_00_02); }
:exts w_rm16_00_02 is w_op_08_15=0x13 & w_op_04_07=0b1101 & w_op_03=0b1 & w_rm16_00_02 { exts16(w_rm16_00_02); }
:exts w_rm32_00_02 is w_op_08_15=0x13 & w_op_04_07=0b1110 & w_op_03=0b1 & w_rm32_00_02 { exts32(w_rm32_00_02); }
:paa w_rm16_00_02 is w_op_08_15=0x14 & w_op_04_07=0b1101 & w_op_03=0b1 & w_rm16_00_02 { paa(w_rm16_00_02); }
:paa w_rm32_00_02 is w_op_08_15=0x14 & w_op_04_07=0b1110 & w_op_03=0b1 & w_rm32_00_02 { paa(w_rm32_00_02); }
:mirr w_rm16_00_02 is w_op_08_15=0x16 & w_op_04_07=0b1101 & w_op_03=0b1 & w_rm16_00_02 { mirr(w_rm16_00_02); }
:mula w_rm16_00_02 is w_op_08_15=0x19 & w_op_04_07=0b1101 & w_op_03=0b1 & w_rm16_00_02 { mula(w_rm16_00_02); }
:djnz w_rm8_00_02,rel8 is w_op_08_15=0x1c & w_op_04_07=0b1100 & w_op_03=0b1 & w_rm8_00_02 ; rel8 {
w_rm8_00_02 = w_rm8_00_02 - 1;