Options for increased maximum output power?

[invd]

Preface: I'm not an expert at high voltage electronics. Do not rely on any of the assumptions in this post. Do any modifications at your own risk.

Based on my understanding of the picoemp design, capacitor C3 stores about (0,47µF * (250V)^2)/2 = 14,69mJ of energy assuming a charge voltage of 250V, a part of which can be used for a discharge into the coil. In the introduction video, the measured charge voltage is about 239V and I've measured about 258V on my own unit, so 250V looks reasonable as a ballpark figure.

"Bigger" designs like the regular chipShouter, siliconToaster etc. allow higher capacitor voltages in the area of 500V-1200V at their highest settings which significantly benefits the energy storage through the quadratic component. It would probably be possible to tweak the picoemp to work at a higher voltage than 250V (for example 300-400V), but I'm very cautious about such a modification since this reduces the safety margin for breakdown voltages (IGBT, capacitor, ..) and physical board or probe tip clearances. It would be very unfortunate if boards have a catastrophic breakdown due to left-over solder paste, partially exposed traces, ringing with mismatched experimental probe tips or one of the many other failure modes for self-assembled boards.

So I have been wondering about the benefits or drawbacks of increasing just the size the capacitor "bank" at C3 by factor two to four. The standard picoemp design is clearly limited by the BOM cost and area/height under the plastic shield, so it is logical to me that "only" a single capacitor was chosen. (Also note that the Hammond 1551 enclosure has an additional plastic part in that corner of the board which needs to be stripped before that space is usable for high components).

@colinoflynn
Are you aware of any direct electrical drawbacks to doubling C3 by stacking an identical 2.5mm height capacitor on top (which could just fit the enclosure) for people who have used the thinner TDK CGA9P1X7T2J474K250KE per your BOM recommendations since Murata KRM55TR72J474MH01K wasn't available?
Alternatively, there appear to be a few capacitor candidates with nominal 1µF which are thin enough to fit under the shield (untested candidates: Kyocera AVX 2220CC105KAZ2A, Knowles Syfer 2220Y6300105KXTWS2 and its more expensive AEC-Q200 twin). Based on the datasheets, 1 to 1.2µF is the upper end of capacitors in this package size at 630V, so there may be capacitor design limitation drawbacks that I'm not aware of which motivate staying at the slightly more conservative 0.47µF choice.
With a custom 3D-printed shield and larger inner shield height, it looks possible to stack some more capacitors on C3 and go for the mentioned 4x capacitor increase.

Looking at the PCB layout, it may be possible to rotate the C3 component counter-clockwise and squeeze another 2220 footprint into the layout for optional used by people who want the additional BOM cost for higher capacity trade-off. It's probably going to be fairly close to the plastic shield mounting clearance, though. (Related idea: it looks like R2 and J3 could be swapped and J3 turned counter-clockwise to simplify the trace routing and increase distances. However, this takes more space along the shield and therefore works against adding another capacitor footprint).

From what I can tell, the recharge rate of the capacitor bank will not change with a size increase, so I expect the main effect to be a larger initial energy supply.

[colinoflynn]

A larger cap will slow down the recharge (the current design is already fairly low). However be aware that the limiting factor is almost always the coil you inject this into, and NOT the capacitive bank.

The ChipSHOUTER manual has a figure showing the maximum pulse width you see at the output showing this:

The problem is the core material saturates at some point (or I think that is the problem). Larger tips allow wider pulse widths. The main advantage of a larger bank is faster repeats (no recharge time needed), but this significantly complicates drive + cooling problems.

Generally though bigger is not always better (often it is worse), especially where there is no voltage control (as in PicoEMP). It makes the rest of your design more difficult & reduces reliability while increasing cost (you need a larger MOSFET which adds cost, then you need a much more complex gate drive since that MOSFET has a larger gate capacitance, etc etc).

Of course people are free to fork the design to try it out, one of the ideas of this! But I made the decision for PicoEMP to simplify it as much as possible (but not more) to reduce cost while still allow recreation of many results.