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class.rst

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5679 lines (3738 loc) · 223 KB

Session

Methods

abort

acquisition_status

auto_setup

close

commit

configure_chan_characteristics

configure_equalization_filter_coefficients

configure_horizontal_timing

configure_trigger_digital

configure_trigger_edge

configure_trigger_hysteresis

configure_trigger_immediate

configure_trigger_software

configure_trigger_video

configure_trigger_window

configure_vertical

disable

export_attribute_configuration_buffer

export_attribute_configuration_file

fetch

fetch_into

get_equalization_filter_coefficients

import_attribute_configuration_buffer

import_attribute_configuration_file

initiate

lock

probe_compensation_signal_start

probe_compensation_signal_stop

read

reset

reset_device

reset_with_defaults

self_cal

self_test

send_software_trigger_edge

unlock

Properties

absolute_sample_clock_offset

acquisition_start_time

acquisition_type

acq_arm_source

adv_trig_src

allow_more_records_than_memory

arm_ref_trig_src

backlog

bandpass_filter_enabled

binary_sample_width

cable_sense_mode

cable_sense_signal_enable

cable_sense_voltage

channel_count

channel_enabled

channel_terminal_configuration

data_transfer_block_size

data_transfer_maximum_bandwidth

data_transfer_preferred_packet_size

device_temperature

enabled_channels

enable_dc_restore

enable_time_interleaved_sampling

end_of_acquisition_event_output_terminal

end_of_record_event_output_terminal

end_of_record_to_advance_trigger_holdoff

equalization_filter_enabled

equalization_num_coefficients

exported_advance_trigger_output_terminal

exported_ref_trigger_output_terminal

exported_start_trigger_output_terminal

flex_fir_antialias_filter_type

fpga_bitfile_path

glitch_condition

glitch_polarity

glitch_width

high_pass_filter_frequency

horz_enforce_realtime

horz_min_num_pts

horz_num_records

horz_record_length

horz_record_ref_position

horz_sample_rate

horz_time_per_record

input_clock_source

input_impedance

instrument_firmware_revision

instrument_manufacturer

instrument_model

interleaving_offset_correction_enabled

io_resource_descriptor

is_probe_comp_on

logical_name

master_enable

max_input_frequency

max_real_time_sampling_rate

max_ris_rate

min_sample_rate

onboard_memory_size

output_clock_source

pll_lock_status

points_done

poll_interval

probe_attenuation

ready_for_advance_event_output_terminal

ready_for_ref_event_output_terminal

ready_for_start_event_output_terminal

records_done

record_arm_source

ref_clk_rate

ref_trigger_detector_location

ref_trigger_minimum_quiet_time

ref_trig_tdc_enable

resolution

ris_in_auto_setup_enable

ris_method

ris_num_averages

runt_high_threshold

runt_low_threshold

runt_polarity

runt_time_condition

runt_time_high_limit

runt_time_low_limit

sample_mode

samp_clk_timebase_div

sample_clock_timebase_multiplier

samp_clk_timebase_rate

samp_clk_timebase_src

serial_number

accessory_gain

accessory_offset

simulate

specific_driver_description

specific_driver_revision

specific_driver_vendor

start_to_ref_trigger_holdoff

supported_instrument_models

trigger_auto_triggered

trigger_coupling

trigger_delay_time

trigger_holdoff

trigger_hysteresis

trigger_impedance

trigger_level

trigger_modifier

trigger_slope

trigger_source

trigger_type

trigger_window_high_level

trigger_window_low_level

trigger_window_mode

tv_trigger_event

tv_trigger_line_number

tv_trigger_polarity

tv_trigger_signal_format

use_spec_initial_x

vertical_coupling

vertical_offset

vertical_range

width_condition

width_high_threshold

width_low_threshold

width_polarity

NI-TClk Support

Session