Enums used in NI-FGEN
.. py:currentmodule:: nifgen
.. py:class:: AnalogPath
.. py:attribute:: AnalogPath.MAIN
Specifies use of the main path. NI-FGEN chooses the amplifier based on the user-specified gain.
.. py:attribute:: AnalogPath.DIRECT
Specifies use of the direct path.
.. py:attribute:: AnalogPath.FIXED_LOW_GAIN
Specifies use of the low-gain amplifier in the main path, no matter what value the user specifies for gain. This setting limits the output range.
.. py:attribute:: AnalogPath.FIXED_HIGH_GAIN
Specifies use of the high-gain amplifier in the main path.
.. py:class:: BusType
.. py:attribute:: BusType.INVALID
Indicates an invalid bus type.
.. py:attribute:: BusType.AT
Indicates the signal generator is the AT bus type.
.. py:attribute:: BusType.PCI
Indicates the signal generator is the PCI bus type.
.. py:attribute:: BusType.PXI
Indicates the signal generator is the PXI bus type.
.. py:attribute:: BusType.VXI
Indicates the signal generator is the VXI bus type.
.. py:attribute:: BusType.PCMCIA
Indicates the signal generator is the PCI-CMA bus type.
.. py:attribute:: BusType.PXIE
Indicates the signal generator is the PXI Express bus type.
.. py:class:: ByteOrder
.. py:attribute:: ByteOrder.LITTLE
.. py:attribute:: ByteOrder.BIG
.. py:class:: ClockMode
.. py:attribute:: ClockMode.HIGH_RESOLUTION
High resolution sampling—Sample rate is generated by a high–resolution clock source.
.. py:attribute:: ClockMode.DIVIDE_DOWN
Divide down sampling—Sample rates are generated by dividing the source frequency.
.. py:attribute:: ClockMode.AUTOMATIC
Automatic Selection—NI-FGEN selects between the divide–down and high–resolution clocking modes.
.. py:class:: DataMarkerEventLevelPolarity
.. py:attribute:: DataMarkerEventLevelPolarity.HIGH
When the operation is ready to start, the Ready for Start event level is high.
.. py:attribute:: DataMarkerEventLevelPolarity.LOW
When the operation is ready to start, the Ready for Start event level is low.
.. py:class:: HardwareState
.. py:attribute:: HardwareState.IDLE
.. py:attribute:: HardwareState.WAITING_FOR_START_TRIGGER
.. py:attribute:: HardwareState.RUNNING
.. py:attribute:: HardwareState.DONE
.. py:attribute:: HardwareState.HARDWARE_ERROR
.. py:class:: IdleBehavior
.. py:attribute:: IdleBehavior.HOLD_LAST
While in an Idle or Wait state, the output signal remains at the last voltage generated prior to entering the state.
.. py:attribute:: IdleBehavior.JUMP_TO
While in an Idle or Wait state, the output signal remains at the value configured in the Idle or Wait value property.
.. py:class:: OutputMode
.. py:attribute:: OutputMode.FUNC
Standard Method mode— Generates standard method waveforms such as sine, square, triangle, and so on.
.. py:attribute:: OutputMode.ARB
Arbitrary waveform mode—Generates waveforms from user-created/provided waveform arrays of numeric data.
.. py:attribute:: OutputMode.SEQ
Arbitrary sequence mode — Generates downloaded waveforms in an order your specify.
.. py:attribute:: OutputMode.FREQ_LIST
Frequency List mode—Generates a standard method using a list of frequencies you define.
.. py:attribute:: OutputMode.SCRIPT
**Script mode—**\ Allows you to use scripting to link and loop multiple
waveforms in complex combinations.
.. py:class:: ReferenceClockSource
.. py:attribute:: ReferenceClockSource.CLOCK_IN
Specifies that the CLK IN input signal from the front panel connector is
used as the Reference Clock source.
.. py:attribute:: ReferenceClockSource.NONE
Specifies that a Reference Clock is not used.
.. py:attribute:: ReferenceClockSource.ONBOARD_REFERENCE_CLOCK
Specifies that the onboard Reference Clock is used as the Reference
Clock source.
.. py:attribute:: ReferenceClockSource.PXI_CLOCK
Specifies that the PXI Clock is used as the Reference Clock source.
.. py:attribute:: ReferenceClockSource.RTSI_7
Specifies that the RTSI line 7 is used as the Reference Clock source.
.. py:class:: RelativeTo
.. py:attribute:: RelativeTo.START
.. py:attribute:: RelativeTo.CURRENT
.. py:class:: SampleClockSource
.. py:attribute:: SampleClockSource.CLOCK_IN
Specifies that the signal at the CLK IN front panel connector is used as
the Sample Clock source.
.. py:attribute:: SampleClockSource.DDC_CLOCK_IN
Specifies that the Sample Clock from the DDC connector is used as the Sample
Clock source.
.. py:attribute:: SampleClockSource.ONBOARD_CLOCK
Specifies that the onboard clock is used as the Sample Clock source.
.. py:attribute:: SampleClockSource.PXI_STAR_LINE
Specifies that the PXI\_STAR trigger line is used as the Sample Clock
source.
.. py:attribute:: SampleClockSource.PXI_TRIGGER_LINE_0_RTSI_0
Specifies that the PXI or RTSI line 0 is used as the Sample Clock
source.
.. py:attribute:: SampleClockSource.PXI_TRIGGER_LINE_1_RTSI_1
Specifies that the PXI or RTSI line 1 is used as the Sample Clock
source.
.. py:attribute:: SampleClockSource.PXI_TRIGGER_LINE_2_RTSI_2
Specifies that the PXI or RTSI line 2 is used as the Sample Clock
source.
.. py:attribute:: SampleClockSource.PXI_TRIGGER_LINE_3_RTSI_3
Specifies that the PXI or RTSI line 3 is used as the Sample Clock
source.
.. py:attribute:: SampleClockSource.PXI_TRIGGER_LINE_4_RTSI_4
Specifies that the PXI or RTSI line 4 is used as the Sample Clock
source.
.. py:attribute:: SampleClockSource.PXI_TRIGGER_LINE_5_RTSI_5
Specifies that the PXI or RTSI line 5 is used as the Sample Clock
source.
.. py:attribute:: SampleClockSource.PXI_TRIGGER_LINE_6_RTSI_6
Specifies that the PXI or RTSI line 6 is used as the Sample Clock
source.
.. py:attribute:: SampleClockSource.PXI_TRIGGER_LINE_7_RTSI_7
Specifies that the PXI or RTSI line 7 is used as the Sample Clock
source.
.. py:class:: SampleClockTimebaseSource
.. py:attribute:: SampleClockTimebaseSource.CLOCK_IN
Specifies that the external signal on the CLK IN front panel connector
is used as the source.
.. py:attribute:: SampleClockTimebaseSource.ONBOARD_CLOCK
Specifies that the onboard Sample Clock timebase is used as the source.
.. py:class:: ScriptTriggerDigitalEdgeEdge
.. py:attribute:: ScriptTriggerDigitalEdgeEdge.RISING
Rising Edge
.. py:attribute:: ScriptTriggerDigitalEdgeEdge.FALLING
Falling Edge
.. py:class:: ScriptTriggerType
.. py:attribute:: ScriptTriggerType.TRIG_NONE
No trigger is configured. Signal generation starts immediately.
.. py:attribute:: ScriptTriggerType.DIGITAL_EDGE
Trigger is asserted when a digital edge is detected.
.. py:attribute:: ScriptTriggerType.DIGITAL_LEVEL
Trigger is asserted when a digital level is detected.
.. py:attribute:: ScriptTriggerType.SOFTWARE_EDGE
Trigger is asserted when a software edge is detected.
.. py:class:: StartTriggerDigitalEdgeEdge
.. py:attribute:: StartTriggerDigitalEdgeEdge.RISING
Rising Edge
.. py:attribute:: StartTriggerDigitalEdgeEdge.FALLING
Falling Edge
.. py:class:: StartTriggerType
.. py:attribute:: StartTriggerType.TRIG_NONE
None
.. py:attribute:: StartTriggerType.DIGITAL_EDGE
Digital Edge
.. py:attribute:: StartTriggerType.SOFTWARE_EDGE
Software Edge
.. py:attribute:: StartTriggerType.P2P_ENDPOINT_FULLNESS
P2P Endpoint Fullness
.. py:class:: TerminalConfiguration
.. py:attribute:: TerminalConfiguration.SINGLE_ENDED
Single-ended operation
.. py:attribute:: TerminalConfiguration.DIFFERENTIAL
Differential operation
.. py:class:: Trigger
.. py:attribute:: Trigger.START
.. py:attribute:: Trigger.SCRIPT
.. py:class:: TriggerMode
.. py:attribute:: TriggerMode.SINGLE
Single Trigger Mode - The waveform you describe in the sequence list is generated only once by going through the entire staging list. Only one trigger is required to start the waveform generation. You can use Single trigger mode with the output mode in any mode. After a trigger is received, the waveform generation starts from the first stage and continues through to the last stage. Then, the last stage generates repeatedly until you stop the waveform generation.
.. py:attribute:: TriggerMode.CONTINUOUS
Continuous Trigger Mode - The waveform you describe in the staging list generates infinitely by repeatedly cycling through the staging list. After a trigger is received, the waveform generation starts from the first stage and continues through to the last stage. After the last stage completes, the waveform generation loops back to the start of the first stage and continues until it is stopped. Only one trigger is required to start the waveform generation.
.. py:attribute:: TriggerMode.STEPPED
Stepped Trigger Mode - After a start trigger is received, the waveform described by the first stage generates. Then, the device waits for the next trigger signal. On the next trigger, the waveform described by the second stage generates, and so on. After the staging list completes, the waveform generation returns to the first stage and continues in a cyclic fashion. After any stage has generated completely, the first eight samples of the next stage are repeated continuously until the next trigger is received.
trigger mode.
.. note:: In Frequency List mode, Stepped trigger mode is the same as Burst
.. py:attribute:: TriggerMode.BURST
Burst Trigger Mode - After a start trigger is received, the waveform described by the first stage generates until another trigger is received. At the next trigger, the buffer of the previous stage completes, and then the waveform described by the second stage generates. After the staging list completes, the waveform generation returns to the first stage and continues in a cyclic fashion. In Frequency List mode, the duration instruction is ignored, and the trigger switches the frequency to the next frequency in the list.
trigger mode.
.. note:: In Frequency List mode, Stepped trigger mode is the same as Burst
.. py:class:: WaitBehavior
.. py:attribute:: WaitBehavior.HOLD_LAST
While in an Idle or Wait state, the output signal remains at the last voltage generated prior to entering the state.
.. py:attribute:: WaitBehavior.JUMP_TO
While in an Idle or Wait state, the output signal remains at the value configured in the Idle or Wait value property.
.. py:class:: Waveform
.. py:attribute:: Waveform.SINE
Sinusoid waveform
.. py:attribute:: Waveform.SQUARE
Square waveform
.. py:attribute:: Waveform.TRIANGLE
Triange waveform
.. py:attribute:: Waveform.RAMP_UP
Positive ramp waveform
.. py:attribute:: Waveform.RAMP_DOWN
Negative ramp waveform
.. py:attribute:: Waveform.DC
Constant voltage
.. py:attribute:: Waveform.NOISE
White noise
.. py:attribute:: Waveform.USER
User-defined waveform as defined by the :py:meth:`nifgen.Session.define_user_standard_waveform` method.