WIP serial logging. HIL test setup

.circleci/config.yml

@@ -7,10 +7,19 @@ jobs:
     steps:
       - checkout
 
+      - restore_cache:
+          key: project-cache
+
       - run:
-          name: Add embedded target
-          command: rustup target add thumbv7em-none-eabihf
+          name: Prepare build
+          command: make rustup
 
       - run:
           name: Build the firmware
-          command: cargo build --release
+          command: make build
+
+      - save_cache:
+          key: project-cache
+          paths:
+            - "~/.cargo"
+            - "./target"

.envrc

@@ -0,0 +1,2 @@
+# to use this, install [direnv](https://direnv.net/)
+source venv/bin/activate

.gitignore

@@ -1,5 +1,7 @@
 /target
 **/*.rs.bk
+**/*.py[cod]
 Cargo.lock
 .gdb_history
 openocd.log
+/venv

70-zissou.rules

@@ -0,0 +1,2 @@
+SUBSYSTEM=="hidraw", ATTRS{idVendor}=="1209", ATTRS{idProduct}=="cc1d", TAG+="uaccess", SYMLINK += "zissou"
+SUBSYSTEM=="tty", ATTRS{idVendor}=="1209", ATTRS{idProduct}=="cc1d", TAG+="uaccess", SYMLINK += "zissouserial"

Cargo.toml

@@ -23,9 +23,12 @@ members = [
 ]
 
 [dependencies]
-cortex-m = "0.5.8"
+cortex-m = "0.6.0"
 cortex-m-rt = "0.6.8"
+nb = "0.1.2"
 panic-halt = "0.2.0"
+ufmt = "0.1.0-beta.4"
+ufmt-write = "0.1.0-beta.1"
 
 [dependencies.stm32l4xx-hal]
 path = "./stm32l4xx-hal"

Makefile

@@ -1,19 +1,21 @@
 GDB ?= arm-none-eabi-gdb
 TARGET ?= thumbv7em-none-eabihf
-ZISSOU ?= target/$(TARGET)/release/zissou
-
+TOOLCHAIN ?= nightly  # ufmt's `uwrite!` needs nightly :/
+# TOOLCHAIN ?= stable
 
+ZISSOU ?= target/$(TARGET)/release/zissou
 zissou $(ZISSOU): build
 
 
 bloat: build
-	cargo bloat $(BLOAT_ARGS) -n 50 --target $(TARGET)
+	cargo +nightly bloat $(BLOAT_ARGS) -n 50 --release
 
 build:
-	rustup install stable
-	rustup component add --toolchain stable llvm-tools-preview
-	rustup target add --toolchain stable $(TARGET)
-	cargo +stable build --release
+	# rustup install stable
+	# rustup component add --toolchain stable llvm-tools-preview
+	# rustup target add --toolchain stable $(TARGET)
+	# touch build.rs  # force reloading git-describe
+	cargo +$(TOOLCHAIN) build --release
 
 clean:
 	cargo clean
@@ -22,7 +24,11 @@ clean:
 # 	rustup component add clippy
 # 	cargo clippy
 
-flash:  $(ZISSOU)
+# slightly faster than `flash-gdb`
+flash flash-openocd: $(ZISSOU)
+	openocd -f openocd.cfg -c "init; targets; reset halt; program $(ZISSOU) verify reset exit"
+
+flash-gdb: $(ZISSOU)
 	$(GDB) -q -x flash.gdb $(ZISSOU)
 
 fmt:
@@ -33,11 +39,36 @@ fmt:
 openocd:
 	openocd
 
+hil:
+	pytest --quiet
+
 # NB: needs separate OpenOCD running
 run: build
-	cargo +stable run --release
+	cargo +$(TOOLCHAIN) run --release
+
+rustup:
+	rustup install $(TOOLCHAIN)
+	rustup component add --toolchain $(TOOLCHAIN) llvm-tools-preview
+	rustup target add --toolchain $(TOOLCHAIN) $(TARGET)
 
 size: build
-	cargo size --bin zissou --release
+	cargo +$(TOOLCHAIN) size --bin zissou --release
+
+tail-zissouserial:
+	scripts/tail-zissouserial
+
+udev:
+	sudo cp 70-zissou.rules /etc/udev/rules.d
+	sudo udevadm control --reload-rules
+	sudo udevadm trigger
 
+venv:
+	python3 -m venv venv
+	venv/bin/pip install -U pip
+	venv/bin/pip install -U -r requirements.txt
 
+# re-run if dev or runtime dependencies change,
+# or when adding new scripts
+update-venv: venv
+	venv/bin/pip install -U pip
+	venv/bin/pip install -U -r requirements.txt

hil-tests/README.md

@@ -0,0 +1,8 @@
+# HIL Tests
+
+These tests are driven from root directory with `make hil`.
+
+The assumption is that a NUCLEO-L432KC is connected via USB adapter,
+with (Nucleo -> USB): PA12/D2 -> D+, PA11/D10 -> D- and GND -> GND.
+
+cf. https://jamesmunns.com/blog/hardware-ci-overview/

hil-tests/test_serial.py

@@ -0,0 +1,23 @@
+import pytest
+import serial as pyserial
+
+
+@pytest.fixture
+def serial():
+    """The serial interface to Zissou."""
+
+    # N.B. Everything after the yield is teardown
+    with pyserial.Serial("/dev/zissouserial") as s:
+        yield s
+
+
+def test_loopback(serial):
+    """Current behaviour - will change."""
+
+    test_str = "Hello!"
+
+    sent = serial.write(test_str.encode())
+    assert sent == len(test_str)
+
+    read = serial.read_all()
+    assert read.decode() == test_str.upper()

openocd.cfg

@@ -1,5 +1,8 @@
-telnet_port disabled    
-tcl_port disabled   
+# the stlink.cfg is supported in openocd-git only
+# it seems openocd gave up on making proper releases
+
+telnet_port disabled
+tcl_port disabled
 source [find interface/stlink.cfg]
 source [find target/stm32l4x.cfg]
 targets

openocd.gdb

@@ -4,13 +4,13 @@ target extended-remote :3333
 set print asm-demangle on
 monitor arm semihosting enable
 
-break DefaultHandler                            
-break HardFault                                            
-break rust_begin_unwind  
+break DefaultHandler
+break HardFault
+break rust_begin_unwind
 
 # reset halt
 load
 # monitor verify
 # monitor reset
 # quit
-continue
+#continue

pytest.ini

@@ -0,0 +1,2 @@
+[pytest]
+testpaths = hil-tests

requirements.txt

@@ -0,0 +1,3 @@
+pyserial >=3.4
+pytest >=4.5.0
+pyusb >=1.0.2

scripts/tail-zissouserial

@@ -0,0 +1,10 @@
+#!/bin/bash
+
+# BAUD=115200
+WHAT=/dev/zissouserial
+
+while true
+do
+    # stty -F ${WHAT} ${BAUD}  # cdc-acm impl doesn't handle this properly
+    cat ${WHAT} 2>/dev/null
+done

src/main.rs

@@ -1,6 +1,9 @@
 #![no_std]
 #![no_main]
+#![feature(proc_macro_hygiene)]
 
+// use core::fmt;
+use ufmt::uwrite;
 extern crate panic_halt;
 use cortex_m_rt::entry;
 
@@ -16,8 +19,24 @@ mod usb;
 static GIT_DESCRIBE: &'static str = env!("GIT_DESCRIBE");
 static CCID_PRODUCT: &'static str = concat!("Zissou v", env!("GIT_DESCRIBE"));
 
+// macro_rules! uprint {
+//     ($serial:expr, $($arg:tt)*) => {
+//         fmt::write($serial, format_args!($($arg)*)).ok()
+//     };
+// }
+
+// macro_rules! uprintln {
+//     ($serial:expr, $fmt:expr) => {
+//         uprint!($serial, concat!($fmt, "\n"))
+//     };
+//     ($serial:expr, $fmt:expr, $($arg:tt)*) => {
+//         uprint!($serial, concat!($fmt, "\n"), $($arg)*)
+//     };
+// }
+
 #[entry]
 fn main() -> ! {
+    let cp = hal::cortex_m::Peripherals::take().unwrap();
     let dp = hal::device::Peripherals::take().unwrap();
 
     // let mut flash = dp.FLASH.constrain();
@@ -48,7 +67,7 @@ fn main() -> ! {
     );
 
     let mut smartcard = usb::ccid::SmartCard::new(&usb_bus);
-    // let mut serial = cdc_acm::SerialPort::new(&usb_bus);
+    let mut serial = usb::cdc_acm::SerialPort::new(&usb_bus);
 
     // vid/pid: http://pid.codes/1209/CC1D/
     let mut usb_dev = UsbDeviceBuilder::new(&usb_bus, UsbVidPid(0x1209, 0xcc1d))
@@ -57,27 +76,69 @@ fn main() -> ! {
         .serial_number("N/a")
         .build();
 
+    // "ensures that the host re-enumerates your device after a new program has been flashed."
     // usb_dev.force_reset().expect("reset failed");
 
     let mut buf = [0u8; 64];
+    let mut i: u32 = 0;
+
+    // let mut nvic = cp.NVIC;
+    // nvic.enable(hal::stm32::Interrupt::TIM7);
+    let mut timer = hal::timer::Timer::tim7(dp.TIM7, 1.hz(), clocks, &mut rcc.apb1r1);
+    // timer.start(1000.ms());
+
+    // timer.start(heartbeat_timeout);  // <- use a periodic one
     loop {
-        // if !usb_dev.poll(&mut [&mut smartcard, &mut serial]) {
-        if !usb_dev.poll(&mut [&mut smartcard]) {
+		// serial.write(b"heartbeat\n").ok();
+        // if i % 10240 == 0 {
+            // uprintln!(&mut serial, "hello {}1!", i);
+            // uprintln!(&mut serial, "{}", i);
+            // uwrite!(&mut serial, "hello {} hello\r\n", i).unwrap();
+        // if i % 2 == 0 {
+            // uwrite!(&mut serial, "hello! {}\n", i).unwrap();
+        // } else {
+            // uwrite!(&mut serial, "elloh\n").unwrap();
+        // }
+            // serial.write(&[]).ok();
+        // }
+        // i += 1;
+        if !usb_dev.poll(&mut [&mut smartcard, &mut serial]) {
             continue;
         }
 
-        // match serial.read(&mut buf) {
-        //     Ok(count) if count > 0 => {
-        //         // Echo back in upper case
-        //         for c in buf[0..count].iter_mut() {
-        //             if 0x61 <= *c && *c <= 0x7a {
-        //                 *c &= !0x20;
-        //             }
-        //         }
+        match serial.read(&mut buf) {
+            Ok(count) if count > 0 => {
+                // Echo back in upper case
+                for c in buf[0..count].iter_mut() {
+                    if 0x61 <= *c && *c <= 0x7a {
+                        *c &= !0x20;
+                    }
+                }
+
+                serial.write(&buf[0..count]).ok();
+                // uwrite!(&mut serial, "{}\n", i).unwrap();
+            },
+            _ => { },
+        }
 
-        //         serial.write(&buf[0..count]).ok();
+        // match timer.wait() {
+        //     Err(nb::Error::Other(e)) => {
+        //         // The error type specified by `timer.wait()` is `!`, which
+        //         // means no error can actually occur. The Rust compiler
+        //         // still forces us to provide this match arm, though.
+        //         unreachable!()
         //     },
-        //     _ => { },
+        //     // no timeout yet, try again
+        //     Err(nb::Error::WouldBlock) => continue,
+        //     // Ok(()) => return Err(Error::TimedOut),
+        //     Ok(()) => {
+        //         uwrite!(&mut serial, "hello! {}\n", i).unwrap();
+        //         // timer.start(1.hz());
+        //         i += 1;
+        //         // send heartbeat via VCOM
+        //         // set new heartbeat timer  <-- not necessary for Periodic timers
+        //     }
         // }
+
     }
 }