Using tool directives with '`' instead of '#'

[Paebbels]

The VHDL standard (IEEE Std. 1076-20**) has tool directives in clause 24. You could use the '`' character instead of '#' and be compliant with the VHDL standard. Moreover, in IEEE Std 1076-2019, a new feature called conditional analysis was added. See Clause 24.2 for more details.

This is the an EBNF based summary:

More details can be found here: http://www.eda-twiki.org/cgi-bin/view.cgi/P1076/LCS2016_061

[nobodywasishere]

I've made substantial updates to VHDLproc recently, including changing the default directive character to '`', and rewriting it in Python from scratch. Overall I think it's much easier to modify and work with than before.

This could fit in with what's being discussed in your link, except I would have to add a lot more functionality for conditional analysis per the LRM. Currently this really only supports C-style preprocessor directives that are on their own line (or indented with spaces), and doesn't support macros with parameters or ifs with conditionals. I'll have to do more research into this. Thank you!

[nobodywasishere]

I've rewritten VHDLproc from scratch on a new branch here. Overall this is a much better implementation of a preprocessor than what I had before. It also matches up with (what I know about) the VHDL 2019 conditional analysis spec (except for `include, which isn't in said spec).

I'd be interested in your thoughts on this. As this is also now implemented as a Python class with a CLI wrapper, other programs should be able to leverage the class directly as well.

[Paebbels]

This sounds very good.

Tool directives are like attributes. The LRM defines a syntax and some pre-existing directives, but there is a big open space for vendor/tool freedom. The LRM also limits the uncontrolled creation of special characters and start sequences in comments by adding a designated syntax for vendor extensions. Moreover it keeps comments clean and avoids pragmas.

So if you want to have your own extensions like

`include some/file.vhdl

it's covered by the standard and not illegal syntax.

---

/cc @umarcor

[Paebbels]

It looks like:

`define LABEL           -   Define LABEL for `ifdef and `ifndef

`define LABEL STRING    -   Replace LABEL by STRING, can be multiple words
                            Will replace ignoring single quotes and attributes ('', ')
                            Will not replace within double quotes ("")

`rand LABEL FORMAT      -   Replace LABEL by generated random characters
                            according to FORMAT. FORMAT has an alphabet
                            for radix and a digit number for generating,
                            The radix character can be set by 'B'(bin),
                            'D'(dec), 'H'(hex) and 'A'(alphabet)

are not supported anymore?
(According to the README on the rewrite branch.)

[nobodywasishere]

This sounds very good.

Tool directives are like attributes. The LRM defines a syntax and some pre-existing directives, but there is a big open space for vendor/tool freedom. The LRM also limits the uncontrolled creation of special characters and start sequences in comments by adding a designated syntax for vendor extensions. Moreover it keeps comments clean and avoids pragmas.

So if you want to have your own extensions like

`include some/file.vhdl

it's covered by the standard and not illegal syntax.

/cc @ umarcor

Unfortunately I don't have access to the VHDL-2019 LRM (as I don't feel like dropping $$$ for a fun side project) so I've only been able to go off the site you originally linked (unless some of this stuff is in the 2008 LRM and I just missed it - which is possible as I'm still working my way through it). This is good to know, thank you!

It looks like:

...

are not supported anymore?
(According to the README on the rewrite branch.)

`define was originally meant for defining labels that were to replace parts of the VHDL code, though this could probably be added back (without the ability to replace parts of the actual code, only for conditional compilation). `rand is almost useless with conditional compilation only, hence why it was removed.

[Paebbels]

Did you know, Verilog uses also backtick for tool directives? They have not defined such if...then...else structures, but we could invent a Verilog like syntax pretty easy.

It would be possible to call your tool vpp as in VHDL/Verilog Pre-Processor.

---

/cc @umarcor

[nobodywasishere]

As far as I know Verilog does have predefined preprocessor directives, though I think they call them compiler directives. See here. I know Yosys supports them already. It would be pretty easy just to have a switch to swap out the VHDL directive syntax for Verilog, but some of the compiler directives for Verilog seem like they should be handled by the 'compiler' instead.

vpp as a name has already been taken actually (see here and here, the latter actually being the project I forked to create this one, two rewrites ago). I changed the name after it moved away from the original source code.

[nobodywasishere]

I just officially released v2.0, which supports VHDL-2019 directives. It's also now on pypi. I do consider this issue 'resolved' now, so I'm going to close it, but we can keep discussions going here. Thank you for the support!