/
d05.cpu01.asm
2313 lines (2312 loc) · 149 KB
/
d05.cpu01.asm
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d05.cpu_tile255: .defchr $4000, $0,\
$88111111,\
$86111111,\
$84111115,\
$71111118,\
$41111112,\
$11111111,\
$11111111,\
$11111111
d05.cpu_tile256: .defchr $4000, $0,\
$38711116,\
$78611115,\
$88611111,\
$87111111,\
$31111111,\
$11111111,\
$11111754,\
$11112888
d05.cpu_tile257: .defchr $4000, $0,\
$88752111,\
$88888111,\
$78888211,\
$15663111,\
$11111111,\
$11111114,\
$33335688,\
$88888888
d05.cpu_tile258: .defchr $4000, $0,\
$11151111,\
$11151111,\
$11221111,\
$11711111,\
$16863456,\
$88888888,\
$88888888,\
$88888888
d05.cpu_tile259: .defchr $4000, $0,\
$11148821,\
$11116884,\
$11128888,\
$12588888,\
$88888888,\
$88888888,\
$88888888,\
$88888888
d05.cpu_tile260: .defchr $4000, $0,\
$11111148,\
$12457888,\
$88888888,\
$88888888,\
$88888888,\
$88888888,\
$88888888,\
$88888888
d05.cpu_tile261: .defchr $4000, $0,\
$88888888,\
$88888888,\
$88888888,\
$88888088,\
$88880008,\
$88800000,\
$88000000,\
$88000000
d05.cpu_tile262: .defchr $4000, $0,\
$88888888,\
$88888888,\
$88888888,\
$88888888,\
$88888888,\
$88888888,\
$00888888,\
$00000800
d05.cpu_tile263: .defchr $4000, $0,\
$88888888,\
$88888888,\
$88888888,\
$88800888,\
$88888888,\
$88800000,\
$88800000,\
$80000000
d05.cpu_tile264: .defchr $4000, $0,\
$88888888,\
$88888888,\
$88888888,\
$88888888,\
$88888888,\
$00000008,\
$00000000,\
$00000000
d05.cpu_tile265: .defchr $4000, $0,\
$88888888,\
$88888888,\
$88088880,\
$80000000,\
$80000000,\
$00000000,\
$00000000,\
$00000000
d05.cpu_tile266: .defchr $4000, $0,\
$80000000,\
$80000000,\
$88000000,\
$00000000,\
$00000000,\
$00000000,\
$00000000,\
$00000000
d05.cpu_tile267: .defchr $4000, $0,\
$00000008,\
$00000000,\
$00000000,\
$00000000,\
$00000008,\
$00000008,\
$00000008,\
$00000000
d05.cpu_tile268: .defchr $4000, $0,\
$88888888,\
$88888888,\
$88888888,\
$88888884,\
$88888885,\
$88888888,\
$88888888,\
$80888888
d05.cpu_tile269: .defchr $4000, $0,\
$88611111,\
$88611111,\
$65211111,\
$11111111,\
$11111235,\
$88888888,\
$88888888,\
$88888888
d05.cpu_tile270: .defchr $4000, $0,\
$11133311,\
$11111111,\
$11111135,\
$11358888,\
$68888888,\
$88888888,\
$88888888,\
$88888888
d05.cpu_tile271: .defchr $4000, $0,\
$11111113,\
$11245788,\
$68888888,\
$88888888,\
$88888888,\
$88888888,\
$88888888,\
$88888888
d05.cpu_tile272: .defchr $4000, $0,\
$43116888,\
$88568888,\
$88888888,\
$88888888,\
$88888888,\
$88888888,\
$88888008,\
$88888888
d05.cpu_tile273: .defchr $4000, $0,\
$88888888,\
$88888888,\
$88888888,\
$88888888,\
$88888880,\
$88888888,\
$88888800,\
$88880000
d05.cpu_tile274: .defchr $4000, $0,\
$88888888,\
$88888888,\
$88888888,\
$88888000,\
$08080000,\
$80000000,\
$00000000,\
$00000000
d05.cpu_tile275: .defchr $4000, $0,\
$88888888,\
$88888888,\
$88888888,\
$88088800,\
$00000000,\
$00000000,\
$00000000,\
$00000000
d05.cpu_tile276: .defchr $4000, $0,\
$88888888,\
$88008888,\
$88000000,\
$00000000,\
$00000000,\
$00000000,\
$00000000,\
$00000000
d05.cpu_tile277: .defchr $4000, $0,\
$80000000,\
$08000000,\
$00000000,\
$00000000,\
$00000000,\
$00000000,\
$00000000,\
$00000000
d05.cpu_tile278: .defchr $4000, $0,\
$88888888,\
$88888888,\
$88888888,\
$00000808,\
$00000008,\
$00000000,\
$00000000,\
$00000000
d05.cpu_tile279: .defchr $4000, $0,\
$88888888,\
$88888888,\
$88888888,\
$88888888,\
$88888888,\
$00880800,\
$00080000,\
$00000000
d05.cpu_tile280: .defchr $4000, $0,\
$88888888,\
$88888888,\
$88888888,\
$88088088,\
$80000888,\
$00000088,\
$00000880,\
$00000000
d05.cpu_tile281: .defchr $4000, $0,\
$88888888,\
$88888888,\
$88888888,\
$88808000,\
$88800000,\
$00000000,\
$00000000,\
$00000000
d05.cpu_tile282: .defchr $4000, $0,\
$80000000,\
$88000000,\
$80000000,\
$00000000,\
$00000000,\
$00000000,\
$00000000,\
$00000000
d05.cpu_tile283: .defchr $4000, $0,\
$80880000,\
$00000000,\
$00000000,\
$00000000,\
$00000000,\
$00000000,\
$00000000,\
$00000000
D05.CPU_TILES01_COUNT .equ 29
D05.CPU_TILES01_LENGTH .equ D05.CPU_TILES01_COUNT * TILE_SIZE
D05.CPU_TILES01_OFFSET .equ D05.CPU_TILES00_OFFSET + D05.CPU_TILES00_LENGTH
d05.cpu_bat: .dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 1)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 2)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 3)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 4)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 5)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 6)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 7)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 8)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 9)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 10)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 11)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 12)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 13)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 14)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 15)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 16)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 17)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 18)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 19)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 20)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 21)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 22)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 23)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 24)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 25)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 26)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 27)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 28)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 29)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 30)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 31)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 32)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 33)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 34)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 35)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 36)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 37)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 38)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 39)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 40)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 41)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 42)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 43)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 44)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 45)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 46)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 47)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 48)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 49)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 50)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 51)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 52)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 53)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 54)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 55)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 56)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 57)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 58)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 59)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 60)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 61)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 62)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 63)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 64)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 65)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 66)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 67)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 68)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 69)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 70)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 71)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 72)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 73)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 74)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 75)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 76)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 77)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 78)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 79)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 80)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 81)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 82)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 83)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 84)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 85)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 86)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 87)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 88)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 89)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 90)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 91)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 92)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 93)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 94)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 95)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 96)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 97)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 98)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)
.dw BATVAL(0, TILE_START + D05.CPU_TILES00_OFFSET + TILE_SIZE * 0)