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ChipKit.txt
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ChipKit.txt
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- Information specific to the chipKIT32 -
Pin to Panel/Strand mapping -
Each panel is ideally mapped to a physically contiguous 4
pins. Sequential Panels (A, B, C, D) are ideally mapped to contiguous
groups of pins (right to left).
-- Summary --
// Single HDI
J4: 8 pins (of 8) on top
J5: 8 pins (of 8) analog pins along bottom
J7: 5 pins (of 8) " " " "
// Dual HDI
J3: 14 pins (of 16) "top left"
J14: 12 pins (of 16) "top right"
J9: 12 pins (of 16) "big one...
J8: 9 pins (of 16) on right"
-- PIN AVAILABILITY w/ NETWORK SHIELD --
Pins 22-29 are on "J9" (the upper portion of the large socket on the right)
And map to:
22 T3CK/AC2TX/RC2
23 T4CK/AC2RX/RC3
[NO] 24 VBUS
25 USBID/RF3
[NO] 26 D-/RG3
[NO] 27 D+/RG2
[NO] 28 AERXERR/RG15
29 ECRX/SDA2/SDI2A/U2ARX/PMA4/CN9/RG7
30 PMD7/RE7
32 PMD5/RE5
34 PMD3/RE3
36 PMD1/RE1
31 PMD6/RE6
33 PMD4/RE4
35 PMD2/RE2
37 PMD0/RE0
Pins 8-13, 78-85 are on "J3" 16pin HDI
8 ETXD2/IC5/PMD12/RD12
9 OC4/RD3
10 OC5/PMWR/CN13/RD4
11 T5CK/SDI1/RC4
12 SCL2/RA2
13 SDA2/RA3
78 C2TX/ETXERR/PMD9/RG1
79 C2RX/PMD8/RG0
80 TRCLK/RA6
81 TRD3/RA7
82 TRD2/RG14
83 TRD1/RG12
84 TRD0/RG13
85 VREF-/CVREF0/AERXD2/PMA7/RA9
Pins 14-21 are on J4 (inline hdi)
21 AETXCLK/SCL1/INT3/RA14
20 AETXEN/SDA1/INT4/RA15
19 AETXD0/SS1A/U1BRX/U1ACTS/CN20/RD14
18 AETXD1/SCK1A/U1BTX/U1ARTS/CN21/RD15
17 SDA3A/SDI3A/U3ARX/PMA9/CN17/RF4
16 SCL3A/SDO3A/U3ATX/PMA8/CN18/RF5
15 AC1RX/SS3A/U3BRX/U3ACTS/RF12
14 AC1TX/SCK3A/U3BTX/U3ARTS/RF13
Pins 0-7 and 70-77 on J14 16pin IDE "top center"
[NO] 0 SDA1A/SDI1A/U1ARX/RF2 (pic52)
[NO] 1 SCL1A/SDO1A/U1ATX/RF8 (pic53)
2 AERXD0/INT1/RE8
3 SDO1/OC1/INT0/RD0
4 SOSCO/T1CK/CN0/RC14 (OK - when SOSCEN=FALSE default)
5 OC2/RD1
6 OC3/RD2
[NO] 7 AERXD1/INT2/RE9 // used to reset PHY on Network Shield
70 TMS/RA0
71 TCK/RA1
72 TDI/RA4
73 TDO/RA5
74 SS1/IC2/RD9
[NO] 75 SOSCI/CN1/RC13 // driven with 32.7khz from Network Shield
76 ETXD3/PMD13/CN19/RD13
77 ETXCLK/PMD15/CN16/RD7
J5, J7 (Analog "in") ports along the bottom
// J5
54 PGED1/AN0/CN2/RB0
55 PGEC1/AN1/CN3/RB1
56 AN2/C2IN-/CN4/RB2
57 AN3/C2IN+/CN5/RB3
58 AN4/C1IN-/CN6/RB4
59 AN5/C1IN+/VBUSON/CN7/RB5
60 PGEC2/AN6/OCFA/RB6
61 PGED2/AN7/RB7
// J7
62 AN8/C1OUT/RB8
63 AN9/C2OUT/RB9
64 AN10/CVREFOUT/PMA13/RB10
[NO] 65 AN11/EREXERR/AETXERR/PMA12/RB11 // FRXD0, FRXD1, FRXERR
[NO] 67 AN12/ERXD0/AECRS/PMA11/RB12
[NO] 66 AN13/ERXD1/AECOL/PMA10/RB13
68 AN14/ERXD2/AETXD3/PMALH/PMA1/RB14
69 AN15/ERXD3/AETXD2/OCFB/PMALL/PMA0/CN12/RB15
-- EXPLICITYLY EXCLUDED PINS --
Pins 7,40-53 are used by the Network Shield. Namely:
7 AERXD0/INT2/RE9/NRST
40 AN11/ERXERR/AETXERR/PMA12/RB11 ERXERR
41 AN13/ERXD1/AECOL/PMA10/RB13 ERXD1
42 AN12/ERXD0/AECRS/PMA11/RB12 ERXD0
43 ERXDV/AERXDV/ECRSDV/AECRSDV/SCL2A/SDO2A/UATX/PMA3/CN10/RG8/ECRSDV
45 C1RX/ETXD1/PMD11/RF0/ETXD1
46 C1TX/ETXD0/PMD10/RF1/ETXD0
47 ETXEN/PMD14/CN15/RD6/ETXEN
48 RTCC/EMDIO/AEMDIO/IC1/RD8/EMDIO
49 EMDC/AEMDC/IC4/PMCS1/PMA14/RD11 EMDC
53 ERXCLK/AERXCLK/EREFCLK/AEREFCLK/SS2A/U2BRX/U2ACTS/PMA2/CN11/RG9/EREFCLK
USB and CAN also use the following pins - but should be passed through when not in use:
USB:
27 USBD+/RG2 (J9 - PANEL 0)
26 USBD-/RG3 " "
25 USBID/RF3 " " [OK]
59 AN5/C1IN+/VBUSON/CN7/RB5 (J8)
2 AERXD0/INT1/RE8
CAN:
14 AC1TX/SCK3A/U3BTX/U3ARTS/RF13/CAN1 (J4)
15 AC1RX/SS3A/U3BRX/U3ACTS/RF12/CAN1 (J4)
22 T3CK/AC2TX/RC2/CAN2 (J9 - PANEL 0) [OK]
23 T4CK/AC2RX/RC " " [OK]