cortex_a: Add support for A7 MPCore

A7 MPCore needs unlocking the debug registers same as with A15 MPCore.
Found out by hacking on the code.

Change-Id: I613cb4fb35007b85b4a9a401577b47768bc1a08b
Signed-off-by: Alexander Stein <alexander.stein@systec-electronic.com>
Reviewed-on: http://openocd.zylin.com/2344
Tested-by: jenkins
Reviewed-by: Kamal Dasu <kamal.dasu@gmail.com>
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>

src/target/cortex_a.c

@@ -208,6 +208,7 @@ static int cortex_a_init_debug_access(struct target *target)
 		CORTEX_A_MIDR_PARTNUM_SHIFT;
 
 	switch (cortex_part_num) {
+	case CORTEX_A7_PARTNUM:
 	case CORTEX_A15_PARTNUM:
 		retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap,
 						    armv7a->debug_base + CPUDBG_OSLSR,
@@ -2511,6 +2512,18 @@ static int cortex_a_examine_first(struct target *target)
 		if (retval != ERROR_OK)
 			return retval;
 
+	}
+	/* Unlocking the debug registers */
+	if ((cpuid & CORTEX_A_MIDR_PARTNUM_MASK) >> CORTEX_A_MIDR_PARTNUM_SHIFT ==
+		CORTEX_A7_PARTNUM) {
+
+		retval = mem_ap_sel_write_atomic_u32(swjdp, armv7a->debug_ap,
+						     armv7a->debug_base + CPUDBG_OSLAR,
+						     0);
+
+		if (retval != ERROR_OK)
+			return retval;
+
 	}
 	retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap,
 					    armv7a->debug_base + CPUDBG_PRSR, &dbg_osreg);

src/target/cortex_a.h

@@ -35,6 +35,7 @@
 #define CORTEX_A_COMMON_MAGIC 0x411fc082
 #define CORTEX_A15_COMMON_MAGIC 0x413fc0f1
 
+#define CORTEX_A7_PARTNUM 0xc07
 #define CORTEX_A8_PARTNUM 0xc08
 #define CORTEX_A9_PARTNUM 0xc09
 #define CORTEX_A15_PARTNUM 0xc0f