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There's no indication of active low or high in the 68k module port definition. I recently tried to use this in a project and assumed it was low. No activity when the CPU was hooked up.
Double checked when using the 68k module in quartus, there's no errors when building (thought it might not be finding the micro code files). Possible to comment the in/out in the 68k module so the manual can be referenced? Thank you for your work @nukeykt.
everything should be as a real chip (i.e active low). For open drain outputs 0 = high impedance, 1 = GND. For DATA_z: 0=output enable, 1=high impedance
everything should be as a real chip (i.e active low). For open drain outputs 0 = high impedance, 1 = GND. For DATA_z: 0=output enable, 1=high impedance
Thank you, I have signs of life now in signal tap.
There's no indication of active low or high in the 68k module port definition. I recently tried to use this in a project and assumed it was low. No activity when the CPU was hooked up.
Double checked when using the 68k module in quartus, there's no errors when building (thought it might not be finding the micro code files). Possible to comment the in/out in the 68k module so the manual can be referenced? Thank you for your work @nukeykt.
Nuked-MD-FPGA/68k.v
Line 26 in 17ecae7
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