s32g3.dtsi

// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
 * Copyright 2021-2023 NXP
 */
#include <dt-bindings/clock/s32g3-clock.h>

/delete-node/ &gic;
/delete-node/ &scmi_scp_rx_mb;
/delete-node/ &scmi_scp_tx_md0;
/delete-node/ &scmi_scp_tx_md1;
/delete-node/ &scmi_scp_tx_md2;
/delete-node/ &scmi_scp_tx_md3;
/delete-node/ &scmi_scp_rx_md;
/ {
	model = "NXP S32G3XX";
	compatible = "nxp,s32g3";

	mem1: memory@80000000 {
		device_type = "memory";
		reg = <0 0x80000000 0 0x80000000>;
	};

	mem2: memory@880000000 {
		device_type = "memory";
		reg = <0x8 0x80000000 0 0x80000000>;
	};

	reserved-memory {
		/* SCP TX mailbox #4 */
		scmi_scp_tx_mb4: shm@34500200 {
			reg = <0x0 0x34500200 0x0 0x80>;
			no-map;
		};

		/* SCP TX mailbox #5 */
		scmi_scp_tx_mb5: shm@34500280 {
			reg = <0x0 0x34500280 0x0 0x80>;
			no-map;
		};

		/* SCP TX mailbox #6 */
		scmi_scp_tx_mb6: shm@34500300 {
			reg = <0x0 0x34500300 0x0 0x80>;
			no-map;
		};

		/* SCP TX mailbox #7 */
		scmi_scp_tx_mb7: shm@34500380 {
			reg = <0x0 0x34500380 0x0 0x80>;
			no-map;
		};

		/* SCP RX mailbox */
		scmi_scp_rx_mb: shm@34500400 {
			reg = <0x0 0x34500400 0x0 0x80>;
			no-map;
		};

		/* SCP TX metadata #0 */
		scmi_scp_tx_md0: shm@34500480 {
			reg = <0x0 0x34500480 0x0 0x80>;
			status = "disabled";
			no-map;
		};

		/* SCP TX metadata #1 */
		scmi_scp_tx_md1: shm@34500500 {
			reg = <0x0 0x34500500 0x0 0x80>;
			status = "disabled";
			no-map;
		};

		/* SCP TX metadata #2 */
		scmi_scp_tx_md2: shm@34500580 {
			reg = <0x0 0x34500580 0x0 0x80>;
			status = "disabled";
			no-map;
		};

		/* SCP TX metadata #3 */
		scmi_scp_tx_md3: shm@34500600 {
			reg = <0x0 0x34500600 0x0 0x80>;
			status = "disabled";
			no-map;
		};

		/* SCP TX metadata #4 */
		scmi_scp_tx_md4: shm@34500680 {
			reg = <0x0 0x34500680 0x0 0x80>;
			status = "disabled";
			no-map;
		};

		/* SCP TX metadata #5 */
		scmi_scp_tx_md5: shm@34500700 {
			reg = <0x0 0x34500700 0x0 0x80>;
			status = "disabled";
			no-map;
		};

		/* SCP TX metadata #6 */
		scmi_scp_tx_md6: shm@34500780 {
			reg = <0x0 0x34500780 0x0 0x80>;
			status = "disabled";
			no-map;
		};

		/* SCP TX metadata #7 */
		scmi_scp_tx_md7: shm@34500800 {
			reg = <0x0 0x34500800 0x0 0x80>;
			status = "disabled";
			no-map;
		};

		/* SCP RX metadata */
		scmi_scp_rx_md: shm@34500880 {
			reg = <0x0 0x34500880 0x0 0x80>;
			status = "disabled";
			no-map;
		};
	};

	cpus {
		cpu-map {
			cluster0 {
				core0 {
					cpu = <&cpu0>;
				};

				core1 {
					cpu = <&cpu1>;
				};

				core2 {
					cpu = <&cpu2>;
				};

				core3 {
					cpu = <&cpu3>;
				};
			};

			cluster1 {
				core0 {
					cpu = <&cpu4>;
				};

				core1 {
					cpu = <&cpu5>;
				};

				core2 {
					cpu = <&cpu6>;
				};

				core3 {
					cpu = <&cpu7>;
				};
			};
		};

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x0>;
			enable-method = "psci";
			clocks = <&dfs S32CC_SCMI_PERF_A53>;
			next-level-cache = <&cluster0_l2_cache>;

			nvmem-cells = <&core_max_freq>;
			nvmem-cell-names = "core_max_freq";
			u-boot,dm-pre-reloc;
		};

		cpu1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x1>;
			enable-method = "psci";
			clocks = <&dfs S32CC_SCMI_PERF_A53>;
			next-level-cache = <&cluster0_l2_cache>;

			nvmem-cells = <&core_max_freq>;
			nvmem-cell-names = "core_max_freq";
		};

		cpu2: cpu@2 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x2>;
			enable-method = "psci";
			clocks = <&dfs S32CC_SCMI_PERF_A53>;
			next-level-cache = <&cluster0_l2_cache>;

			nvmem-cells = <&core_max_freq>;
			nvmem-cell-names = "core_max_freq";
		};

		cpu3: cpu@3 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x3>;
			enable-method = "psci";
			clocks = <&dfs S32CC_SCMI_PERF_A53>;
			next-level-cache = <&cluster0_l2_cache>;

			nvmem-cells = <&core_max_freq>;
			nvmem-cell-names = "core_max_freq";
		};

		cpu4: cpu@100 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x100>;
			enable-method = "psci";
			clocks = <&dfs S32CC_SCMI_PERF_A53>;
			next-level-cache = <&cluster1_l2_cache>;

			nvmem-cells = <&core_max_freq>;
			nvmem-cell-names = "core_max_freq";
		};

		cpu5: cpu@101 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x101>;
			enable-method = "psci";
			clocks = <&dfs S32CC_SCMI_PERF_A53>;
			next-level-cache = <&cluster1_l2_cache>;

			nvmem-cells = <&core_max_freq>;
			nvmem-cell-names = "core_max_freq";
		};

		cpu6: cpu@102 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x102>;
			enable-method = "psci";
			clocks = <&dfs S32CC_SCMI_PERF_A53>;
			next-level-cache = <&cluster1_l2_cache>;

			nvmem-cells = <&core_max_freq>;
			nvmem-cell-names = "core_max_freq";
		};

		cpu7: cpu@103 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x103>;
			enable-method = "psci";
			clocks = <&dfs S32CC_SCMI_PERF_A53>;
			next-level-cache = <&cluster1_l2_cache>;

			nvmem-cells = <&core_max_freq>;
			nvmem-cell-names = "core_max_freq";
		};
	};

	soc {
		mc_cgm6: mc_cgm6@4053c000 {
			compatible = "nxp,s32cc-mc_cgm6";
			reg = <0x0 0x4053c000 0x0 0x3000>;

			assigned-clocks =
				<&plat_clks S32G_CLK_MC_CGM6_MUX0>,
				<&plat_clks S32G_CLK_MC_CGM6_MUX1>,
				<&plat_clks S32G_CLK_MC_CGM6_MUX2>,
				<&plat_clks S32GEN1_CLK_GMAC0_TS>;
			assigned-clock-parents =
				<&plat_clks S32GEN1_CLK_PERIPH_PLL_PHI4>,
				<&plat_clks S32GEN1_CLK_PERIPH_PLL_PHI5>,
				<&plat_clks S32GEN1_CLK_GMAC0_EXT_RX>;
			assigned-clock-rates =
				<0>,
				<0>,
				<0>,
				<200000000>;
		};

		gic: interrupt-controller@50800000 {
			compatible = "arm,gic-v3";
			#interrupt-cells = <3>;
			#address-cells = <2>;
			#size-cells = <2>;
			interrupt-controller;
			reg = <0 0x50800000 0 0x10000>, /* GIC Dist */
			      <0 0x50900000 0 0x200000>, /* GICR (RD_base + SGI_base) */
			      <0 0x50400000 0 0x2000>, /* GICC */
			      <0 0x50410000 0 0x2000>, /* GICH */
			      <0 0x50420000 0 0x2000>; /* GICV */
			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
		};
	};
};

&mc_cgm0 {
	assigned-clocks =
		<&plat_clks S32GEN1_CLK_MC_CGM0_MUX0>,
		<&plat_clks S32GEN1_CLK_MC_CGM0_MUX1>,
		<&plat_clks S32GEN1_CLK_MC_CGM0_MUX2>,
		<&plat_clks S32GEN1_CLK_MC_CGM0_MUX3>,
		<&plat_clks S32GEN1_CLK_MC_CGM0_MUX4>,
		<&plat_clks S32GEN1_CLK_MC_CGM0_MUX5>,
		<&plat_clks S32GEN1_CLK_MC_CGM0_MUX7>,
		<&plat_clks S32GEN1_CLK_MC_CGM0_MUX8>,
		<&plat_clks S32GEN1_CLK_MC_CGM0_MUX12>,
		<&plat_clks S32GEN1_CLK_MC_CGM0_MUX14>,
		<&plat_clks S32GEN1_CLK_MC_CGM0_MUX16>,
		<&plat_clks S32GEN1_CLK_PER>,
		<&plat_clks S32GEN1_CLK_XBAR_2X>,
		<&plat_clks S32GEN1_CLK_FTM0_REF>,
		<&plat_clks S32GEN1_CLK_FTM1_REF>,
		<&plat_clks S32GEN1_CLK_CAN_PE>,
		<&plat_clks S32GEN1_CLK_LIN_BAUD>,
		<&plat_clks S32GEN1_CLK_SPI>,
		<&plat_clks S32GEN1_CLK_QSPI_2X>,
		<&plat_clks S32GEN1_CLK_SDHC>;
	assigned-clock-parents =
		<&plat_clks S32GEN1_CLK_ARM_PLL_DFS1>,
		<&plat_clks S32GEN1_CLK_PERIPH_PLL_PHI0>,
		<&plat_clks S32GEN1_CLK_FXOSC>,
		<&plat_clks S32GEN1_CLK_PERIPH_PLL_PHI1>,
		<&plat_clks S32GEN1_CLK_PERIPH_PLL_PHI1>,
		<&plat_clks S32GEN1_CLK_PERIPH_PLL_PHI1>,
		<&plat_clks S32GEN1_CLK_PERIPH_PLL_PHI2>,
		<&plat_clks S32GEN1_CLK_PERIPH_PLL_PHI3>,
		<&plat_clks S32GEN1_CLK_PERIPH_PLL_DFS1>,
		<&plat_clks S32GEN1_CLK_PERIPH_PLL_DFS3>,
		<&plat_clks S32GEN1_CLK_PERIPH_PLL_PHI7>;
	assigned-clock-rates =
		<0>,
		<0>,
		<0>,
		<0>,
		<0>,
		<0>,
		<0>,
		<0>,
		<0>,
		<0>,
		<0>,
		<80000000>,
		<0>,
		<40000000>,
		<40000000>,
		<80000000>,
		<125000000>,
		<100000000>,
		<S32GEN1_QSPI_2X_CLK_FREQ>,
		<400000000>;
};

&cmu {
	compatible = "nxp,s32g3-cmu";
};

&qspi {
	compatible = "nxp,s32g3-qspi", "nxp,s32cc-qspi";
	pinctrl-names = "default";
	pinctrl-0 = <&qspi_pins_200mhz_slow_sre>;
};

&siul2_0_nvram {
	compatible = "nxp,s32g3-siul2_0-nvram";
};

&siul2_1_nvram {
	compatible = "nxp,s32g3-siul2_1-nvram";
};

&pcie0 {
	pcie_device_id = <0x4300>;
};

&pcie1 {
	pcie_device_id = <0x4300>;
};

&scmi {
	nxp,scp-mboxes = <&scmi_scp_tx_mb0>, <&scmi_scp_tx_md0>,
			<&scmi_scp_tx_mb1>, <&scmi_scp_tx_md1>,
			<&scmi_scp_tx_mb2>, <&scmi_scp_tx_md2>,
			<&scmi_scp_tx_mb3>, <&scmi_scp_tx_md3>,
			<&scmi_scp_tx_mb4>, <&scmi_scp_tx_md4>,
			<&scmi_scp_tx_mb5>, <&scmi_scp_tx_md5>,
			<&scmi_scp_tx_mb6>, <&scmi_scp_tx_md6>,
			<&scmi_scp_tx_mb7>, <&scmi_scp_tx_md7>,
			<&scmi_scp_rx_mb>, <&scmi_scp_rx_md>,
			<&scmi_ospm_notif>;
	nxp,scp-mbox-names = "scp_tx_mb0", "scp_tx_md0",
			"scp_tx_mb1", "scp_tx_md1",
			"scp_tx_mb2", "scp_tx_md2",
			"scp_tx_mb3", "scp_tx_md3",
			"scp_tx_mb4", "scp_tx_md4",
			"scp_tx_mb5", "scp_tx_md5",
			"scp_tx_mb6", "scp_tx_md6",
			"scp_tx_mb7", "scp_tx_md7",
			"scp_rx_mb", "scp_rx_md",
			"scmi_ospm_notif";
};

&nvmem_scmi {
	compatible = "nxp,s32g3-nvmem-scmi";
};

&mscm0 {
	/* CPU2CPU interrupts */
	interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, // CPU to M7/A53 interrupt#0
		<GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, // CPU to M7/A53 interrupt#1
		<GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, // CPU to M7/A53 interrupt#2
		<GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, // CPU to M7/A53 interrupt#3
		<GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, // CPU to M7/A53 interrupt#4
		<GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, // CPU to M7/A53 interrupt#5
		<GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, // CPU to M7/A53 interrupt#6
		<GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, // CPU to M7/A53 interrupt#7
		<GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>, // CPU to M7/A53 interrupt#8
		<GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>, // CPU to M7/A53 interrupt#9
		<GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>, // CPU to M7/A53 interrupt#10
		<GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; // CPU to M7/A53 interrupt#11
};