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fsl_pxp.h
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fsl_pxp.h
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/*
* Copyright 2017-2023 NXP
* All rights reserved.
*
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _FSL_PXP_H_
#define _FSL_PXP_H_
#include "fsl_common.h"
/* Compatibility macro map. */
#if defined(PXP_AS_CTRL_ALPHA_INVERT_MASK) && (!defined(PXP_AS_CTRL_ALPHA0_INVERT_MASK))
#define PXP_AS_CTRL_ALPHA0_INVERT_MASK PXP_AS_CTRL_ALPHA_INVERT_MASK
#endif
#if defined(PXP_AS_CTRL_ALPHA_INVERT_MASK) && (!defined(PXP_AS_CTRL_ALPHA_INVERT_MASK))
#define PXP_AS_CTRL_ALPHA0_INVERT_MASK PXP_AS_CTRL_ALPHA_INVERT_MASK
#endif
#if defined(PXP_STAT_IRQ_MASK) && (!defined(PXP_STAT_IRQ0_MASK))
#define PXP_STAT_IRQ0_MASK PXP_STAT_IRQ_MASK
#endif
#if defined(PXP_STAT_AXI_READ_ERROR_MASK) && (!defined(PXP_STAT_AXI_READ_ERROR_0_MASK))
#define PXP_STAT_AXI_READ_ERROR_0_MASK PXP_STAT_AXI_READ_ERROR_MASK
#endif
#if defined(PXP_STAT_AXI_WRITE_ERROR_MASK) && (!defined(PXP_STAT_AXI_WRITE_ERROR_0_MASK))
#define PXP_STAT_AXI_WRITE_ERROR_0_MASK PXP_STAT_AXI_WRITE_ERROR_MASK
#endif
/*!
* @addtogroup pxp_driver
* @{
*/
/*******************************************************************************
* Definitions
******************************************************************************/
/* PXP global LUT table is 16K. */
#define PXP_LUT_TABLE_BYTE (16UL * 1024UL)
/* Intenral memory for LUT, the size is 256 bytes. */
#define PXP_INTERNAL_RAM_LUT_BYTE (256)
/*! @name Driver version */
/*@{*/
#define FSL_PXP_DRIVER_VERSION (MAKE_VERSION(2, 6, 0))
/*@}*/
/* This macto indicates whether the rotate sub module is shared by process surface and output buffer. */
#if defined(PXP_CTRL_ROT_POS_MASK)
#define PXP_SHARE_ROTATE 1
#else
#define PXP_SHARE_ROTATE 0
#endif
/* This macto indicates whether PXP needs mux the process path. */
#if defined(PXP_DATA_PATH_CTRL0_MUX0_SEL_MASK)
#define PXP_USE_PATH 1
#else
#define PXP_USE_PATH 0
#endif
#if PXP_USE_PATH
#define PXP_PATH(mux, sel) (((mux) << 8U) | (sel))
#define PXP_GET_MUX_FROM_PATH(path) ((path) >> 8U)
#define PXP_GET_SEL_FROM_PATH(path) ((path)&0x03U)
#endif /* PXP_USE_PATH */
#define PXP_COMBINE_BYTE_TO_WORD(dataAddr) \
((*(uint8_t *)(dataAddr)) | ((*(uint8_t *)((dataAddr) + 1U)) << 8U) | ((*(uint8_t *)((dataAddr) + 2U)) << 16U) | \
((*(uint8_t *)((dataAddr) + 3U)) << 24U));
/*! @brief PXP interrupts to enable. */
enum _pxp_interrupt_enable
{
kPXP_CompleteInterruptEnable = PXP_CTRL_IRQ_ENABLE_MASK, /*!< PXP process completed. bit 1 */
kPXP_CommandLoadInterruptEnable = PXP_CTRL_NEXT_IRQ_ENABLE_MASK, /*!< Interrupt to show that the command set by @ref
PXP_SetNextCommand has been loaded. bit 2 */
#if !(defined(FSL_FEATURE_PXP_HAS_NO_LUT) && FSL_FEATURE_PXP_HAS_NO_LUT)
kPXP_LutDmaLoadInterruptEnable =
PXP_CTRL_LUT_DMA_IRQ_ENABLE_MASK, /*!< The LUT table has been loaded by DMA. bit 3 */
#endif
#if defined(FSL_FEATURE_PXP_V3) && FSL_FEATURE_PXP_V3
kPXP_CompressDoneInterruptEnable =
PXP_IRQ_MASK_COMPRESS_DONE_IRQ_EN_MASK >> 16U, /*!< Compress done interrupt enable. bit 15 */
kPXP_InputFetchCh0InterruptEnable = PXP_IRQ_MASK_FIRST_CH0_PREFETCH_IRQ_EN_MASK
<< 16U, /*!< Input fetch channel 0 completed. bit 16 */
kPXP_InputFetchCh1InterruptEnable = PXP_IRQ_MASK_FIRST_CH1_PREFETCH_IRQ_EN_MASK
<< 16U, /*!< Input fetch channel 1 completed. bit 17 */
kPXP_InputStoreCh0InterruptEnable = PXP_IRQ_MASK_FIRST_CH0_STORE_IRQ_EN_MASK
<< 16U, /*!< Input store channel 0 completed. bit 18 */
kPXP_InputStoreCh1InterruptEnable = PXP_IRQ_MASK_FIRST_CH1_STORE_IRQ_EN_MASK
<< 16U, /*!< Input store channel 1 completed. bit 19 */
kPXP_DitherFetchCh0InterruptEnable = PXP_IRQ_MASK_DITHER_CH0_PREFETCH_IRQ_EN_MASK
<< 16U, /*!< Dither fetch channel 0 completed. bit 20 */
kPXP_DitherFetchCh1InterruptEnable = PXP_IRQ_MASK_DITHER_CH1_PREFETCH_IRQ_EN_MASK
<< 16U, /*!< Dither fetch channel 1 completed. bit 21 */
kPXP_DitherStoreCh0InterruptEnable = PXP_IRQ_MASK_DITHER_CH0_STORE_IRQ_EN_MASK
<< 16U, /*!< Dither store channle 0 completed. bit 22 */
kPXP_DitherStoreCh1InterruptEnable = PXP_IRQ_MASK_DITHER_CH1_STORE_IRQ_EN_MASK
<< 16U, /*!< Dither store channle 1 completed. bit 23 */
kPXP_WfeaStoreCh0InterruptEnable = PXP_IRQ_MASK_WFE_A_CH0_STORE_IRQ_EN_MASK
<< 16U, /*!< WFE-A store channel 0 completed. bit 24 */
kPXP_WfeaStoreCh1InterruptEnable = PXP_IRQ_MASK_WFE_A_CH1_STORE_IRQ_EN_MASK
<< 16U, /*!< WFE-A store channel 1 completed. bit 25 */
kPXP_WfebStoreCh0InterruptEnable = PXP_IRQ_MASK_WFE_B_CH0_STORE_IRQ_EN_MASK
<< 16U, /*!< WFE-B store channel 0 completed. bit 26 */
kPXP_WfebStoreCh1InterruptEnable = PXP_IRQ_MASK_WFE_B_CH1_STORE_IRQ_EN_MASK
<< 16U, /*!< WFE-B store channel 1 completed. bit 27 */
kPXP_InputStoreInterruptEnable = PXP_IRQ_MASK_FIRST_STORE_IRQ_EN_MASK << 16U, /*!< Input store completed. bit 28 */
kPXP_DitherStoreInterruptEnable = PXP_IRQ_MASK_DITHER_STORE_IRQ_EN_MASK
<< 16U, /*!< Dither store completed. bit 29 */
kPXP_WfeaStoreInterruptEnable = PXP_IRQ_MASK_WFE_A_STORE_IRQ_EN_MASK << 16U, /*!< WFE-A store completed. bit 30 */
kPXP_WfebStoreInterruptEnable = PXP_IRQ_MASK_WFE_B_STORE_IRQ_EN_MASK << 16U, /*!< WFE-B store completed. bit 31 */
#endif /* FSL_FEATURE_PXP_V3 */
};
/*!
* @brief PXP status flags.
*
* @note These enumerations are meant to be OR'd together to form a bit mask.
*/
enum _pxp_flags
{
kPXP_CompleteFlag = PXP_STAT_IRQ0_MASK, /*!< PXP process completed. bit 0 */
kPXP_Axi0WriteErrorFlag = PXP_STAT_AXI_WRITE_ERROR_0_MASK, /*!< PXP encountered an AXI write error and processing
has been terminated. bit 1*/
kPXP_Axi0ReadErrorFlag = PXP_STAT_AXI_READ_ERROR_0_MASK, /*!< PXP encountered an AXI read error and processing has
been terminated. bit 2 */
kPXP_CommandLoadFlag = PXP_STAT_NEXT_IRQ_MASK, /*!< The command set by @ref PXP_SetNextCommand has been loaded,
could set new command. bit 3 */
#if !(defined(FSL_FEATURE_PXP_HAS_NO_LUT) && FSL_FEATURE_PXP_HAS_NO_LUT)
kPXP_LutDmaLoadFlag = PXP_STAT_LUT_DMA_LOAD_DONE_IRQ_MASK, /*!< The LUT table has been loaded by DMA. bit 8 */
#endif
#if defined(PXP_STAT_AXI_READ_ERROR_1_MASK)
kPXP_Axi1WriteErrorFlag = PXP_STAT_AXI_WRITE_ERROR_1_MASK, /*!< PXP encountered an AXI write error and processing
has been terminated. bit 9 */
kPXP_Axi1ReadErrorFlag = PXP_STAT_AXI_READ_ERROR_1_MASK, /*!< PXP encountered an AXI read error and processing has
been terminated. bit 10 */
#endif
#if defined(FSL_FEATURE_PXP_V3) && FSL_FEATURE_PXP_V3
kPXP_CompressDoneFlag = PXP_IRQ_COMPRESS_DONE_IRQ_MASK >> 16U, /*!< Compress done. bit 15 */
kPXP_InputFetchCh0CompleteFlag = PXP_IRQ_FIRST_CH0_PREFETCH_IRQ_MASK
<< 16U, /*!< Input fetch channel 0 completed. bit 16 */
kPXP_InputFetchCh1CompleteFlag = PXP_IRQ_FIRST_CH1_PREFETCH_IRQ_MASK
<< 16U, /*!< Input fetch channel 1 completed. bit 17 */
kPXP_InputStoreCh0CompleteFlag = PXP_IRQ_FIRST_CH0_STORE_IRQ_MASK
<< 16U, /*!< Input store channel 0 completed. bit 18 */
kPXP_InputStoreCh1CompleteFlag = PXP_IRQ_FIRST_CH1_STORE_IRQ_MASK
<< 16U, /*!< Input store channel 1 completed. bit 19 */
kPXP_DitherFetchCh0CompleteFlag = PXP_IRQ_DITHER_CH0_PREFETCH_IRQ_MASK
<< 16U, /*!< Dither fetch channel 0 completed. bit 20 */
kPXP_DitherFetchCh1CompleteFlag = PXP_IRQ_DITHER_CH1_PREFETCH_IRQ_MASK
<< 16U, /*!< Dither fetch channel 1 completed. bit 21 */
kPXP_DitherStoreCh0CompleteFlag = PXP_IRQ_DITHER_CH0_STORE_IRQ_MASK
<< 16U, /*!< Dither store channel 0 completed. bit 22 */
kPXP_DitherStoreCh1CompleteFlag = PXP_IRQ_DITHER_CH1_STORE_IRQ_MASK
<< 16U, /*!< Dither store channel 1 completed. bit 23 */
kPXP_WfeaStoreCh0CompleteFlag = PXP_IRQ_WFE_A_CH0_STORE_IRQ_MASK
<< 16U, /*!< WFE-A store channel 0 completed. bit 24 */
kPXP_WfeaStoreCh1CompleteFlag = PXP_IRQ_WFE_A_CH1_STORE_IRQ_MASK
<< 16U, /*!< WFE-A store channel 1 completed. bit 25 */
kPXP_WfebStoreCh0CompleteFlag = PXP_IRQ_WFE_B_CH0_STORE_IRQ_MASK
<< 16U, /*!< WFE-B store channel 0 completed. bit 26 */
kPXP_WfebStoreCh1CompleteFlag = PXP_IRQ_WFE_B_CH1_STORE_IRQ_MASK
<< 16U, /*!< WFE-B store channel 1 completed. bit 27 */
kPXP_InputStoreCompleteFlag = PXP_IRQ_FIRST_STORE_IRQ_MASK << 16U, /*!< Input store completed. bit 28 */
kPXP_DitherStoreCompleteFlag = PXP_IRQ_DITHER_STORE_IRQ_MASK << 16U, /*!< Dither store completed. bit 29 */
kPXP_WfeaStoreCompleteFlag = PXP_IRQ_WFE_A_STORE_IRQ_MASK << 16U, /*!< WFE-A store completed. bit 30 */
kPXP_WfebStoreCompleteFlag = PXP_IRQ_WFE_B_STORE_IRQ_MASK << 16U, /*!< WFE-B store completed. bit 31 */
#endif /* FSL_FEATURE_PXP_V3 */
};
#if PXP_USE_PATH
#if defined(FSL_FEATURE_PXP_V3) && FSL_FEATURE_PXP_V3
typedef enum _pxp_path
{
kPXP_Mux0SelectProcessSurfaceEngine = PXP_PATH(0U, 0U), /*!< MUX0 select Process Surface engine. */
kPXP_Mux0SelectInputFetchEngineChannel0 = PXP_PATH(0U, 1U), /*!< MUX0 select input Fetch engine channel 0. */
kPXP_Mux0SelectInputFetchEngineChannel1 = PXP_PATH(0U, 2U), /*!< MUX0 select input Fetch engine channel 1. */
kPXP_Mux0SelectNone = PXP_PATH(0U, 3U), /*!< MUX0 select no output. */
kPXP_Mux1SelectInputFetchEngineChannel0 = PXP_PATH(1U, 0U), /*!< MUX1 select input Fetch engine channel 0. */
kPXP_Mux1SelectRotation1Engine = PXP_PATH(1U, 1U), /*!< MUX1 select Rotation1 engine output. */
kPXP_Mux1SelectNone = PXP_PATH(1U, 2U), /*!< MUX1 select no output. */
kPXP_Mux2SelectInputFetchEngineChannel1 = PXP_PATH(2U, 0U), /*!< MUX2 select input Fetch engine channel 1. */
kPXP_Mux2SelectRotation1Engine = PXP_PATH(2U, 1U), /*!< MUX2 select Rotation1 engine output. */
kPXP_Mux2SelectNone = PXP_PATH(2U, 2U), /*!< MUX2 select no output. */
kPXP_Mux3SelectCsc1Engine = PXP_PATH(3U, 0U), /*!< MUX3 select output of CSC1 engine. */
kPXP_Mux3SelectRotation1Engine = PXP_PATH(3U, 1U), /*!< MUX3 select output of Rotation1 engine. */
kPXP_Mux3SelectNone = PXP_PATH(3U, 2U), /*!< MUX3 select no output. */
kPXP_Mux5SelectMux1 = PXP_PATH(5U, 0U), /*!< MUX5 select output of MUX1. */
kPXP_Mux5SelectAlphaBlending1 = PXP_PATH(5U, 1U), /*!< MUX5 select output of alpha blending / color key 1. */
kPXP_Mux5SelectNone = PXP_PATH(5U, 2U), /*!< MUX5 select no output. */
kPXP_Mux6SelectAlphaBlending1 = PXP_PATH(6U, 0U), /*!< MUX6 select output of alpha blending / color key 1. */
kPXP_Mux6SelectAlphaBlending0 = PXP_PATH(6U, 1U), /*!< MUX6 select output of alpha blending / color key 0. */
kPXP_Mux6SelectNone = PXP_PATH(6U, 2U), /*!< MUX6 select no output. */
kPXP_Mux7SelectMux5 = PXP_PATH(7U, 0U), /*!< MUX7 select output of MUX5. */
kPXP_Mux7SelectCsc2Engine = PXP_PATH(7U, 1U), /*!< MUX7 select output of CSC2 engine. */
kPXP_Mux7SelectNone = PXP_PATH(7U, 2U), /*!< MUX7 select no output. */
kPXP_Mux8SelectCsc2Engine = PXP_PATH(8U, 0U), /*!< MUX8 select output of CSC2 engine. */
kPXP_Mux8SelectAlphaBlending0 = PXP_PATH(8U, 1U), /*!< MUX8 select output of alpha blending / color key 0. */
kPXP_Mux8SelectNone = PXP_PATH(8U, 2U), /*!< MUX8 select no output. */
kPXP_Mux9SelectMux7 = PXP_PATH(9U, 0U), /*!< MUX9 select output of MUX7. */
kPXP_Mux9SelectMux8 = PXP_PATH(9U, 1U), /*!< MUX9 select output of MUX8. */
kPXP_Mux9SelectNone = PXP_PATH(9U, 2U), /*!< MUX9 select no output. */
kPXP_Mux10SelectMux7 = PXP_PATH(10U, 0U), /*!< MUX10 select output of MUX7. */
kPXP_Mux10SelectLut = PXP_PATH(10U, 1U), /*!< MUX10 select output of LUT. */
kPXP_Mux10SelectNone = PXP_PATH(10U, 2U), /*!< MUX10 select no output. */
kPXP_Mux11SelectLut = PXP_PATH(11U, 0U), /*!< MUX11 select output of LUT. */
kPXP_Mux11SelectMux8 = PXP_PATH(11U, 1U), /*!< MUX11 select output of MUX8. */
kPXP_Mux11SelectNone = PXP_PATH(11U, 2U), /*!< MUX11 select no output. */
kPXP_Mux12SelectMux10 = PXP_PATH(12U, 0U), /*!< MUX12 select output of MUX10. */
kPXP_Mux12SelectMux11 = PXP_PATH(12U, 1U), /*!< MUX12 select output of MUX11. */
kPXP_Mux12SelectNone = PXP_PATH(12U, 2U), /*!< MUX12 select no output. */
kPXP_Mux13SelectNone = PXP_PATH(13U, 0U), /*!< MUX13 select no output. */
kPXP_Mux13SelectFetchEngineChannel1 = PXP_PATH(13U, 1U), /*!< MUX13 select input Fetch engine channel 1. */
kPXP_Mux14SelectRotation0Engine = PXP_PATH(14U, 0U), /*!< MUX14 select output of Rotation0 engine. */
kPXP_Mux14SelectMux11 = PXP_PATH(14U, 1U), /*!< MUX14 select output of MUX11. */
kPXP_Mux14SelectNone = PXP_PATH(14U, 2U), /*!< MUX14 select no output. */
kPXP_Mux15SelectFetchEngineChannel0 = PXP_PATH(15U, 0U), /*!< MUX15 select input Fetch engine channel 0. */
kPXP_Mux15SelectMux10 = PXP_PATH(15U, 1U), /*!< MUX15 select output of MUX10. */
kPXP_Mux15SelectNone = PXP_PATH(15U, 2U), /*!< MUX15 select no output. */
kPXP_Mux16SelectAluA = PXP_PATH(16U, 0U), /*!< MUX16 select output of ALU A. */
kPXP_Mux16SelectOutput = PXP_PATH(16U, 1U), /*!< MUX16 select output of legacy output. */
kPXP_Mux16SelectAluB = PXP_PATH(16U, 2U), /*!< MUX16 select output of ALU B. */
kPXP_Mux16SelectNone = PXP_PATH(16U, 3U), /*!< MUX16 select no output. */
kPXP_Mux17SelectAluA = PXP_PATH(17U, 0U), /*!< MUX17 select output of ALU A. */
kPXP_Mux17SelectAluB = PXP_PATH(17U, 1U), /*!< MUX17 select output of ALU B. */
kPXP_Mux17SelectNone = PXP_PATH(17U, 2U), /*!< MUX17 select no output. */
} pxp_path_t;
#else
typedef enum _pxp_path
{
kPXP_Mux0SelectFetchDataArray = PXP_PATH(0U, 0U), /*!< MUX0 select Fetch Data Array. */
kPXP_Mux0SelectAlu = PXP_PATH(0U, 1U), /*!< MUX0 select output of ALU. */
kPXP_Mux0SelectNone = PXP_PATH(0U, 2U), /*!< MUX0 select no output. */
kPXP_Mux1SelectLut = PXP_PATH(1U, 0U), /*!< MUX1 select output of LUT. */
kPXP_Mux1SelectMux0 = PXP_PATH(1U, 1U), /*!< MUX1 select output of MUX0. */
kPXP_Mux1SelectNone = PXP_PATH(1U, 2U), /*!< MUX1 select no output. */
kPXP_Mux3SelectRotation1Engine = PXP_PATH(3U, 0U), /*!< MUX3 select output of Rotation1 engine. */
kPXP_Mux3SelectCsc1Engine = PXP_PATH(3U, 1U), /*!< MUX3 select output of CSC1 engine. */
kPXP_Mux3SelectNone = PXP_PATH(3U, 2U), /*!< MUX3 select no output. */
kPXP_Mux8SelectCsc2Engine = PXP_PATH(8U, 0U), /*!< MUX8 select output of CSC2 engine. */
kPXP_Mux8SelectAlphaBlending0 = PXP_PATH(8U, 1U), /*!< MUX8 select output of alpha blending / color key 0. */
kPXP_Mux8SelectNone = PXP_PATH(8U, 2U), /*!< MUX8 select no output. */
kPXP_Mux9SelectMux0 = PXP_PATH(9U, 0U), /*!< MUX9 select output of MUX0. */
kPXP_Mux9SelectMux8 = PXP_PATH(9U, 1U), /*!< MUX9 select output of MUX8. */
kPXP_Mux9SelectNone = PXP_PATH(9U, 2U), /*!< MUX9 select no output. */
kPXP_Mux11SelectLut = PXP_PATH(11U, 0U), /*!< MUX11 select output of LUT. */
kPXP_Mux11SelectMux8 = PXP_PATH(11U, 1U), /*!< MUX11 select output of MUX8. */
kPXP_Mux11SelectNone = PXP_PATH(11U, 2U), /*!< MUX11 select no output. */
kPXP_Mux12SelectRotation0Engine = PXP_PATH(12U, 0U), /*!< MUX12 select output of Rotation0 engine. */
kPXP_Mux12SelectMux11 = PXP_PATH(12U, 1U), /*!< MUX12 select output of MUX11. */
kPXP_Mux12SelectNone = PXP_PATH(12U, 2U), /*!< MUX12 select no output. */
kPXP_Mux14SelectDitherEngine = PXP_PATH(14U, 0U), /*!< MUX14 select output of Dither engine. */
kPXP_Mux14SelectMux12 = PXP_PATH(14U, 1U), /*!< MUX14 select output of MUX12. */
kPXP_Mux14SelectNone = PXP_PATH(14U, 2U), /*!< MUX14 select no output. */
kPXP_Mux16SelectOutputBuffer = PXP_PATH(16U, 0U), /*!< MUX16 select output of output buffer. */
kPXP_Mux16SelectStoreEngine = PXP_PATH(16U, 1U), /*!< MUX16 select output of store engine. */
kPXP_Mux16SelectNone = PXP_PATH(16U, 2U), /*!< MUX16 select no output. */
kPXP_Mux17SelectOutputBuffer = PXP_PATH(17U, 0U), /*!< MUX17 select output of output buffer. */
kPXP_Mux17SelectStoreEngine = PXP_PATH(17U, 1U), /*!< MUX17 select output of store engine. */
kPXP_Mux17SelectNone = PXP_PATH(17U, 2U), /*!< MUX17 select no output. */
} pxp_path_t;
#endif /* FSL_FEATURE_PXP_V3 */
#endif /* PXP_USE_PATH */
/*! @brief PXP output flip mode. */
typedef enum _pxp_flip_mode
{
kPXP_FlipDisable = 0U, /*!< Flip disable. */
kPXP_FlipHorizontal = 0x01U, /*!< Horizontal flip. */
kPXP_FlipVertical = 0x02U, /*!< Vertical flip. */
kPXP_FlipBoth = 0x03U, /*!< Flip both directions. */
} pxp_flip_mode_t;
/*! @brief PXP rotate mode. */
typedef enum _pxp_rotate_position
{
kPXP_RotateOutputBuffer = 0U, /*!< Rotate the output buffer. */
kPXP_RotateProcessSurface, /*!< Rotate the process surface. */
} pxp_rotate_position_t;
/*! @brief PXP rotate degree. */
typedef enum _pxp_rotate_degree
{
kPXP_Rotate0 = 0U, /*!< Clock wise rotate 0 deg. */
kPXP_Rotate90, /*!< Clock wise rotate 90 deg. */
kPXP_Rotate180, /*!< Clock wise rotate 180 deg. */
kPXP_Rotate270, /*!< Clock wise rotate 270 deg. */
} pxp_rotate_degree_t;
/*! @brief PXP interlaced output mode. */
typedef enum _pxp_interlaced_output_mode
{
kPXP_OutputProgressive = 0U, /*!< All data written in progressive format to output buffer 0. */
kPXP_OutputField0, /*!< Only write field 0 data to output buffer 0. */
kPXP_OutputField1, /*!< Only write field 1 data to output buffer 0. */
kPXP_OutputInterlaced, /*!< Field 0 write to buffer 0, field 1 write to buffer 1. */
} pxp_interlaced_output_mode_t;
/*! @brief PXP output buffer format. */
typedef enum _pxp_output_pixel_format
{
kPXP_OutputPixelFormatARGB8888 = 0x0, /*!< 32-bit pixels with alpha. */
kPXP_OutputPixelFormatRGB888 = 0x4, /*!< 32-bit pixels without alpha (unpacked 24-bit format) */
kPXP_OutputPixelFormatRGB888P = 0x5, /*!< 24-bit pixels without alpha (packed 24-bit format) */
kPXP_OutputPixelFormatARGB1555 = 0x8, /*!< 16-bit pixels with alpha. */
kPXP_OutputPixelFormatARGB4444 = 0x9, /*!< 16-bit pixels with alpha. */
kPXP_OutputPixelFormatRGB555 = 0xC, /*!< 16-bit pixels without alpha. */
kPXP_OutputPixelFormatRGB444 = 0xD, /*!< 16-bit pixels without alpha. */
kPXP_OutputPixelFormatRGB565 = 0xE, /*!< 16-bit pixels without alpha. */
kPXP_OutputPixelFormatYUV1P444 = 0x10, /*!< 32-bit pixels (1-plane XYUV unpacked). */
kPXP_OutputPixelFormatUYVY1P422 = 0x12, /*!< 16-bit pixels (1-plane U0,Y0,V0,Y1 interleaved bytes) */
kPXP_OutputPixelFormatVYUY1P422 = 0x13, /*!< 16-bit pixels (1-plane V0,Y0,U0,Y1 interleaved bytes) */
kPXP_OutputPixelFormatY8 = 0x14, /*!< 8-bit monochrome pixels (1-plane Y luma output) */
kPXP_OutputPixelFormatY4 = 0x15, /*!< 4-bit monochrome pixels (1-plane Y luma, 4 bit truncation) */
kPXP_OutputPixelFormatYUV2P422 = 0x18, /*!< 16-bit pixels (2-plane UV interleaved bytes) */
kPXP_OutputPixelFormatYUV2P420 = 0x19, /*!< 16-bit pixels (2-plane UV) */
kPXP_OutputPixelFormatYVU2P422 = 0x1A, /*!< 16-bit pixels (2-plane VU interleaved bytes) */
kPXP_OutputPixelFormatYVU2P420 = 0x1B, /*!< 16-bit pixels (2-plane VU) */
} pxp_output_pixel_format_t;
/*! @brief PXP output buffer configuration. */
typedef struct _pxp_output_buffer_config
{
pxp_output_pixel_format_t pixelFormat; /*!< Output buffer pixel format. */
pxp_interlaced_output_mode_t interlacedMode; /*!< Interlaced output mode. */
uint32_t buffer0Addr; /*!< Output buffer 0 address. */
uint32_t buffer1Addr; /*!< Output buffer 1 address, used for UV data in YUV 2-plane mode, or
field 1 in output interlaced mode. */
uint16_t pitchBytes; /*!< Number of bytes between two vertically adjacent pixels. */
uint16_t width; /*!< Pixels per line. */
uint16_t height; /*!< How many lines in output buffer. */
} pxp_output_buffer_config_t;
/*! @brief PXP process surface buffer pixel format. */
typedef enum _pxp_ps_pixel_format
{
#if (!(defined(FSL_FEATURE_PXP_HAS_NO_EXTEND_PIXEL_FORMAT) && FSL_FEATURE_PXP_HAS_NO_EXTEND_PIXEL_FORMAT)) && \
(!(defined(FSL_FEATURE_PXP_V3) && FSL_FEATURE_PXP_V3))
kPXP_PsPixelFormatARGB8888 = 0x4, /*!< 32-bit pixels with alpha(when participates in blend with
alpha surface uses pixel format that has alpha value) or without alpha (unpacked 24-bit format) */
kPXP_PsPixelFormatARGB1555 = 0xC, /*!< 16-bit pixels with alpha(when participates in blend with
alpha surface uses pixel format that has alpha value) or without alpha. */
kPXP_PsPixelFormatARGB4444 = 0xD, /*!< 16-bit pixels with alpha(when participates in blend with
alpha surface uses pixel format that has alpha value) or without alpha. */
#else
kPXP_PsPixelFormatRGB888 = 0x4, /*!< 32-bit pixels without alpha (unpacked 24-bit format) */
kPXP_PsPixelFormatRGB555 = 0xC, /*!< 16-bit pixels without alpha. */
kPXP_PsPixelFormatRGB444 = 0xD, /*!< 16-bit pixels without alpha. */
#endif
kPXP_PsPixelFormatRGB565 = 0xE, /*!< 16-bit pixels without alpha. */
kPXP_PsPixelFormatYUV1P444 = 0x10, /*!< 32-bit pixels (1-plane XYUV unpacked). */
kPXP_PsPixelFormatUYVY1P422 = 0x12, /*!< 16-bit pixels (1-plane U0,Y0,V0,Y1 interleaved bytes) */
kPXP_PsPixelFormatVYUY1P422 = 0x13, /*!< 16-bit pixels (1-plane V0,Y0,U0,Y1 interleaved bytes) */
kPXP_PsPixelFormatY8 = 0x14, /*!< 8-bit monochrome pixels (1-plane Y luma output) */
kPXP_PsPixelFormatY4 = 0x15, /*!< 4-bit monochrome pixels (1-plane Y luma, 4 bit truncation) */
kPXP_PsPixelFormatYUV2P422 = 0x18, /*!< 16-bit pixels (2-plane UV interleaved bytes) */
kPXP_PsPixelFormatYUV2P420 = 0x19, /*!< 16-bit pixels (2-plane UV) */
kPXP_PsPixelFormatYVU2P422 = 0x1A, /*!< 16-bit pixels (2-plane VU interleaved bytes) */
kPXP_PsPixelFormatYVU2P420 = 0x1B, /*!< 16-bit pixels (2-plane VU) */
kPXP_PsPixelFormatYVU422 = 0x1E, /*!< 16-bit pixels (3-plane) */
kPXP_PsPixelFormatYVU420 = 0x1F, /*!< 16-bit pixels (3-plane) */
#if !(defined(FSL_FEATURE_PXP_HAS_NO_EXTEND_PIXEL_FORMAT) && FSL_FEATURE_PXP_HAS_NO_EXTEND_PIXEL_FORMAT)
#if !(defined(FSL_FEATURE_PXP_V3) && FSL_FEATURE_PXP_V3)
kPXP_PsPixelFormatRGBA8888 = 0x24, /*!< 32-bit pixels with alpha at low 8-bit */
kPXP_PsPixelFormatRGBA5551 = 0x2C, /*!< 16-bit pixels with alpha at low 1-bit. */
kPXP_PsPixelFormatRGBA4444 = 0x2D, /*!< 16-bit pixels with alpha at low 4-bit. */
#endif
#endif
} pxp_ps_pixel_format_t;
/*! @brief PXP process surface buffer YUV format. */
typedef enum _pxp_ps_yuv_format
{
kPXP_PsYUVFormatYUV = 0U, /*!< YUV format. */
kPXP_PsYUVFormatYCbCr, /*!< YCbCr format. */
} pxp_ps_yuv_format_t;
/*! @brief PXP process surface buffer configuration. */
typedef struct _pxp_ps_buffer_config
{
pxp_ps_pixel_format_t pixelFormat; /*!< PS buffer pixel format. */
bool swapByte; /*!< For each 16 bit word, set true to swap the two bytes. */
uint32_t bufferAddr; /*!< Input buffer address for the first panel. */
uint32_t bufferAddrU; /*!< Input buffer address for the second panel. */
uint32_t bufferAddrV; /*!< Input buffer address for the third panel. */
uint16_t pitchBytes; /*!< Number of bytes between two vertically adjacent pixels. */
} pxp_ps_buffer_config_t;
/*! @brief PXP alpha surface buffer pixel format. */
typedef enum _pxp_as_pixel_format
{
kPXP_AsPixelFormatARGB8888 = 0x0, /*!< 32-bit pixels with alpha. */
kPXP_AsPixelFormatRGB888 = 0x4, /*!< 32-bit pixels without alpha (unpacked 24-bit format) */
kPXP_AsPixelFormatARGB1555 = 0x8, /*!< 16-bit pixels with alpha. */
kPXP_AsPixelFormatARGB4444 = 0x9, /*!< 16-bit pixels with alpha. */
kPXP_AsPixelFormatRGB555 = 0xC, /*!< 16-bit pixels without alpha. */
kPXP_AsPixelFormatRGB444 = 0xD, /*!< 16-bit pixels without alpha. */
kPXP_AsPixelFormatRGB565 = 0xE, /*!< 16-bit pixels without alpha. */
#if !(defined(FSL_FEATURE_PXP_HAS_NO_EXTEND_PIXEL_FORMAT) && FSL_FEATURE_PXP_HAS_NO_EXTEND_PIXEL_FORMAT)
#if !(defined(FSL_FEATURE_PXP_V3) && FSL_FEATURE_PXP_V3)
kPXP_AsPixelFormatRGBA8888 = 0x1, /*!< 32-bit pixels with alpha at low 8-bit. */
kPXP_AsPixelFormatRGBA5551 = 0xA, /*!< 16-bit pixels with alpha at low 1-bit. */
kPXP_AsPixelFormatRGBA4444 = 0xB, /*!< 16-bit pixels with alpha at low 4-bit. */
#endif
#endif
} pxp_as_pixel_format_t;
/*! @brief PXP alphs surface buffer configuration. */
typedef struct _pxp_as_buffer_config
{
pxp_as_pixel_format_t pixelFormat; /*!< AS buffer pixel format. */
uint32_t bufferAddr; /*!< Input buffer address. */
uint16_t pitchBytes; /*!< Number of bytes between two vertically adjacent pixels. */
} pxp_as_buffer_config_t;
/*!
* @brief PXP alpha mode during blending.
*/
typedef enum _pxp_alpha_mode
{
kPXP_AlphaEmbedded, /*!< The alpha surface pixel alpha value will be used for blend. */
kPXP_AlphaOverride, /*!< The user defined alpha value will be used for blend directly. */
kPXP_AlphaMultiply, /*!< The alpha surface pixel alpha value scaled the user defined
alpha value will be used for blend, for example, pixel alpha set
set to 200, user defined alpha set to 100, then the reault alpha
is 200 * 100 / 255. */
kPXP_AlphaRop /*!< Raster operation. */
} pxp_alpha_mode_t;
/*!
* @brief PXP ROP mode during blending.
*
* Explanation:
* - AS: Alpha surface
* - PS: Process surface
* - nAS: Alpha surface NOT value
* - nPS: Process surface NOT value
*/
typedef enum _pxp_rop_mode
{
kPXP_RopMaskAs = 0x0, /*!< AS AND PS. */
kPXP_RopMaskNotAs = 0x1, /*!< nAS AND PS. */
kPXP_RopMaskAsNot = 0x2, /*!< AS AND nPS. */
kPXP_RopMergeAs = 0x3, /*!< AS OR PS. */
kPXP_RopMergeNotAs = 0x4, /*!< nAS OR PS. */
kPXP_RopMergeAsNot = 0x5, /*!< AS OR nPS. */
kPXP_RopNotCopyAs = 0x6, /*!< nAS. */
kPXP_RopNot = 0x7, /*!< nPS. */
kPXP_RopNotMaskAs = 0x8, /*!< AS NAND PS. */
kPXP_RopNotMergeAs = 0x9, /*!< AS NOR PS. */
kPXP_RopXorAs = 0xA, /*!< AS XOR PS. */
kPXP_RopNotXorAs = 0xB /*!< AS XNOR PS. */
} pxp_rop_mode_t;
/*!
* @brief PXP alpha surface blending configuration.
*/
typedef struct _pxp_as_blend_config
{
uint8_t alpha; /*!< User defined alpha value, only used when @ref alphaMode is @ref kPXP_AlphaOverride or @ref
kPXP_AlphaRop. */
bool invertAlpha; /*!< Set true to invert the alpha. */
pxp_alpha_mode_t alphaMode; /*!< Alpha mode. */
pxp_rop_mode_t ropMode; /*!< ROP mode, only valid when @ref alphaMode is @ref kPXP_AlphaRop. */
} pxp_as_blend_config_t;
#if defined(FSL_FEATURE_PXP_V3) && FSL_FEATURE_PXP_V3
/*!
* @brief PXP secondary alpha surface blending engine configuration.
*/
typedef struct _pxp_as_blend_secondary_config
{
bool invertAlpha; /*!< Set true to invert the alpha. */
bool ropEnable; /*!< Enable rop mode. */
pxp_rop_mode_t ropMode; /*!< ROP mode, only valid when ropEnable is true. */
} pxp_as_blend_secondary_config_t;
#endif /* FSL_FEATURE_PXP_V3 */
/*! @brief PXP process block size. */
typedef enum _pxp_block_size
{
kPXP_BlockSize8 = 0U, /*!< Process 8x8 pixel blocks. */
kPXP_BlockSize16, /*!< Process 16x16 pixel blocks. */
} pxp_block_size_t;
/*! @brief PXP CSC1 mode. */
typedef enum _pxp_csc1_mode
{
kPXP_Csc1YUV2RGB = 0U, /*!< YUV to RGB. */
kPXP_Csc1YCbCr2RGB, /*!< YCbCr to RGB. */
} pxp_csc1_mode_t;
/*! @brief PXP CSC2 mode. */
typedef enum _pxp_csc2_mode
{
kPXP_Csc2YUV2RGB = 0U, /*!< YUV to RGB. */
kPXP_Csc2YCbCr2RGB, /*!< YCbCr to RGB. */
kPXP_Csc2RGB2YUV, /*!< RGB to YUV. */
kPXP_Csc2RGB2YCbCr, /*!< RGB to YCbCr. */
} pxp_csc2_mode_t;
/*!
* @brief PXP CSC2 configuration.
*
* Converting from YUV/YCbCr color spaces to the RGB color space uses the
* following equation structure:
*
* R = A1(Y+D1) + A2(U+D2) + A3(V+D3)
* G = B1(Y+D1) + B2(U+D2) + B3(V+D3)
* B = C1(Y+D1) + C2(U+D2) + C3(V+D3)
*
* Converting from the RGB color space to YUV/YCbCr color spaces uses the
* following equation structure:
*
* Y = A1*R + A2*G + A3*B + D1
* U = B1*R + B2*G + B3*B + D2
* V = C1*R + C2*G + C3*B + D3
*/
typedef struct _pxp_csc2_config
{
pxp_csc2_mode_t mode; /*!< Convertion mode. */
float A1; /*!< A1. */
float A2; /*!< A2. */
float A3; /*!< A3. */
float B1; /*!< B1. */
float B2; /*!< B2. */
float B3; /*!< B3. */
float C1; /*!< C1. */
float C2; /*!< C2. */
float C3; /*!< C3. */
int16_t D1; /*!< D1. */
int16_t D2; /*!< D2. */
int16_t D3; /*!< D3. */
} pxp_csc2_config_t;
#if !(defined(FSL_FEATURE_PXP_HAS_NO_LUT) && FSL_FEATURE_PXP_HAS_NO_LUT)
/*! @brief PXP LUT lookup mode. */
typedef enum _pxp_lut_lookup_mode
{
kPXP_LutCacheRGB565 = 0U, /*!< LUT ADDR = R[7:3],G[7:2],B[7:3]. Use all 16KB of LUT
for indirect cached 128KB lookup. */
kPXP_LutDirectY8, /*!< LUT ADDR = 16'b0,Y[7:0]. Use the first 256 bytes of LUT.
Only third data path byte is tranformed. */
kPXP_LutDirectRGB444, /*!< LUT ADDR = R[7:4],G[7:4],B[7:4]. Use one 8KB bank of LUT
selected by @ref PXP_Select8kLutBank. */
kPXP_LutDirectRGB454, /*!< LUT ADDR = R[7:4],G[7:3],B[7:4]. Use all 16KB of LUT. */
} pxp_lut_lookup_mode_t;
/*! @brief PXP LUT output mode. */
typedef enum _pxp_lut_out_mode
{
kPXP_LutOutY8 = 1U, /*!< R/Y byte lane 2 lookup, bytes 1,0 bypassed. */
kPXP_LutOutRGBW4444CFA, /*!< Byte lane 2 = CFA_Y8, byte lane 1,0 = RGBW4444. */
kPXP_LutOutRGB888, /*!< RGB565->RGB888 conversion for Gamma correction. */
} pxp_lut_out_mode_t;
/*! @brief PXP LUT 8K bank index used when lookup mode is @ref kPXP_LutDirectRGB444. */
typedef enum _pxp_lut_8k_bank
{
kPXP_Lut8kBank0 = 0U, /*!< The first 8K bank used. */
kPXP_Lut8kBank1, /*!< The second 8K bank used. */
} pxp_lut_8k_bank_t;
/*! @brief PXP LUT configuration. */
typedef struct _pxp_lut_config
{
pxp_lut_lookup_mode_t lookupMode; /*!< Look up mode. */
pxp_lut_out_mode_t outMode; /*!< Out mode. */
uint32_t cfaValue; /*!< The CFA value used when look up mode is @ref kPXP_LutOutRGBW4444CFA. */
} pxp_lut_config_t;
#endif /* FSL_FEATURE_PXP_HAS_NO_LUT */
/*! @brief PXP internal memory. */
typedef enum _pxp_ram
{
kPXP_RamDither0Lut = 0U, /*!< Dither 0 LUT memory. */
kPXP_RamDither1Lut = 3U, /*!< Dither 1 LUT memory. */
kPXP_RamDither2Lut = 4U, /*!< Dither 2 LUT memory. */
#if defined(FSL_FEATURE_PXP_V3) && FSL_FEATURE_PXP_V3
kPXP_RamDither0Err0 = 1U, /*!< Dither 0 ERR0 memory. */
kPXP_RamDither0Err1 = 2U, /*!< Dither 0 ERR1 memory. */
kPXP_RamAluA = 5U, /*!< ALU A instr memory. */
kPXP_RamAluB = 6U, /*!< ALU B instr memory. */
kPXP_WfeAFetch = 7U, /*!< WFE-A fetch memory. */
kPXP_WfeBFetch = 8U, /*!< WFE-B fetch memory. */
#endif /* FSL_FEATURE_PXP_V3 */
} pxp_ram_t;
/*! @brief PXP dither mode. */
enum _pxp_dither_mode
{
kPXP_DitherPassThrough = 0U, /*!< Pass through, no dither. */
kPXP_DitherFloydSteinberg = 1U, /*!< Floyd-Steinberg. For dither engine 0 only. */
kPXP_DitherAtkinson = 2U, /*!< Atkinson. For dither engine 0 only. */
kPXP_DitherOrdered = 3U, /*!< Ordered dither. */
kPXP_DitherQuantOnly = 4U, /*!< No dithering, only quantization. */
kPXP_DitherSierra = 5U, /*!< Sierra. For dither engine 0 only. */
};
/*! @brief PXP dither LUT mode. */
enum _pxp_dither_lut_mode
{
kPXP_DitherLutOff = 0U, /*!< The LUT memory is not used for LUT, could be used as ordered dither index matrix. */
kPXP_DitherLutPreDither, /*!< Use LUT at the pre-dither stage, The pre-dither LUT could only be used in Floyd mode
or Atkinson mode, which are not supported by current PXP module. */
kPXP_DitherLutPostDither, /*!< Use LUT at the post-dither stage. */
};
/*! @brief PXP dither matrix size. */
enum _pxp_dither_matrix_size
{
kPXP_DitherMatrix4 = 0, /*!< The dither index matrix is 4x4. */
kPXP_DitherMatrix8, /*!< The dither index matrix is 8x8. */
kPXP_DitherMatrix16, /*!< The dither index matrix is 16x16. */
};
/*! @brief PXP dither final LUT data. */
typedef struct _pxp_dither_final_lut_data
{
uint32_t data_3_0; /*!< Data 3 to data 0. Data 0 is the least significant byte. */
uint32_t data_7_4; /*!< Data 7 to data 4. Data 4 is the least significant byte. */
uint32_t data_11_8; /*!< Data 11 to data 8. Data 8 is the least significant byte. */
uint32_t data_15_12; /*!< Data 15 to data 12. Data 12 is the least significant byte. */
} pxp_dither_final_lut_data_t;
/*! @brief PXP dither configuration. */
typedef struct _pxp_dither_config
{
uint32_t enableDither0 : 1; /*!< Enable dither engine 0 or not, set 1 to enable, 0 to disable. */
uint32_t enableDither1 : 1; /*!< Enable dither engine 1 or not, set 1 to enable, 0 to disable. */
uint32_t enableDither2 : 1; /*!< Enable dither engine 2 or not, set 1 to enable, 0 to disable. */
uint32_t ditherMode0 : 3; /*!< Dither mode for dither engine 0. See @ref _pxp_dither_mode. */
uint32_t ditherMode1 : 3; /*!< Dither mode for dither engine 1. See @ref _pxp_dither_mode. */
uint32_t ditherMode2 : 3; /*!< Dither mode for dither engine 2. See @ref _pxp_dither_mode. */
uint32_t quantBitNum : 3; /*!< Number of bits quantize down to, the valid value is 1~7. */
uint32_t lutMode : 2; /*!< How to use the memory LUT, see @ref _pxp_dither_lut_mode. This must be set to @ref
kPXP_DitherLutOff
if any dither engine uses @ref kPXP_DitherOrdered mode. */
uint32_t idxMatrixSize0 : 2; /*!< Size of index matrix used for dither for dither engine 0, see @ref
_pxp_dither_matrix_size. */
uint32_t idxMatrixSize1 : 2; /*!< Size of index matrix used for dither for dither engine 1, see @ref
_pxp_dither_matrix_size. */
uint32_t idxMatrixSize2 : 2; /*!< Size of index matrix used for dither for dither engine 2, see @ref
_pxp_dither_matrix_size. */
uint32_t enableFinalLut : 1; /*!< Enable the final LUT, set 1 to enable, 0 to disable. */
uint32_t : 8;
} pxp_dither_config_t;
/*!
* @brief Porter Duff factor mode.
* @anchor pxp_porter_duff_factor_mode
*/
enum
{
kPXP_PorterDuffFactorOne = 0U, /*!< Use 1. */
kPXP_PorterDuffFactorZero, /*!< Use 0. */
kPXP_PorterDuffFactorStraight, /*!< Use straight alpha. */
kPXP_PorterDuffFactorInversed, /*!< Use inversed alpha. */
};
/*!
* @brief Porter Duff global alpha mode.
* @anchor pxp_porter_duff_global_alpha_mode
*/
enum
{
kPXP_PorterDuffGlobalAlpha = 0U, /*!< Use global alpha. */
kPXP_PorterDuffLocalAlpha, /*!< Use local alpha in each pixel. */
kPXP_PorterDuffScaledAlpha, /*!< Use global alpha * local alpha. */
};
/*!
* @brief Porter Duff alpha mode.
* @anchor pxp_porter_duff_alpha_mode
*/
enum
{
kPXP_PorterDuffAlphaStraight = 0U, /*!< Use straight alpha, s0_alpha' = s0_alpha. */
kPXP_PorterDuffAlphaInversed /*!< Use inversed alpha, s0_alpha' = 0xFF - s0_alpha. */
};
/*!
* @brief Porter Duff color mode.
* @anchor pxp_porter_duff_color_mode
*/
enum
{
kPXP_PorterDuffColorStraight = 0, /*!< @deprecated Use kPXP_PorterDuffColorNoAlpha. */
kPXP_PorterDuffColorInversed = 1, /*!< @deprecated Use kPXP_PorterDuffColorWithAlpha. */
kPXP_PorterDuffColorNoAlpha = 0, /*!< s0_pixel' = s0_pixel. */
kPXP_PorterDuffColorWithAlpha = 1, /*!< s0_pixel' = s0_pixel * s0_alpha". */
};
/*! @brief PXP Porter Duff configuration. */
typedef struct
{
uint32_t enable : 1; /*!< Enable or disable Porter Duff. */
uint32_t srcFactorMode : 2; /*!< Source layer (or AS, s1) factor mode, see @ref pxp_porter_duff_factor_mode. */
uint32_t dstGlobalAlphaMode : 2; /*!< Destination layer (or PS, s0) global alpha mode, see
@ref pxp_porter_duff_global_alpha_mode. */
uint32_t dstAlphaMode : 1; /*!< Destination layer (or PS, s0) alpha mode, see @ref pxp_porter_duff_alpha_mode. */
uint32_t dstColorMode : 1; /*!< Destination layer (or PS, s0) color mode, see @ref pxp_porter_duff_color_mode. */
uint32_t : 1;
uint32_t dstFactorMode : 2; /*!< Destination layer (or PS, s0) factor mode, see @ref pxp_porter_duff_factor_mode. */
uint32_t srcGlobalAlphaMode : 2; /*!< Source layer (or AS, s1) global alpha mode, see
@ref pxp_porter_duff_global_alpha_mode. */
uint32_t srcAlphaMode : 1; /*!< Source layer (or AS, s1) alpha mode, see @ref pxp_porter_duff_alpha_mode. */
uint32_t srcColorMode : 1; /*!< Source layer (or AS, s1) color mode, see @ref pxp_porter_duff_color_mode. */
uint32_t : 2;
uint32_t dstGlobalAlpha : 8; /*!< Destination layer (or PS, s0) global alpha value, 0~255. */
uint32_t srcGlobalAlpha : 8; /*!< Source layer (or AS, s1) global alpha value, 0~255. */
} pxp_porter_duff_config_t;
/*! @brief PXP Porter Duff blend mode. Note: don't change the enum item value */
typedef enum _pxp_porter_duff_blend_mode
{
kPXP_PorterDuffSrc = 0, /*!< Source Only */
kPXP_PorterDuffAtop, /*!< Source Atop */
kPXP_PorterDuffOver, /*!< Source Over */
kPXP_PorterDuffIn, /*!< Source In. */
kPXP_PorterDuffOut, /*!< Source Out. */
kPXP_PorterDuffDst, /*!< Destination Only. */
kPXP_PorterDuffDstAtop, /*!< Destination Atop. */
kPXP_PorterDuffDstOver, /*!< Destination Over. */
kPXP_PorterDuffDstIn, /*!< Destination In. */
kPXP_PorterDuffDstOut, /*!< Destination Out. */
kPXP_PorterDuffXor, /*!< XOR. */
kPXP_PorterDuffClear, /*!< Clear. */
kPXP_PorterDuffMax,
} pxp_porter_duff_blend_mode_t;
/*! @brief PXP Porter Duff blend mode. Note: don't change the enum item value */
typedef struct _pxp_pic_copy_config
{
uint32_t srcPicBaseAddr; /*!< Source picture base address. */
uint16_t srcPitchBytes; /*!< Pitch of the source buffer. */
uint16_t srcOffsetX; /*!< Copy position in source picture. */
uint16_t srcOffsetY; /*!< Copy position in source picture. */
uint32_t destPicBaseAddr; /*!< Destination picture base address. */
uint16_t destPitchBytes; /*!< Pitch of the destination buffer. */
uint16_t destOffsetX; /*!< Copy position in destination picture. */
uint16_t destOffsetY; /*!< Copy position in destination picture. */
uint16_t width; /*!< Pixel number each line to copy. */
uint16_t height; /*!< Lines to copy. */
pxp_as_pixel_format_t pixelFormat; /*!< Buffer pixel format. */
} pxp_pic_copy_config_t;
#if defined(FSL_FEATURE_PXP_V3) && FSL_FEATURE_PXP_V3
/*!
* @brief PXP process engine enumeration
*/
typedef enum _pxp_process_engine_name
{
kPXP_PsAsOutEngine = PXP_CTRL_ENABLE_PS_AS_OUT_MASK,
kPXP_DitherEngine = PXP_CTRL_ENABLE_DITHER_MASK,
kPXP_WfeaEngine = PXP_CTRL_ENABLE_WFE_A_MASK,
kPXP_WfebEngine = PXP_CTRL_ENABLE_WFE_B_MASK,
kPXP_InputFetchStoreEngine = PXP_CTRL_ENABLE_INPUT_FETCH_STORE_MASK,
kPXP_Alpha1Engine = PXP_CTRL_ENABLE_ALPHA_B_MASK,
kPXP_Csc2Engine = PXP_CTRL_ENABLE_CSC2_MASK,
kPXP_LutEngine = PXP_CTRL_ENABLE_LUT_MASK,
kPXP_Rotate0Engine = PXP_CTRL_ENABLE_ROTATE0_MASK,
kPXP_Rotate1Engine = PXP_CTRL_ENABLE_ROTATE1_MASK,
} pxp_process_engine_name_t;
/* Fetch engine configuration. */
/*!
* @brief PXP fetch engine enumeration
*
* There are actually 4 fetch engine implemented, the others are WFE-A fetch engine and WFE-B fetch engine,
* whose registers are reserved from developer.
*/
typedef enum _pxp_fetch_engine_name
{
kPXP_FetchInput,
kPXP_FetchDither,
} pxp_fetch_engine_name_t;
/*! @brief PXP fetch engine interface mode with the upstream store engine. */
typedef enum _pxp_fetch_interface_mode
{
kPXP_FetchModeNormal = 0U,
kPXP_FetchModeHandshake = 0x1U,
kPXP_FetchModeBypass = 0x2U,
} pxp_fetch_interface_mode_t;
/*! @brief PXP fetch/store engine burst length for scanline mode. */
typedef enum _pxp_scanline_burst
{
kPXP_Scanline8bytes,
kPXP_Scanline16bytes,
kPXP_Scanline32bytes,
kPXP_Scanline64bytes,
} pxp_scanline_burst_t;
/*! @brief PXP fetch engine block configuration. */
typedef struct _pxp_block_format_config
{
bool
enableblock; /*!< Enable to use block mode instead of scanline mode. Note: 1.Make sure to enable if rotate or
flip mode is enabled. 2.Block mode cannot work on 64bpp data stream where activeBits = 64. 3. If
LUT processing is in the path between the fetch and store engind, block mode must be enabled. */
bool blockSize16; /*!< Enable to use 16*16 block, otherwise it will be 8*8 block. */
pxp_scanline_burst_t burstLength; /*!< When using scanline mode, configure this for burst length. */
} pxp_block_config_t;
/*!
* @brief PXP fetch/store engine input/output active bits configuration.
*
* Since fetch engine is 64-bit input and 32-bit output per channel, need to configure both channels to use 64-bit input
* mode. And expand configuration will have no effect.
*/
typedef enum _pxp_activeBits
{
kPXP_Active8Bits = 0x0,
kPXP_Active16Bits = 0x1,
kPXP_Active32Bits = 0x2,
kPXP_Active64Bits = 0x3,
} pxp_active_bits_t;
/*! @brief PXP fetch engine output word order when using 2 channels for 64-bit mode. */
typedef enum _pxp_fetch_output_word_order
{
kPXP_FetchOutputChannel1channel0 = 0x0, /*!< In 64bit mode, channel 1 output high byte. */
kPXP_FetchOutputChannel0channel1 = 0x1, /*!< In 64bit mode, channel 0 output high byte. */
} pxp_fetch_output_word_order_t;
/*!
* @brief PXP fetch engine shift component configuration.
*
* Fetch engine can divded each word into 4 components and shift them.
*/
typedef struct _pxp_fetch_shift_component
{
uint8_t offset;
uint8_t width;
} pxp_fetch_shift_component_t;
/*!
* @brief PXP fetch engine shift configuration.
*
* Fetch engine can divded each word into 4 components and shift them.
* For example, to change YUV444 to YVU444, U and V positions need to be shifted: OFFSET0=8, OFFSET1=0, OFFSET2=16,
* OFFSET3=24, WIDTH0/1/2/3=8
*/
typedef struct _pxp_fetch_shift_config
{
bool shiftBypass; /* Bypass the shift */
pxp_fetch_shift_component_t component0;
pxp_fetch_shift_component_t component1;
pxp_fetch_shift_component_t component2;
pxp_fetch_shift_component_t component3;
} pxp_fetch_shift_config_t;
/*! @brief PXP fetch engine input pixel format. */
typedef enum _pxp_fetch_pixel_format
{
kPXP_FetchFormatRGB565 = 0x0,
kPXP_FetchFormatRGB555 = 0x1,
kPXP_FetchFormatARGB1555 = 0x2,
kPXP_FetchFormatRGB444 = 0x3,
kPXP_FetchFormatARGB4444 = 0x4,
kPXP_FetchFormatYUYVorYVYU = 0x5,
kPXP_FetchFormatUYVYorVYUY = 0x6,
kPXP_FetchFormatYUV422_2P = 0x7,
} pxp_fetch_pixel_format_t;
/*! @brief PXP fetch engine configuration for one of the channel. */
typedef struct _pxp_fetch_engine_config
{
bool channelEnable; /*!< Enable channel. */
/* Address configuration */
uint32_t inputBaseAddr0; /*!< The input base address. Used for Y plane input when pixel format is YUV422_2p. */
uint32_t inputBaseAddr1; /*!< Must configure this for UV plane when input pixel format is YUV422_2p. */
/* Size configuration */
uint16_t totalHeight; /*!< Total height for the actual fetch size. */
uint16_t totalWidth; /*!< Total width for the actual fetch size. */
uint16_t pitchBytes; /*!< Channel input pitch */
uint16_t ulcX; /*!< X coordinate of upper left coordinate in pixels of the active area of the total input memory */
uint16_t ulcY; /*!< Y coordinate of upper left coordinate in pixels of the active area of the total input memory */
uint16_t lrcX; /*!< X coordinate of Lower right coordinate in pixels of the active area of the total input memory */
uint16_t lrcY; /*!< Y coordinate of Lower right coordinate in pixels of the active area of the total input memory */
uint32_t backGroundColor; /*!< Pixel value of the background color for the space outside the active area. */
/* Interface configuration */
pxp_fetch_interface_mode_t interface; /*!< Interface mode, normal/bypass/handshake */
/* Pixel configuration */
pxp_active_bits_t activeBits; /*!< Input active bits. */
pxp_fetch_pixel_format_t pixelFormat; /*!< Input pixel fetch format */
bool expandEnable; /*!< If enabled, input pixel will be expanded to ARGB8888, RGB888 or YUV444 of 32-bit format at
the output. */
/* Fetch format configuration */
pxp_flip_mode_t flipMode; /*!< Flip the fetched input. */
pxp_rotate_degree_t rotateDegree; /*!< Rotate the fetched input. */
pxp_block_config_t
fetchFormat; /*!< Block mode configuration. Make sure to enable block if rotate or flip mode is enabled. */
/* Output configuration. */
pxp_fetch_shift_config_t shiftConfig; /*!< Shift operation configuration. */
pxp_fetch_output_word_order_t wordOrder; /*!< Output word order when using 2 channels for 64-bit mode. */
} pxp_fetch_engine_config_t;
/* Store engine configuration. */
/*!
* @brief PXP store engine enumeration
*
* There are actually 4 store engine implemented, the others are WFE-A store engine and WFE-B store engine,
* whose registers are reserved from developer.
*/
typedef enum _pxp_store_engine_name
{
kPXP_StoreInput,
kPXP_StoreDither,
} pxp_store_engine_name_t;
/*! @brief PXP store engine interface mode with the downstream fetch engine. */
typedef enum _pxp_store_interface_mode
{
kPXP_StoreModeBypass = 0x20U, /*!< Store engine output the input data, after the shift function directly to the
downstream Fetch Engine. */
kPXP_StoreModeNormal = 0x40U, /*!< Store engine stores the input data to memory. */
kPXP_StoreModeHandshake = 0x43U, /*!< Downstream fetch engine fetch data per scanline from memory using buffer
sharing with store engine. */
kPXP_StoreModeDual = 0x60U, /*!< Store engine outputs data directly to downstream fetch engine(Bypass) but also
storing it to memory at the same time. */
} pxp_store_interface_mode_t;
/*! @brief PXP store engine YUV output mode. */
typedef enum _pxp_store_yuv_mode
{
kPXP_StoreYUVDisable = 0U, /*!< Do not output YUV pixel format. */
kPXP_StoreYUVPlane1 =
0x1U, /*!< Use channel to output YUV422_1p pixel format, need to use shift operation to make sure each pixel
component in its proper position: 64-bits of pixel data format and each 32 bits as {Y0, U0, Y1, V0}. */
kPXP_StoreYUVPlane2 =
0x2U, /*!< Use channel to output YUV422_2p pixel format, need to use shift operation to make sure each pixel
component in its proper position: channel 0 {Y0,Y1}, channel 1 {U0,V0}. */
} pxp_store_yuv_mode_t;
/*! @brief Shift configuration for PXP store engine. */
typedef struct _pxp_store_shift_config
{
/* Data/Flag shift */
bool shiftBypass; /*!< Bypass the data shift */
uint64_t *pDataShiftMask; /*!< Pointer to mask0~mask7 to mask the 64-bit of output data, data is masked first then
shifted according to width. */
uint8_t *pDataShiftWidth; /*!< Pointer to width0~width7. Bit 7 is for shifted direction, 0 to right. Bit0~5 is for
shift width. */
uint8_t *pFlagShiftMask; /*!< Pointer to mask0~mask7 to mask the 8-bit of output flag, flag is masked first then
shifted according to width. */
uint8_t *pFlagShiftWidth; /*!< Pointer to width0~width7. Bit 6 is for shifted direction, 0 to right. Bit0~5 is for
shift width. */
} pxp_store_shift_config_t;
/*! @brief PXP store engine configuration for one of the channel. */
typedef struct _pxp_store_engine_config
{
bool channelEnable; /*!< Enable channel. */
/* Address configuration */
uint32_t outputBaseAddr0; /*!< The channel 0 output address if using 2 channels. If using 1 channel(must be channel
0) and YUV422_2p output format, is for Y plane address. */
uint32_t outputBaseAddr1; /*!< The channel 1 output address if using 2 channels. If using 1 channel(must be channel
0) and YUV422_2p output format, is for UV plane address. */
/* Size configuration */
uint16_t totalHeight; /*!< Total height for the actual store size. */
uint16_t totalWidth; /*!< Total width for the actual store size. */
uint16_t pitchBytes; /*!< Channel input pitch */
/* Interface configuration */
pxp_store_interface_mode_t interface; /*!< Interface mode, normal/bypass/handshake/dual. Make sure 2 channels use
the same mode if both enabled. */
/* pxp_store_handshake_array_t arraySize; !< If interfase mode is handshake, need to configure the array size. When
block is disabled, the scanline can only be 1. TODO no need now. */
/* Pixel configuration */
pxp_active_bits_t activeBits; /*!< Output active bits. */
pxp_store_yuv_mode_t yuvMode; /*!< Whether to output YUV pixel format. */
/* Fixed data configuration, only apply for channel 0. */
bool useFixedData; /*!< Whether to use fixed value for the output data. Can be used to write fixed value to specific
memory location for memory initialization. */
uint32_t fixedData; /*!< The value of the fixed data. */
/* Data packing */
bool packInSelect; /*!< When enabled, channel 0 will select low 32 bit shift out data to pack while channel i select
high 32 bit, otherwise all 64-bit of data will be selected. */
/* Data store format */
pxp_block_config_t storeFormat; /*!< The format to store data, block or otherwise. */
pxp_store_shift_config_t shiftConfig; /*!< Shift operation configuration. */
} pxp_store_engine_config_t;
/* Pre-dither CFA engine configuration */
/*! @brief PXP pre-dither CFA engine input pixel format. */
typedef enum _pxp_cfa_input_format
{