-
Notifications
You must be signed in to change notification settings - Fork 1.1k
/
opam
36 lines (36 loc) · 1.32 KB
/
opam
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
opam-version: "2.0"
maintainer: "Jane Street developers"
authors: ["Jane Street Group, LLC"]
homepage: "https://github.com/janestreet/hardcaml"
bug-reports: "https://github.com/janestreet/hardcaml/issues"
dev-repo: "git+https://github.com/janestreet/hardcaml.git"
doc: "https://ocaml.janestreet.com/ocaml-core/latest/doc/hardcaml/index.html"
license: "MIT"
build: [
["dune" "build" "-p" name "-j" jobs]
]
depends: [
"ocaml" {>= "4.07.0"}
"base" {>= "v0.12" & < "v0.13"}
"ppx_jane" {>= "v0.12" & < "v0.13"}
"stdio" {>= "v0.12" & < "v0.13"}
"topological_sort" {>= "v0.12" & < "v0.13"}
"dune" {>= "1.5.1"}
"zarith" {>= "1.5"}
]
synopsis: "RTL Hardware Design in OCaml"
description: "
Hardcaml is an embedded DSL for designing and simulating hardware in OCaml.
Generic hardware designs are easily expressed using features such as higher
order functions, lists, maps etc. A built in simulator allows designs to
be simulated within Hardcaml. Designs are converted to either Verilog or
VHDL to interact with standard back end tooling.
"
url {
src:
"https://ocaml.janestreet.com/ocaml-core/v0.12/files/hardcaml-v0.12.0.tar.gz"
checksum: [
"sha256=1bef834dd9105c26530600cd6a211727004af0741fe39376682fb833fda8b918"
"md5=bddd766d20ca9d90d3d4d0d521e0d2b2"
]
}