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opam
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opam-version: "2.0"
maintainer: "Jane Street developers"
authors: ["Jane Street Group, LLC"]
homepage: "https://github.com/janestreet/hardcaml_of_verilog"
bug-reports: "https://github.com/janestreet/hardcaml_of_verilog/issues"
dev-repo: "git+https://github.com/janestreet/hardcaml_of_verilog.git"
doc: "https://ocaml.janestreet.com/ocaml-core/latest/doc/hardcaml_of_verilog/index.html"
license: "MIT"
build: [
["dune" "build" "-p" name "-j" jobs]
]
depends: [
"ocaml" {>= "5.1.0"}
"base" {>= "v0.17" & < "v0.18"}
"core" {>= "v0.17" & < "v0.18"}
"core_unix" {>= "v0.17" & < "v0.18"}
"hardcaml" {>= "v0.17" & < "v0.18"}
"hardcaml_verify" {>= "v0.17" & < "v0.18"}
"jsonaf" {>= "v0.17" & < "v0.18"}
"ppx_hardcaml" {>= "v0.17" & < "v0.18"}
"ppx_jane" {>= "v0.17" & < "v0.18"}
"ppx_jsonaf_conv" {>= "v0.17" & < "v0.18"}
"stdio" {>= "v0.17" & < "v0.18"}
"dune" {>= "3.11.0"}
]
available: arch != "arm32" & arch != "x86_32"
synopsis: "Convert Verilog to a Hardcaml design"
description: "
The opensource synthesis tool yosys is used to convert a verilog design to a JSON based
netlist representation. This library can load the JSON netlist and build a hardcaml
circuit.
Code can also be generated to wrap the conversion process using Hardcaml interfaces.
"
url {
src: "https://github.com/janestreet/hardcaml_of_verilog/archive/refs/tags/v0.17.0.tar.gz"
checksum: "sha256=8603da93ce48dc3e550043310ab3b5c0da3bc19f04391ade7bcc8c46dc3e612d"
}