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The wong code is this:
const ucg_pgm_uint8_t ucg_ssd1331_set_pos_dir0_seq[] =
{
UCG_CS(0), /* enable chip /
UCG_C10(0x015), UCG_VARX(0,0x0ff, 0), UCG_D1(0x07f), / set x position /
UCG_C10(0x075), UCG_VARY(0,0x0ff, 0), UCG_VARY(0,0x0ff, 0), / set y position /
UCG_DATA(), / change to data mode */
UCG_END()
};
Correct code should be:
const ucg_pgm_uint8_t ucg_ssd1331_set_pos_dir0_seq[] =
{
UCG_CS(0), /* enable chip /
UCG_C10(0x015), UCG_VARX(0,0x0ff, 0), UCG_A1(0x07f), / set x position /
UCG_C10(0x075), UCG_VARY(0,0x0ff, 0), UCG_VARY(0,0x0ff, 0), / set y position /
UCG_DATA(), / change to data mode */
UCG_END()
};
ucg_dev_ic_ili9163.c
ucg_dev_ic_ili9325_spi.c
ucg_dev_ic_ld50t6160.c
ucg_dev_ic_ssd1289.c
ucg_dev_ic_ssd1351.c
ucg_dev_ic_ili9325.c
ucg_dev_ic_ili9341.c
ucg_dev_ic_pcf8833.c
ucg_dev_ic_ssd1331.c --> fixed & tested
ucg_dev_ic_st7735.c
Some speed optimization might be possible: CD line is set too often here
The text was updated successfully, but these errors were encountered:
The wong code is this:
const ucg_pgm_uint8_t ucg_ssd1331_set_pos_dir0_seq[] =
{
UCG_CS(0), /* enable chip /
UCG_C10(0x015), UCG_VARX(0,0x0ff, 0), UCG_D1(0x07f), / set x position /
UCG_C10(0x075), UCG_VARY(0,0x0ff, 0), UCG_VARY(0,0x0ff, 0), / set y position /
UCG_DATA(), / change to data mode */
UCG_END()
};
Correct code should be:
const ucg_pgm_uint8_t ucg_ssd1331_set_pos_dir0_seq[] =
{
UCG_CS(0), /* enable chip /
UCG_C10(0x015), UCG_VARX(0,0x0ff, 0), UCG_A1(0x07f), / set x position /
UCG_C10(0x075), UCG_VARY(0,0x0ff, 0), UCG_VARY(0,0x0ff, 0), / set y position /
UCG_DATA(), / change to data mode */
UCG_END()
};
Some speed optimization might be possible: CD line is set too often here
The text was updated successfully, but these errors were encountered: