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That would be a good addition. Unfortunately I know too little about Vivado HLS. Wondering if it would be best done as a completely new edalize backend or if it would be better to have as a generator that just compiles the code to RTL and reuses the rest of the infrastructure after that
Wondering if it would be best done as a completely new edalize backend or if it would be better to have as a generator that just compiles the code to RTL and reuses the rest of the infrastructure after that
I think that this depends on the project. It is possible to export HLS designs to RTL (VHDL) and then simulate them with GHDL + VUnit verification components. However, the software partition might need rewriting.
I think it might be interesting to integrate hlsclt ( https://github.com/benjmarshall/hlsclt ) to have support for Vivado HLS.
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