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Lint error "Unnamed generate block" #110

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monstrous-moonshine opened this issue Nov 15, 2023 · 3 comments
Closed

Lint error "Unnamed generate block" #110

monstrous-moonshine opened this issue Nov 15, 2023 · 3 comments

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@monstrous-moonshine
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Running the following command produces lint errors from Verilator:

$ fusesoc run --target=lint serv
INFO: Preparing ::serv:1.2.1
INFO: Setting up project
INFO: Building simulation model
INFO: verilator -f serv_1.2.1.vc -Wall

ERROR: %Warning-GENUNNAMED: src/serv_1.2.1/rtl/serv_rf_ram_if.v:65:29: Unnamed generate block 'genblk1' (IEEE 1800-2017 27.6)
                                                              : ... Suggest assign a label with 'begin : gen_<label_name>'
   65 |    generate if (width == 2) begin
      |                             ^~~~~
                     ... For warning description see https://verilator.org/warn/GENUNNAMED?v=5.018
                     ... Use "/* verilator lint_off GENUNNAMED */" and lint_on around source to disable this message.
%Warning-GENUNNAMED: src/serv_1.2.1/rtl/serv_rf_ram_if.v:67:13: Unnamed generate block 'genblk1' (IEEE 1800-2017 27.6)
                                                              : ... Suggest assign a label with 'begin : gen_<label_name>'
   67 |    end else begin
      |             ^~~~~
%Warning-GENUNNAMED: src/serv_1.2.1/rtl/serv_rf_ram_if.v:80:21: Unnamed generate block 'genblk2' (IEEE 1800-2017 27.6)
                                                              : ... Suggest assign a label with 'begin : gen_<label_name>'
   80 |      assign o_waddr = wreg;
      |                     ^
%Warning-GENUNNAMED: src/serv_1.2.1/rtl/serv_rf_ram_if.v:82:21: Unnamed generate block 'genblk2' (IEEE 1800-2017 27.6)
                                                              : ... Suggest assign a label with 'begin : gen_<label_name>'
   82 |      assign o_waddr = {wreg, wcnt[4:l2w]};
      |                     ^
%Warning-GENUNNAMED: src/serv_1.2.1/rtl/serv_rf_ram_if.v:109:21: Unnamed generate block 'genblk3' (IEEE 1800-2017 27.6)
                                                               : ... Suggest assign a label with 'begin : gen_<label_name>'
  109 |      assign o_raddr = rreg;
      |                     ^
%Warning-GENUNNAMED: src/serv_1.2.1/rtl/serv_rf_ram_if.v:111:21: Unnamed generate block 'genblk3' (IEEE 1800-2017 27.6)
                                                               : ... Suggest assign a label with 'begin : gen_<label_name>'
  111 |      assign o_raddr = {rreg, rcnt[4:l2w]};
      |                     ^
%Warning-GENUNNAMED: src/serv_1.2.1/rtl/serv_rf_ram_if.v:125:19: Unnamed generate block 'genblk4' (IEEE 1800-2017 27.6)
                                                               : ... Suggest assign a label with 'begin : gen_<label_name>'
  125 |      assign o_ren = rgate;
      |                   ^
%Warning-GENUNNAMED: src/serv_1.2.1/rtl/serv_rf_ram_if.v:127:19: Unnamed generate block 'genblk4' (IEEE 1800-2017 27.6)
                                                               : ... Suggest assign a label with 'begin : gen_<label_name>'
  127 |      assign o_ren = rgate & (rcnt[l2w-1:1] == 0);
      |                   ^
%Warning-GENUNNAMED: src/serv_1.2.1/rtl/serv_rf_ram_if.v:133:6: Unnamed generate block 'genblk5' (IEEE 1800-2017 27.6)
                                                              : ... Suggest assign a label with 'begin : gen_<label_name>'
  133 |      always @(posedge i_clk) begin
      |      ^~~~~~
%Warning-GENUNNAMED: src/serv_1.2.1/rtl/serv_rf_ram_if.v:139:6: Unnamed generate block 'genblk5' (IEEE 1800-2017 27.6)
                                                              : ... Suggest assign a label with 'begin : gen_<label_name>'
  139 |      always @(posedge i_clk) if (rtrig1) rdata1 <= i_rdata[1];
      |      ^~~~~~
%Warning-GENUNNAMED: src/serv_1.2.1/rtl/serv_top.v:185:18: Unnamed generate block 'genblk1' (IEEE 1800-2017 27.6)
                                                         : ... Suggest assign a label with 'begin : gen_<label_name>'
  185 |       if (ALIGN) begin
      |                  ^~~~~
%Warning-GENUNNAMED: src/serv_1.2.1/rtl/serv_top.v:200:16: Unnamed generate block 'genblk1' (IEEE 1800-2017 27.6)
                                                         : ... Suggest assign a label with 'begin : gen_<label_name>'
  200 |       end else begin
      |                ^~~~~
%Warning-GENUNNAMED: src/serv_1.2.1/rtl/serv_top.v:209:23: Unnamed generate block 'genblk2' (IEEE 1800-2017 27.6)
                                                         : ... Suggest assign a label with 'begin : gen_<label_name>'
  209 |       if (COMPRESSED) begin
      |                       ^~~~~
%Warning-GENUNNAMED: src/serv_1.2.1/rtl/serv_top.v:217:16: Unnamed generate block 'genblk2' (IEEE 1800-2017 27.6)
                                                         : ... Suggest assign a label with 'begin : gen_<label_name>'
  217 |       end else begin
      |                ^~~~~
%Warning-GENUNNAMED: src/serv_1.2.1/rtl/serv_top.v:536:22: Unnamed generate block 'genblk3' (IEEE 1800-2017 27.6)
                                                         : ... Suggest assign a label with 'begin : gen_<label_name>'
  536 |       if (|WITH_CSR) begin
      |                      ^~~~~
%Warning-GENUNNAMED: src/serv_1.2.1/rtl/serv_top.v:570:16: Unnamed generate block 'genblk3' (IEEE 1800-2017 27.6)
                                                         : ... Suggest assign a label with 'begin : gen_<label_name>'
  570 |       end else begin
      |                ^~~~~
%Warning-GENUNNAMED: src/serv_1.2.1/rtl/serv_top.v:648:12: Unnamed generate block 'genblk4' (IEEE 1800-2017 27.6)
                                                         : ... Suggest assign a label with 'begin : gen_<label_name>'
  648 |   if (MDU) begin
      |            ^~~~~
%Warning-GENUNNAMED: src/serv_1.2.1/rtl/serv_top.v:651:12: Unnamed generate block 'genblk4' (IEEE 1800-2017 27.6)
                                                         : ... Suggest assign a label with 'begin : gen_<label_name>'
  651 |   end else begin
      |            ^~~~~
%Warning-GENUNNAMED: src/serv_1.2.1/rtl/serv_alu.v:63:39: Unnamed generate block 'genblk1' (IEEE 1800-2017 27.6)
                                                        : ... Suggest assign a label with 'begin : gen_<label_name>'
   63 |       if (W>1) assign result_slt[B:1] = '0;
      |                                       ^
%Warning-GENUNNAMED: src/serv_1.2.1/rtl/serv_ctrl.v:57:16: Unnamed generate block 'genblk1' (IEEE 1800-2017 27.6)
                                                         : ... Suggest assign a label with 'begin : gen_<label_name>'
   57 |  assign new_pc = i_trap ? (i_csr_pc & !i_cnt0) : i_jump ? pc_plus_offset_aligned : pc_plus_4;
      |                ^
%Warning-GENUNNAMED: src/serv_1.2.1/rtl/serv_ctrl.v:59:16: Unnamed generate block 'genblk1' (IEEE 1800-2017 27.6)
                                                         : ... Suggest assign a label with 'begin : gen_<label_name>'
   59 |  assign new_pc = i_jump ? pc_plus_offset_aligned : pc_plus_4;
      |                ^
%Warning-GENUNNAMED: src/serv_1.2.1/rtl/serv_decode.v:236:25: Unnamed generate block 'genblk1' (IEEE 1800-2017 27.6)
                                                            : ... Suggest assign a label with 'begin : gen_<label_name>'
  236 |       if (PRE_REGISTER) begin
      |                         ^~~~~
%Warning-GENUNNAMED: src/serv_1.2.1/rtl/serv_decode.v:299:16: Unnamed generate block 'genblk1' (IEEE 1800-2017 27.6)
                                                            : ... Suggest assign a label with 'begin : gen_<label_name>'
  299 |       end else begin
      |                ^~~~~
%Warning-GENUNNAMED: src/serv_1.2.1/rtl/serv_immdec.v:36:35: Unnamed generate block 'genblk1' (IEEE 1800-2017 27.6)
                                                           : ... Suggest assign a label with 'begin : gen_<label_name>'
   36 |       if (SHARED_RFADDR_IMM_REGS) begin
      |                                   ^~~~~
%Warning-GENUNNAMED: src/serv_1.2.1/rtl/serv_immdec.v:60:16: Unnamed generate block 'genblk1' (IEEE 1800-2017 27.6)
                                                           : ... Suggest assign a label with 'begin : gen_<label_name>'
   60 |       end else begin
      |                ^~~~~
%Warning-GENUNNAMED: src/serv_1.2.1/rtl/serv_rf_if.v:56:19: Unnamed generate block 'genblk1' (IEEE 1800-2017 27.6)
                                                          : ... Suggest assign a label with 'begin : gen_<label_name>'
   56 |    if (|WITH_CSR) begin
      |                   ^~~~~
%Warning-GENUNNAMED: src/serv_1.2.1/rtl/serv_rf_if.v:122:13: Unnamed generate block 'genblk1' (IEEE 1800-2017 27.6)
                                                           : ... Suggest assign a label with 'begin : gen_<label_name>'
  122 |    end else begin
      |             ^~~~~
%Warning-GENUNNAMED: src/serv_1.2.1/rtl/serv_state.v:207:21: Unnamed generate block 'genblk1' (IEEE 1800-2017 27.6)
                                                           : ... Suggest assign a label with 'begin : gen_<label_name>'
  207 |       if (WITH_CSR) begin
      |                     ^~~~~
%Warning-GENUNNAMED: src/serv_1.2.1/rtl/serv_state.v:221:28: Unnamed generate block 'genblk1' (IEEE 1800-2017 27.6)
                                                           : ... Suggest assign a label with 'begin : gen_<label_name>'
  221 |  assign misalign_trap_sync = 1'b0;
      |                            ^
%Error: Exiting due to 29 warning(s)
make: *** [Makefile:16: Vserv_rf_top.mk] Error 1

ERROR: Failed to build ::serv:1.2.1 : '['make', 'Vserv_rf_top.mk']' exited with an error: 2

These are the versions of SERV, Verilator, and FuseSoC:

$ git rev-parse --short HEAD # in $workspace/fusesoc_libraries/serv
c7fc572
$ verilator --version
Verilator 5.018 2023-10-30 rev UNKNOWN.REV
$ fusesoc --version
2.2.1

I followed the steps outlined in the README:

$ python -m venv venv && . venv/bin/activate
$ pip install fusesoc
$ fusesoc library add fusesoc_cores https://github.com/fusesoc/fusesoc-cores
$ fusesoc library add serv https://github.com/olofk/serv

I think these might be relevant to the error:

I'm opening this issue because I think the author(s) intend the RTL to pass the linter, so I wanted to know if I'm missing anything obvious. Any help would be appreciated.

@olofk
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olofk commented Nov 16, 2023

Good catch. I have been running with an older version of Verilator that didn't catch this issue. It turns out that the CI also runs an older verilator which is why it wasn't discovered there either. Anyway, thanks for reporting. I'll fix.

@olofk
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olofk commented Nov 16, 2023

Ok, I pushed a fix for this now. Please let me know if that helps

@monstrous-moonshine
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Yes, works like a charm. Thanks for the fix!

@olofk olofk closed this as completed Nov 20, 2023
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