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Self Save: Fixed bugs pertaining to SPR self save.
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Commit fixes some issues with code found during integration test
    -  replacement of addi with xor instruction during self save API.
    -  fixing instruction generation for MFMSR during self save
    -  data struct updates in STOP API
    -  error RC updates for hcode image build
    -  HOMER parser updates.
    -  removed self save support for URMOR and HRMOR
    -  code changes for compilation with OPAL
    -  populating CME Image header with unsecure HOMER address.

Key_Cronus_Test=PM_REGRESS

Change-Id: I7cedcc466267c4245255d8d75c01ed695e316720
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/66580
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Cronus HW CI <cronushw-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>
Reviewed-by: RAHUL BATRA <rbatra@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
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@premsjha @op-jenkins
premsjha authored and op-jenkins committed Dec 8, 2018
1 parent ed22134 commit 1b71d5d
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Showing 6 changed files with 61 additions and 34 deletions.
1 change: 1 addition & 0 deletions import/chips/p9/procedures/hwp/lib/p9_hcode_image_defines.H
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Original file line number Diff line number Diff line change
Expand Up @@ -304,6 +304,7 @@ HCD_HDR_UINT16(g_cme_location_id, 0);
HCD_HDR_UINT16(g_cme_qm_mode_flags, 0);
HCD_HDR_UINT32(g_cme_timebase_hz, 0); //Retain next field at 8B boundary
HCD_HDR_UINT64(g_cme_cpmr_PhyAddr, 0);
HCD_HDR_UINT64(g_cme_unsec_cpmr_PhyAddr, 0);
HCD_HDR_PAD(IMG_HDR_ALIGN_SIZE);
#ifdef __ASSEMBLER__
.endm
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7 changes: 5 additions & 2 deletions import/chips/p9/procedures/hwp/lib/p9_stop_util.H
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Expand Up @@ -5,7 +5,7 @@
/* */
/* OpenPOWER HCODE Project */
/* */
/* COPYRIGHT 2015,2017 */
/* COPYRIGHT 2015,2018 */
/* [+] International Business Machines Corp. */
/* */
/* */
Expand Down Expand Up @@ -95,7 +95,10 @@ typedef struct
uint64_t cpmrMagicWord;
uint32_t buildDate;
uint32_t version;
uint8_t reserve1[7];
uint8_t reserve1[4];
uint8_t selfRestoreVer;
uint8_t stopApiVer;
uint8_t urmorFix;
uint8_t fusedModeStatus;
uint32_t cmeImgOffset;
uint32_t cmeImgLength;
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1 change: 1 addition & 0 deletions import/chips/p9/procedures/utils/stopreg/p9_cpu_reg_restore_instruction.H
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Expand Up @@ -68,6 +68,7 @@ enum
MFSPR_CONST = 339,
BLR_INST = 0x4e800020,
MTSPR_BASE_OPCODE = 0x7c0003a6,
MFSPR_BASE_OPCODE = 0x7c0002a6,
ATTN_OPCODE = 0x00000200,
OPCODE_18 = 18,
SELF_SAVE_FUNC_ADD = 0x2300,
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80 changes: 52 additions & 28 deletions import/chips/p9/procedures/utils/stopreg/p9_stop_api.C
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Original file line number Diff line number Diff line change
Expand Up @@ -54,26 +54,26 @@ namespace stopImageSection

const StopSprReg_t g_sprRegister[] =
{
{ P9_STOP_SPR_CIABR, true, 0 },
{ P9_STOP_SPR_DAWR, true, 1 },
{ P9_STOP_SPR_DAWRX, true, 2 },
{ P9_STOP_SPR_HSPRG0, true, 3 },
{ P9_STOP_SPR_LDBAR, true, 4, },
{ P9_STOP_SPR_LPCR, true, 5 },
{ P9_STOP_SPR_PSSCR, true, 6 },
{ P9_STOP_SPR_MSR, true, 7 },
{ P9_STOP_SPR_HRMOR, false, 20 },
{ P9_STOP_SPR_HID, false, 21 },
{ P9_STOP_SPR_HMEER, false, 22 },
{ P9_STOP_SPR_PMCR, false, 23 },
{ P9_STOP_SPR_PTCR, false, 24 },
{ P9_STOP_SPR_SMFCTRL, true, 28 },
{ P9_STOP_SPR_USPRG0, true, 29 },
{ P9_STOP_SPR_USPRG1, true, 30 },
{ P9_STOP_SPR_URMOR, false, 31 },
{ P9_STOP_SPR_CIABR, true, 0 },
{ P9_STOP_SPR_DAWR, true, 1 },
{ P9_STOP_SPR_DAWRX, true, 2 },
{ P9_STOP_SPR_HSPRG0, true, 3 },
{ P9_STOP_SPR_LDBAR, true, 4, },
{ P9_STOP_SPR_LPCR, true, 5 },
{ P9_STOP_SPR_PSSCR, true, 6 },
{ P9_STOP_SPR_MSR, true, 7 },
{ P9_STOP_SPR_HRMOR, false, 255 },
{ P9_STOP_SPR_HID, false, 21 },
{ P9_STOP_SPR_HMEER, false, 22 },
{ P9_STOP_SPR_PMCR, false, 23 },
{ P9_STOP_SPR_PTCR, false, 24 },
{ P9_STOP_SPR_SMFCTRL, true, 28 },
{ P9_STOP_SPR_USPRG0, true, 29 },
{ P9_STOP_SPR_USPRG1, true, 30 },
{ P9_STOP_SPR_URMOR, false, 255 },
};

const uint32_t MAX_SPR_SUPPORTED = 17;
const uint32_t MAX_SPR_SUPPORTED = 17;
const uint32_t LEGACY_CORE_SCOM_SUPPORTED = 15;
const uint32_t LEGACY_QUAD_SCOM_SUPPORTED = 63;

Expand Down Expand Up @@ -255,7 +255,7 @@ STATIC uint32_t getOriInstruction( const uint16_t i_Rs, const uint16_t i_Ra,
*/
STATIC uint32_t genKeyForSprLookup( const CpuReg_t i_regId )
{
return getOriInstruction( 0, 0, (uint16_t) i_regId );
return getOriInstruction( 24, 0, (uint16_t) i_regId );
}

//-----------------------------------------------------------------------------
Expand Down Expand Up @@ -330,7 +330,7 @@ STATIC uint32_t getMtsprInstruction( const uint16_t i_Rs, const uint16_t i_Spr )
*/
STATIC uint32_t getMfmsrInstruction( const uint16_t i_Rt )
{
uint32_t mfmsrInstOpcode = ((OPCODE_31 << 26) | (i_Rt << 21) | (MFMSR_CONST));
uint32_t mfmsrInstOpcode = ((OPCODE_31 << 26) | (i_Rt << 21) | ((MFMSR_CONST)<< 1));

return SWIZZLE_4_BYTE(mfmsrInstOpcode);
}
Expand Down Expand Up @@ -361,14 +361,19 @@ STATIC uint32_t getRldicrInstruction( const uint16_t i_Ra, const uint16_t i_Rs,

STATIC uint32_t getMfsprInstruction( const uint16_t i_Rt, const uint16_t i_sprNum )
{
uint32_t mfsprInstOpcode = 0;
mfsprInstOpcode = (( OPCODE_31 << 26 ) | ( i_Rt << 21 ) | ( i_sprNum << 11 ) | ( MFSPR_CONST << 1 ));
uint32_t mfsprInstOpcode = 0;
uint32_t temp = (( i_sprNum & 0x03FF ) << 11);
mfsprInstOpcode = (uint8_t)i_Rt << 21;
mfsprInstOpcode |= (( temp & 0x0000F800 ) << 5);
mfsprInstOpcode |= (( temp & 0x001F0000 ) >> 5);
mfsprInstOpcode |= MFSPR_BASE_OPCODE;

return SWIZZLE_4_BYTE(mfsprInstOpcode);
}

//-----------------------------------------------------------------------------

STATIC uint32_t getBranchLinkRegInstruction( )
STATIC uint32_t getBranchLinkRegInstruction(void)
{
uint32_t branchConstInstOpcode = 0;
branchConstInstOpcode = (( OPCODE_18 << 26 ) | ( SELF_SAVE_FUNC_ADD ) | 0x03 );
Expand Down Expand Up @@ -455,7 +460,7 @@ STATIC StopReturnCode_t lookUpSprInImage( uint32_t* i_pThreadSectLoc, const uint
STATIC StopReturnCode_t updateSprEntryInImage( uint32_t* i_pSprEntryLocation,
const CpuReg_t i_regId,
const uint64_t i_regData,
const SprEntryUpdateMode i_mode
const enum SprEntryUpdateMode i_mode
)
{
StopReturnCode_t l_rc = STOP_SAVE_SUCCESS;
Expand Down Expand Up @@ -615,14 +620,14 @@ STATIC StopReturnCode_t getSprRegIndexAdjustment( const uint32_t i_saveMaskPos,

do
{
if( (( i_saveMaskPos >= SPR_BIT_POS_8 ) && ( i_saveMaskPos <= SPR_BIT_POS_19 )) ||
if( (( i_saveMaskPos >= SPR_BIT_POS_8 ) && ( i_saveMaskPos <= SPR_BIT_POS_20 )) ||
(( i_saveMaskPos >= SPR_BIT_POS_25 ) && ( i_saveMaskPos <= SPR_BIT_POS_27 )) )
{
l_rc = STOP_SAVE_SPR_BIT_POS_RESERVE;
break;
}

if( (i_saveMaskPos > SPR_BIT_POS_19) && (i_saveMaskPos < SPR_BIT_POS_25 ) )
if( (i_saveMaskPos > SPR_BIT_POS_20) && (i_saveMaskPos < SPR_BIT_POS_25) )
{
*i_sprAdjIndex = 12;
}
Expand Down Expand Up @@ -1332,7 +1337,7 @@ StopReturnCode_t p9_stop_save_scom( void* const i_pImage,
* @param[in] i_pSaveSprLoc start location of save entry for a given SPR.
* @return STOP_SAVE_SUCCESS if look up succeeds, error code otherwise.
*/
StopReturnCode_t lookUpSelfSaveSpr( uint32_t i_sprBitPos, uint32_t* l_pSprSaveStart,
STATIC StopReturnCode_t lookUpSelfSaveSpr( uint32_t i_sprBitPos, uint32_t* l_pSprSaveStart,
uint32_t i_searchLength, uint32_t** i_pSaveSprLoc )
{
int32_t l_saveWordLength = (int32_t)(i_searchLength >> 2);
Expand Down Expand Up @@ -1363,7 +1368,7 @@ StopReturnCode_t lookUpSelfSaveSpr( uint32_t i_sprBitPos, uint32_t* l_pSprSaveSt
* @param[in] i_sprNum Id of the SPR for which entry needs to be edited.
* @return STOP_SAVE_SUCCESS if look up succeeds, error code otherwise.
*/
StopReturnCode_t updateSelfSaveEntry( uint32_t* i_pSaveReg, uint16_t i_sprNum )
STATIC StopReturnCode_t updateSelfSaveEntry( uint32_t* i_pSaveReg, uint16_t i_sprNum )
{
StopReturnCode_t l_rc = STOP_SAVE_SUCCESS;

Expand Down Expand Up @@ -1411,6 +1416,7 @@ StopReturnCode_t p9_stop_save_cpureg_control( void* i_pImage,
uint32_t* l_pRestoreStart = NULL;
uint32_t* l_pSprSave = NULL;
void* l_pTempLoc = NULL;
uint32_t * l_pTempWord = NULL;
SmfHomerSection_t* l_pHomer = NULL;
uint8_t l_selfRestVer = 0;

Expand Down Expand Up @@ -1440,6 +1446,11 @@ StopReturnCode_t p9_stop_save_cpureg_control( void* i_pImage,
{
l_sprPos = g_sprRegister[l_sprIndex].iv_saveMaskPos;

if( l_sprPos > MAX_SPR_BIT_POS )
{
continue;
}

//Check if a given SPR needs to be self-saved each time on STOP entry

if( i_saveRegVector & ( TEST_BIT_PATTERN >> l_sprPos ) )
Expand Down Expand Up @@ -1493,6 +1504,19 @@ StopReturnCode_t p9_stop_save_cpureg_control( void* i_pImage,
//update specific instructions of self save region to enable saving for SPR
l_rc = updateSelfSaveEntry( l_pSprSave, g_sprRegister[l_sprIndex].iv_sprId );

if( l_rc )
{
MY_ERR( "Failed to update self save instructions for 0x%08x",
(uint32_t) g_sprRegister[l_sprIndex].iv_sprId );
}

if( l_pTempLoc )
{
l_pTempWord = (uint32_t *)l_pTempLoc;
l_pTempWord++;
*l_pTempWord = getXorInstruction( 0, 0, 0 );
}

}// end if( i_saveRegVector..)
}// end for
}
Expand Down
2 changes: 0 additions & 2 deletions import/chips/p9/procedures/utils/stopreg/p9_stop_api.H
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Original file line number Diff line number Diff line change
Expand Up @@ -148,15 +148,13 @@ typedef enum
BIT_POS_LPCR = 5,
BIT_POS_PSSCR = 6,
BIT_POS_MSR = 7,
BIT_POS_HRMOR = 20,
BIT_POS_HID = 21,
BIT_POS_HMEER = 22,
BIT_POS_PMCR = 23,
BIT_POS_PTCR = 24,
BIT_POS_SMFCTRL = 28,
BIT_POS_USPRG0 = 29,
BIT_POS_USPRG1 = 30,
BIT_POS_URMOR = 31,
} SprBitPositionList_t;


Expand Down
4 changes: 2 additions & 2 deletions import/chips/p9/procedures/utils/stopreg/p9_stop_data_struct.H
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Original file line number Diff line number Diff line change
Expand Up @@ -67,9 +67,9 @@ enum
SIZE_PER_SPR_RESTORE_INST = ((4 * sizeof(uint8_t)) / sizeof(uint32_t)),
MAX_THREAD_LEVEL_SPRS = 11,
MAX_CORE_LEVEL_SPRS = 6,
MAX_SPR_BIT_POS = 31,
MAX_SPR_BIT_POS = 30,
SPR_BIT_POS_8 = 8,
SPR_BIT_POS_19 = 19,
SPR_BIT_POS_20 = 20,
SPR_BIT_POS_25 = 25,
SPR_BIT_POS_27 = 27,
};
Expand Down

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