STOP: Add URMOR RAM to CME for NDD23 SMF

Key_Cronus_Test=PM_REGRESS

Change-Id: I7b4bc42805a82cafe52f6a80a646c2554e973905
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/58953
Reviewed-by: Michael S. Floyd <mfloyd@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Cronus HW CI <cronushw-ci+hostboot@us.ibm.com>
Reviewed-by: Prem Shanker Jha <premjha2@in.ibm.com>
Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>

import/chips/p9/procedures/ppe_closed/cme/pk_app_cfg.h

@@ -57,6 +57,16 @@
 // being enabled on all other dd levels unless this override
 #define DISABLE_CME_DUAL_CAST            0
 
+// NDD23 Secure Memory Support: RAM URMOR
+#if NIMBUS_DD_LEVEL >= 23 || CUMULUS_DD_LEVEL >= 13
+
+    #define SMF_SUPPORT_ENABLE 1
+
+#else
+
+    #define SMF_SUPPORT_ENABLE 0
+
+#endif
 
 #if NIMBUS_DD_LEVEL == 20 || DISABLE_CME_DUAL_CAST == 1
     // NDD2: no catchup due to dual cast bug

import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop.h

@@ -108,6 +108,7 @@
 #define IMA_EVENT_MASK         0x20010AA8
 #define CORE_THREAD_STATE      0x20010AB3
 #define HRMOR                  0x20010AB9
+#define URMOR                  0x20010ABA
 
 #define C_SYNC_CONFIG          0x20030000
 #define C_OPCG_ALIGN           0x20030001

import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_exit.c

@@ -1140,6 +1140,20 @@ p9_cme_stop_exit()
 // Nimbus DD2+
 #else
 
+#if SMF_SUPPORT_ENABLE
+
+#if EPM_P9_TUNING
+
+            CME_PUTSCOM(URMOR, core, 0xA200000);
+
+#else
+
+            PK_TRACE_INF("Core Wakes Up, Write URMOR with HOMER address");
+            CME_PUTSCOM(URMOR, core, scom_data.value);
+
+#endif
+
+#endif
 
 #if EPM_P9_TUNING